Analog Devices AD9240EB Datasheet
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Complete 14-Bit, 10 MSPS
Monolithic A/D Converter
AD9240
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
FUNCTIONAL BLOCK DIAGRAM
VINA
CAPT
CAPB
SENSE
OTR
BIT 1
(MSB)
BIT 14
(LSB)
VREF
DVSSAVSS
AD9240
SHA
DIGITAL CORRECTION LOGIC
OUTPUT BUFFERS
VINB
1V
REFCOM
5
5
4
4
4
4
4
14
DVDDAVDD
CLK
MODE
SELECT
MDAC3
GAIN = 8
MDAC2
GAIN = 8
MDAC1
GAIN = 16
A/DA/DA/D
DRVDD
DRVSS
CML
BIAS
A/D
FEATURES
Monolithic 14-Bit, 10 MSPS A/D Converter
Low Power Dissipation: 285 mW
Single +5 V Supply
Integral Nonlinearity Error: 2.5 LSB
Differential Nonlinearity Error: 0.6 LSB
Input Referred Noise: 0.36 LSB
Complete: On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio: 77.5 dB
Spurious-Free Dynamic Range: 90 dB
Out-of-Range Indicator
Straight Binary Output Data
44-Lead MQFP
PRODUCT HIGHLIGHTS
The AD9240 offers a complete single-chip sampling 14-bit,
analog-to-digital conversion function in a 44-lead Metric Quad
Flatpack.
Low Power and Single Supply
The AD9240 consumes only 280 mW on a single +5 V power
supply.
Excellent DC Performance Over Temperature
The AD9240 provides no missing codes, and excellent temperature drift performance over the full operating temperature range.
Excellent AC Performance and Low Noise
The AD9240 provides nearly 13 ENOB performance and has an
input referred noise of 0.36 LSB rms.
Flexible Analog Input Range
The versatile onboard sample-and-hold (SHA) can be configured
for either single ended or differential inputs of varying input spans.
Flexible Digital Outputs
The digital outputs can be configured to interface with +3 V and
+5 V CMOS logic families.
Excellent Undersampling Performance
The full power bandwidth and dynamic range of the AD9240
make it well suited for Direct-IF Down Conversion extending to
45 MHz.
PRODUCT DESCRIPTION
The AD9240 is a 10 MSPS, single supply, 14-bit analog-todigital converter (ADC). It combines a low cost, high speed
CMOS process and a novel architecture to achieve the resolution
and speed of existing hybrid implementations at a fraction of the
power consumption and cost. It is a complete, monolithic ADC
with an on-chip, high performance, low noise sample-and-hold
amplifier and programmable voltage reference. An external reference can also be chosen to suit the dc accuracy and temperature
drift requirements of the application. The device uses a multistage
differential pipelined architecture with digital output error correction logic to guarantee no missing codes over the full operating
temperature range.
The input of the AD9240 is highly flexible, allowing for easy
interfacing to imaging, communications, medical and dataacquisition systems. A truly differential input structure allows
for both single-ended and differential input interfaces of varying
input spans. The sample-and-hold amplifier (SHA) is equally
suited for multiplexed systems that switch full-scale voltage
levels in successive channels as well as sampling single-channel
inputs at frequencies up to and beyond the Nyquist rate. The
AD9240 also performs well in communication systems employing Direct-IF Down Conversion, since the SHA in the differential input mode can achieve excellent dynamic performance well
beyond its specified Nyquist frequency of 5 MHz.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an
overflow condition which can be used with the most significant
bit to determine low or high overflow.
REV. A
–2–
AD9240–SPECIFICATIONS
DC SPECIFICATIONS
Parameter AD9240 Units
RESOLUTION 14 Bits min
MAX CONVERSION RATE 10 MHz min
INPUT REFERRED NOISE
VREF = 1 V 0.9 LSB rms typ
VREF = 2.5 V 0.36 LSB rms typ
ACCURACY
Integral Nonlinearity (INL) ±2.5 LSB typ
Differential Nonlinearity (DNL) ±0.6 LSB typ
±1.0 LSB max
INL
1
±2.5 LSB typ
DNL
1
±0.7 LSB typ
No Missing Codes 14 Bits Guaranteed
Zero Error (@ +25°C) 0.3 % FSR max
Gain Error (@ +25°C)
2
1.5 % FSR max
Gain Error (@ +25°C)
3
0.75 % FSR max
TEMPERATURE DRIFT
Zero Error 3.0 ppm/°C typ
Gain Error
2
20.0 ppm/°C typ
Gain Error
3
5.0 ppm/°C typ
POWER SUPPLY REJECTION 0.1 % FSR max
ANALOG INPUT
Input Span (with VREF = 1.0 V) 2 V p-p min
Input Span (with VREF = 2.5 V) 5 V p-p max
Input (VINA or VINB) Range 0 V min
AVDD V max
Input Capacitance 16 pF typ
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode) 1 Volts typ
Output Voltage Tolerance (1 V Mode) ±14 mV max
Output Voltage (2.5 V Mode) 2.5 Volts typ
Output Voltage Tolerance (2.5 V Mode) ±35 mV max
Load Regulation
4
5.0 mV max
REFERENCE INPUT RESISTANCE 5 kΩ typ
POWER SUPPLIES
Supply Voltages
AVDD +5 V (±5% AVDD
Operating)
DVDD +5 V (±5% DVDD
Operating)
DRVDD +5 V (±5% DRVDD
Operating)
Supply Current
IAVDD 50 mA max (46 mA typ)
IDRVDD 1 mA max (0.1 mA typ)
IDVDD 15 mA max (11 mA typ)
POWER CONSUMPTION 330 mW max (285 mW typ)
NOTES
1
VREF = 1 V.
2
Including internal reference.
3
Excluding internal reference.
4
Load regulation with 1 mA load current (in addition to that required by the AD9240).
Specification subject to change without notice.
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f
SAMPLE
= 10 MSPS, R
BIAS
= 2 k⍀, VREF = 2.5 V, VINB = 2.5 V,
T
MIN
to T
MAX
unless otherwise noted)
AC SPECIFICATIONS
Parameter AD9240 Units
SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D)
f
INPUT
= 500 kHz 75.0 dB min
77.5 dB typ
f
INPUT
= 1.0 MHz 77.5 dB typ
f
INPUT
= 5.0 MHz 75.0 dB typ
EFFECTIVE NUMBER OF BITS (ENOB)
f
INPUT
= 500 kHz 12.2 Bits min
12.6 Bits typ
f
INPUT
= 1.0 MHz 12.6 Bits typ
f
INPUT
= 5.0 MHz 12.2 Bits typ
SIGNAL-TO-NOISE RATIO (SNR)
f
INPUT
= 500 kHz 76.0 dB min
78.5 dB typ
f
INPUT
= 1.0 MHz 78.5 dB typ
f
INPUT
= 5.0 MHz 78.5 dB typ
TOTAL HARMONIC DISTORTION (THD)
f
INPUT
= 500 kHz –78.0 dB max
–85.0 dB typ
f
INPUT
= 1.0 MHz –85.0 dB typ
f
INPUT
= 5.0 MHz –77.0 dB typ
SPURIOUS FREE DYNAMIC RANGE
f
INPUT
= 500 kHz 90.0 dB typ
f
INPUT
= 1.0 MHz 90.0 dB typ
f
INPUT
= 5.0 MHz 80.0 dB typ
DYNAMIC PERFORMANCE
Full Power Bandwidth 70 MHz typ
Small Signal Bandwidth 70 MHz typ
Aperture Delay 1 ns typ
Aperture Jitter 4 ps rms typ
Acquisition to Full-Scale Step (0.0025%) 45 ns typ
Overvoltage Recovery Time 167 ns typ
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Parameters Symbol AD9240 Units
CLOCK INPUT
High Level Input Voltage V
IH
+3.5 V min
Low Level Input Voltage V
IL
+1.0 V max
High Level Input Current (V
IN
= DVDD) I
IH
±10 µA max
Low Level Input Current (V
IN
= 0 V) I
IL
±10 µA max
Input Capacitance C
IN
5 pF typ
LOGIC OUTPUTS (with DRVDD = 5 V)
High Level Output Voltage (I
OH
= 50 µA) V
OH
+4.5 V min
High Level Output Voltage (I
OH
= 0.5 mA) V
OH
+2.4 V min
Low Level Output Voltage (I
OL
= 1.6 mA) V
OL
+0.4 V max
Low Level Output Voltage (I
OL
= 50 µA) V
OL
+0.1 V max
Output Capacitance C
OUT
5 pF typ
LOGIC OUTPUTS (with DRVDD = 3 V)
High Level Output Voltage (I
OH
= 50 µA) V
OH
+2.4 V min
Low Level Output Voltage (I
OL
= 50 µA) V
OL
+0.7 V max
Specifications subject to change without notice.
AD9240
REV. A
–3–
(AVDD = +5 V, DVDD= +5 V, DRVDD = +5 V, f
SAMPLE
= 10 MSPS, R
BIAS
= 2 k⍀, VREF = 2.5 V, AIN = –0.5 dBFS,
AC Coupled/Differential Input, T
MIN
to T
MAX
unless otherwise noted)
(AVDD = +5 V, DVDD = +5 V, T
MIN
to T
MAX
unless otherwise noted)
AD9240
REV. A
–4–
ABSOLUTE MAXIMUM RATINGS*
With
Respect
Parameter to Min Max Units
AVDD AVSS –0.3 +6.5 V
DVDD DVSS –0.3 +6.5 V
AVSS DVSS –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
DRVDD DRVSS –0.3 +6.5 V
DRVSS AVSS –0.3 +0.3 V
REFCOM AVSS –0.3 +0.3 V
CLK AVSS –0.3 AVDD
+ 0.3 V
Digital Outputs DRVSS –0.3 DRVDD
+ 0.3 V
VINA, VINB AVSS –0.3 AVDD
+ 0.3 V
VREF AVSS –0.3 AVDD
+ 0.3 V
SENSE AVSS –0.3 AVDD
+ 0.3 V
CAPB, CAPT AVSS –0.3 AVDD
+ 0.3 V
BIAS AVSS –0.3 AVDD
+ 0.3 V
Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature
(10 sec) +300 °C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
SWITCHING SPECIFICATIONS
Parameters Symbol AD9240 Units
Clock Period
1
t
C
100 ns min
CLOCK Pulsewidth High t
CH
45 ns min
CLOCK Pulsewidth Low t
CL
45 ns min
Output Delay t
OD
8ns min
13 ns typ
19 ns max
Pipeline Delay (Latency) 3 Clock Cycles
NOTES
1
The clock period may be extended to 1 ms without degradation in specified performance @ +25 °C.
Specifications subject to change without notice.
(T
MIN
to T
MAX
with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, R
BIAS
= 2 k⍀, CL = 20 pF)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9240 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
t
CL
t
CH
t
C
t
OD
DATA 1
DATA
OUTPUT
INPUT
CLOCK
ANALOG
INPUT
S1
S2
S3
S4
Figure 1. Timing Diagram
THERMAL CHARACTERISTICS
Thermal Resistance
44-Lead MQFP
θ
JA
= 53.2°C/W
θ
JC
= 19°C/W
ORDERING GUIDE
Temperature Package Package
Model Range Description Option*
AD9240AS –40
o
C to +85oC 44-Lead MQFP S-44
AD9240EB Evaluation Board
*S = Metric Quad Flatpack.
PIN CONFIGURATION
3
4
5
6
7
1
2
10
11
8
9
40 39 3841
42
4344 36 35 3437
29
30
31
32
33
27
28
25
26
23
24
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD9240
121314 15 16 17 18 19 20 21 22
NC = NO CONNECT
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
DVSS
AVSS
DVDD
AVDD
DRVSS
DRVDD
CLK
NC
NC
NC
(LSB) BIT 14
REFCOM
VREF
SENSE
NC
AVSS
AVDD
NC
NC
OTR
BIT 1 (MSB)
BIT 2
NC
NC
NC
CML
NC
CAPT
CAPB
BIAS
NC
VINB
VINA
WARNING!
ESD SENSITIVE DEVICE
AD9240
REV. A
–5–
OVERVOLTAGE RECOVERY TIME
Overvoltage recovery time is defined as that amount of time
required for the ADC to achieve a specified accuracy after an
overvoltage (50% greater than full-scale range), measured from
the time the overvoltage signal reenters the converter’s range.
TEMPERATURE DRIFT
The temperature drift for zero error and gain error specifies the
maximum change from the initial (+25°C) value to the value at
T
MIN
or T
MAX
.
POWER SUPPLY REJECTION
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
APERTURE DELAY
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIO
S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
Thus, an effective number of bits for a device for sine wave
inputs at a given input frequency can be calculated directly
from its measured SINAD.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal and
is expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
TWO-TONE SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. Two-tone SFDR may be
reported in dBc (i.e., degrades as signal level is lowered), or in
dBFS (always related back to converter full scale).
PIN FUNCTION DESCRIPTIONS
Pin
Number Name Description
1 DVSS Digital Ground
2, 29 AVSS Analog Ground
3 DVDD +5 V Digital Supply
4, 28 AVDD +5 V Analog Supply
5 DRVSS Digital Output Driver Ground
6 DRVDD Digital Output Driver Supply
7 CLK Clock Input Pin
8–10 NC No Connect
11 BIT 14 Least Significant Data Bit (LSB)
12–23 BIT 13–BIT 2 Data Output Bits
24 BIT 1 Most Significant Data Bit (MSB)
25 OTR Out of Range
26, 27, 30 NC No Connect
31 SENSE Reference Select
32 VREF Reference I/O
33 REFCOM Reference Common
34, 38, 40,
43, 44 NC No Connect
35 BIAS* Power/Speed Programming
36 CAPB Noise Reduction Pin
37 CAPT Noise Reduction Pin
39 CML Common-Mode Level (Midsupply)
41 VINA Analog Input Pin (+)
42 VINB Analog Input Pin (–)
*See Speed/Power Programmability section.
DEFINITIONS OF SPECIFICATION
INTEGRAL NONLINEARITY (INL)
INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as “negative full scale” occurs 1/2 LSB before
the first code transition. “Positive full scale” is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16384
codes, respectively, must be present over all operating ranges.
ZERO ERROR
The major carry transition should occur for an analog value
1/2 LSB below VINA = VINB. Zero error is defined as the
deviation of the actual transition from that point.
GAIN ERROR
The first code transition should occur at an analog value 1/2 LSB
above negative full scale. The last transition should occur at an
analog value 1 1/2 LSB below the nominal full scale. Gain error
is the deviation of the actual difference between first and last
code transitions and the ideal difference between first and last
code transitions.
AD9240
REV. A
–6–
Typical Differential AC Characterization Curves/Plots
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f
SAMPLE
=
10 MSPS, R
BIAS
= 2 k⍀, TA = +25ⴗC, Differential Input)
INPUT FREQUENCY – MHz
90
85
0.1 1 20
10
55
50
65
60
80
70
75
SINAD – dB
–0.5dBFS
–6.0dBFS
–20.0dBFS
Figure 2. SINAD vs. Input Frequency
(Input Span = 5 V, V
CM
= 2.5 V)
INPUT FREQUENCY – MHz
90
85
0.1 1 20
10
55
50
65
60
80
70
75
SINAD – dB
–0.5dBFS
–6.0dBFS
–20.0dBFS
Figure 5. SINAD vs. Input Frequency
(Input Span = 2 V, V
CM
= 2.5 V)
SAMPLE RATE – MHz
–60
–65
0.1 1 10
–95
–100
–85
–90
–70
–80
–75
THD – dB
5V SPAN
2V SPAN
Figure 8. THD vs. Sample Rate
(f
IN
= 5.0 MHz, AIN = –0.5 dBFS,
V
CM
= 2.5 V)
INPUT FREQUENCY – MHz
–40
–100
0.1 1 20
10
–90
–80
–70
–50
–60
THD – dB
–0.5dBFS
–6.0dBFS
–20.0dBFS
Figure 3. THD vs. Input Frequency
(Input Span = 5 V, V
CM
= 2.5 V)
INPUT FREQUENCY – MHz
–40
–100
0.1 1 20
10
–90
–80
–70
–50
–60
THD – dB
–20.0dBFS
–6.0dBFS
–0.5dBFS
Figure 6. THD vs. Input Frequency
(Input Span = 2 V, V
CM
= 2.5 V)
AIN – dB
SFDR – dBc AND dBFS
110
20
90
60
50
40
30
80
70
–60 –50 0
–40 –30 –20 –10
5V SPAN – dBc
2V SPAN – dBFS
5V SPAN – dBFS
100
2V SPAN – dBc
Figure 9. Single Tone SFDR
(f
IN
= 5.0 MHz, VCM = 2.5 V)
FREQUENCY – MHz
AMPLITUDE – dB
0
–70
–100
0 5.0
–10
–60
–80
–90
–40
–50
–20
–30
–110
–120
1st
9th
8th
2nd
3rd
7th
6th
4th
5th
Figure 4. Typical FFT, fIN = 1.0 MHz
(Input Span = 5 V, V
CM
= 2.5 V)
2
FREQUENCY – MHz
AMPLITUDE – dB
0
–15
–30
–45
–60
–75
–90
–105
–120
–135
–150
1
3
4
5
6
7
8
9
0 5.0
Figure 7. Typical FFT, fIN = 5.0 MHz
(Input Span = 2 V, V
CM
= 2.5 V)
INPUT POWER LEVEL (
f
1
=
f
2
) – dBFS
WORST CASE SPURIOUS – dBc AND dBFS
110
60
–40 –35
0
–30 –25 –20 –15 –10 –5
105
90
85
75
65
100
95
80
70
5V SPAN – dBFS
5V SPAN – dBc
2V SPAN – dBFS
2V SPAN – dBc
Figure 10. Dual Tone SFDR
(f
1
= 0.95 MHz, f2 = 1.04 MHz,
V
CM
= 2.5 V)
AD9240
REV. A
–7–
Other Characterization Curves/Plots
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f
SAMPLE
= 10 MSPS, R
BIAS
= 2 k⍀,
TA = +25ⴗC, Single-Ended Input)
CODE
INL – LSB
3.0
–0.5
–2.0
0 16863
2.5
0.0
–1.0
–1.5
2.0
1.0
1.5
0.5
–2.5
–3.0
Figure 11. Typical INL
(Input Span = 5 V)
INPUT FREQUENCY – MHz
90
85
40
0.1 1 20
10
55
45
50
65
60
80
70
75
SINAD – dB
–0.5dBFS
–6.0dBFS
–20.0dBFS
Figure 14. SINAD vs. Input Frequency
(Input Span = 2 V, V
CM
= 2.5 V)
INPUT FREQUENCY – MHz
90
85
0.1 1 20
10
55
50
65
60
80
70
75
SINAD – dB
–0.5dBFS
–6.0dBFS
–20.0dBFS
Figure 17. SINAD vs. Input Frequency
(Input Span = 5 V, V
CM
= 2.5 V)
CODE
DNL – LSB
1.0
–0.4
–1.0
0 16383
0.8
–0.2
–0.6
–0.8
0.6
0.2
0.4
0.0
Figure 12. Typical DNL
(Input Span = 5 V)
INPUT FREQUENCY – MHz
–40
–100
0.1 1 20
10
–90
–80
–70
–50
–60
THD – dB
–0.5dBFS
–6.0dBFS
–20.0dBFS
Figure 15. THD vs. Input Frequency
(Input Span = 2 V, V
CM
= 2.5 V)
INPUT FREQUENCY – MHz
–40
–100
0.1 1 20
10
–90
–80
–70
–50
–60
THD – dB
–0.5dBFS
–6.0dBFS
–20dBFS
Figure 18. THD vs. Input Frequency
(Input Span = 5 V, V
CM
= 2.5 V)
N–1
13484335
1414263
1482053
N N+1
HITS
CODE
Figure 13. “Grounded-Input”
Histogram (Input Span = 5 V)
FREQUENCY – MHz
0
–10
1 10 100
–70
–80
–50
–60
–20
–40
–30
AMPLITUDE – dB
Figure 16. CMR vs. Input Frequency
(Input Span = 2 V, V
CM
= 2.5 V)
TEMPERATURE – 8C
V
REF
ERROR – V
0.01
–0.004
–0.01
–60 –40 140–20 0 20 40 60 80 100 120
0.008
–0.002
–0.006
–0.008
0.002
0
0.006
0.004
Figure 19. Typical Voltage Reference
Error vs. Temperature
AD9240
REV. A
–8–
CLOCK FREQUENCY – MHz
SINAD – dB
80
20
12010
70
60
50
40
30
10
0
R
BIAS
= 10kV
R
BIAS
= 20kV
R
BIAS
= 200kV
R
BIAS
=
4kV
R
BIAS
=
2kV
Figure 21. SINAD vs. Clock Frequency for Varying R
BIAS
Values (VCM = 2.5 V, AIN = –0.5 dB, 5 V Span, fIN = f
CLK
/2)
CLOCK FREQUENCY – MHz
POWER – mW
400
100
2204 6 8 10 12 14 16 18
350
300
250
200
150
R
BIAS
= 1.7kV
R
BIAS
= 2kV
R
BIAS
= 2.5kV
R
BIAS
= 3.3kV
R
BIAS
= 5kV
R
BIAS
= 10kV
R
BIAS
= 100kV
Figure 22. Power Dissipation vs. Clock Frequency for
Varying R
BIAS
Values
ANALOG INPUT AND REFERENCE OVERVIEW
Figure 23, a simplified model of the AD9240, highlights the relationship between the analog inputs, VINA, VINB, and the reference voltage, VREF. Like the voltage applied to the top of
the resistor ladder in a flash A/D converter, the value VREF defines
the maximum input voltage to the A/D core. The minimum input
voltage to the A/D core is automatically defined to be –VREF.
V
CORE
VINA
VINB
+VREF
–VREF
A/D
CORE
14
AD9240
Figure 23. Equivalent Functional Input Circuit
INTRODUCTION
The AD9240 uses a four-stage pipeline architecture with a
wideband input sample-and-hold amplifier (SHA) implemented
on a cost-effective CMOS process. Each stage of the pipeline,
excluding the last, consists of a low resolution flash A/D connected to a switched capacitor DAC and interstage residue
amplifier (MDAC). The residue amplifier amplifies the difference between the reconstructed DAC output and the flash input
for the next stage in the pipeline. One bit of redundancy is used
in each of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash A/D.
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. This means that while the
converter is capable of capturing a new input sample every clock
cycle, it actually takes three clock cycles for the conversion to be
fully processed and appear at the output. This latency is not a
concern in most applications. The digital output, together with
the out-of-range indicator (OTR), is latched into an output
buffer to drive the output pins. The output drivers can be configured to interface with +5 V or +3.3 V logic families.
The AD9240 uses both edges of the clock in its internal timing
circuitry (see Figure 1 and specification page for exact timing
requirements). The A/D samples the analog input on the rising
edge of the clock input. During the clock low time (between the
falling edge and rising edge of the clock), the input SHA is in
the sample mode; during the clock high time it is in the hold
mode. System disturbances just prior to the rising edge of the
clock and/or excessive clock jitter may cause the input SHA to
acquire the wrong value, and should be minimized.
Speed/Power Programmability
The AD9240’s maximum conversion rate and associated power
dissipation can be set using the part’s BIAS pin. A simplified
diagram of the on-chip circuitry associated with the BIAS pin is
shown in Figure 20.
AD9240
BIAS
R
BIAS
I
FIXED
ADC
BIAS
Figure 20.
The value of R
BIAS
can be varied over a limited range to set the
maximum sample rate and power dissipation of the AD9240. A
typical plot of S/(N+D) @ f
IN
= Nyquist vs. f
CLK
at varying
R
BIAS
is shown in Figure 21. A similar plot of power vs. f
CLK
at varying R
BIAS
is shown in Figure 22. These plots indicate
typical performance vs. R
BIAS
. Note that all other plots and
specifications in this data sheet reflect performance at a fixed
R
BIAS
= 2 kΩ.
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