ANALOG DEVICES AD9239 Service Manual

Quad, 12-Bit, 170 MSPS/210 MSPS/250 MSPS

A

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FEATURES

4 ADCs in 1 package Coded serial digital outputs with ECC per channel On-chip temperature sensor

−95 dB channel-to-channel crosstalk SNR = 65 dBFS with AIN = 85 MHz at 250 MSPS SFDR = 77 dBc with AIN = 85 MHz at 250 MSPS Excellent linearity

DNL = ±0.3 LSB (typical)

INL = ±0.7 LSB (typical) 780 MHz full power analog bandwidth Power dissipation = 380 mW per channel at 250 MSPS

1.25 V p-p input voltage range, adjustable up to 1.5 V p-p

1.8 V supply operation Clock duty cycle stabilizer Serial port interface features

Power-down modes

Digital test pattern enable

Programmable header

Programmable pin functions (PGMx, PDWN)

APPLICATIONS

Communication receivers Cable head end equipment/M-CMTS Broadband radios Wireless infrastructure transceivers Radar/military-aerospace subsystems Test equipment

Serial Output 1.8 V ADC

AD9239

FUNCTIONAL BLOCK DIAGRAM

VDD PDWN DRVDD DRGND

AD9239

VIN + A DOUT + A

VIN – A

VCM A

VIN + B

VIN – B

VCM B

VIN + C DOUT + C

VIN – C

VCM C

VIN + D

VIN – D

VCM D

RBIAS

TEMPOUT

BUF

REFERENCE

SCLK SDI/

SHA

SDIO

PIPELINE

SERIAL

PORT

ADC

SDO CSB

Figure 1.

12

DATA RATE MULTIPLIER

CLK+ CLK–

CML DRIVERS

DATA SERIALIZE R, ENCODER, AND

CHANNEL A

CHANNEL B

CHANNEL C

CHANNEL D

DOUT – A

DOUT + B

DOUT – B

DOUT – C

DOUT + D

DOUT – D

PGM3

PGM2

PGM1

PGM0

RESET

06980-001

GENERAL DESCRIPTION

The AD9239 is a quad, 12-bit, 250 MSPS analog-to-digital converter (ADC) with an on-chip temperature sensor and a high speed serial interface. It is designed to support digitizing high frequency, wide dynamic range signals with an input bandwidth up to 780 MHz. The output data are serialized and presented in packet format, consisting of channel-specific information, coded samples, and error correction code.

The ADC requires a single 1.8 V power supply and the input clock may be driven differentially with a sine wave, LVPECL, TTL, or LVDS. A clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. The on-chip reference eliminates the need for external decoupling and can be adjusted by means of SPI control.

Various power-down and standby modes are supported. The ADC typically consumes 145 mW per channel with the digital link still in operation when standby operation is enabled.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Fabricated on an advanced CMOS process, the AD9239 is available in a Pb-free/RoHS-compliant, 72-lead LFCSP package. It is specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Four ADCs are contained in a small, space-saving package.

2. An on-chip PLL allows users to provide a single ADC

sampling clock, and the PLL distributes and multiplies up to produce the corresponding data rate clock.

3. Coded data rate supports up to 4.0 Gbps per channel.

Coding includes scrambling to ensure proper dc common mode, embedded clock, and error correction.

4. The AD9239 operates from a single 1.8 V power supply.

5. Flexible synchronization schemes and programmable

mode pins.

6. On-chip temperature sensor.

AD9239

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REVISION HISTORY

10/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

AD9239

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SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T otherwise noted.

Table 1.

AD9239BCPZ-170 AD9239BCPZ-210 AD9239BCPZ-250 Parameter

1

Temp Min Typ Max Min Typ Max Min Typ Max Unit

RESOLUTION 12 12 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Guaranteed

Offset Error 25°C −2 ±12 −2 ±12 −2 ±12 mV

Offset Matching 25°C 4 12 4 12 4 12 mV

Gain Error 25°C −2.8 +1 +4.7 −2.8 +1 +4.7 −2.8 +1 +4.7 % FS

Gain Matching 25°C 0.9 2.7 0.9 2.7 0.9 2.7 % FS

Differential Nonlinearity (DNL) Full ±0.28 ±0.6 ±0.28 ±0.6 ±0.3 ±0.6 LSB

Integral Nonlinearity (INL) Full ±0.45 ±0.9 ±0.7 ±1.3 ±0.7 ±1.3 LSB

ANALOG INPUTS

Differential Input Voltage Range

Common-Mode Voltage Full 1.4 1.4 1.4 V

Input Capacitance 25°C 2 2 2 pF

Input Resistance Full 4.3 4.3

Analog Bandwidth, Full Power Full 780 780 780 MHz

Voltage Common Mode (VCMx)

Voltage Output Full 1.4 1.44 1.5 1.4 1.44 1.5 1.4 1.44 1.5 V

Current Drive Full 1 1 1 mA

Temperature Sensor Output −1.12 −1.12 −1.12 mV/°C

Voltage Output Full 739 737 734 mV

Current Drive Full 10 10 10 µA

POWER SUPPLY

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

I

Full 535 570 610 650 725 775 mA

AVDD

I

Full 98 105 111 120 123 133 mA

DRVDD

Total Power Dissipation

(Including Output Drivers) Power-Down Dissipation Full 3 3 3 mW Standby Dissipation

2

Full 152 173 195 mW

CROSSTALK Full −95 −95 −95 dB

Overrange Condition

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.

2

AVDD/DRVDD, with link established.

3

Overrange condition is specified with 6 dB above the full-scale input range.

3

Full −90 −90 −90 dB

= −40°C, T

MIN

2

Full 1.25 1.25 1.25 V p-p

= +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless

MAX

4.3

kΩ

Full 1.139 1.215 1.298 1.386 1.526 1.634 W

Rev. 0 | Page 3 of 40

AD9239

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AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T otherwise noted.

Table 2.

AD9239BCPZ-170 AD9239BCPZ-210 AD9239BCPZ-250 Parameter

1

Temp Min Typ Max Min Typ Max Min Typ Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 9.7 MHz 25°C 64.5 dB fIN = 84.3 MHz Full 63.5 64.5 63.2 64.2 63.1 64.1 dB fIN = 170.3 MHz 25°C 63.9 dB fIN = 240.3 MHz 25°C 64.1 63.2 63.3 dB

SIGNAL-TO-NOISE RATIO (SINAD)

fIN = 9.7 MHz 25°C 64.2 dB fIN = 84.3 MHz Full 63.3 64.4 62.8 63.9 62.8 63.8 dB fIN = 170.3 MHz 25°C 63.1 dB fIN = 240.3 MHz 25°C 63.9 63 63.1 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 9.7 MHz 25°C 10.4 Bits fIN = 84.3 MHz Full 10.2 10.4 10.1 10.3

fIN = 170.3 MHz 25°C 10.2 Bits fIN = 240.3 MHz 25°C 10.3 10.2 10.2 Bits

WORST HARMONIC (SECOND)

fIN = 9.7 MHz 25°C 90 dBc fIN = 84.3 MHz Full 87.5 78.6 86 77 86 74.5 dBc fIN = 170.3 MHz 25°C 76 dBc fIN = 240.3 MHz 25°C 82 80 82 dBc

WORST HARMONIC (THIRD)

fIN = 9.7 MHz 25°C 78 dBc fIN = 84.3 MHz Full 79 74 76 72.6 76 72.5 dBc fIN = 170.3 MHz 25°C 74 dBc fIN = 240.3 MHz 25°C 84 77 80 dBc

WORST OTHER (EXCLUDING SECOND OR THIRD)

fIN = 9.7 MHz 25°C 85 dBc fIN = 84.3 MHz Full 96 86 90 83.7 94 83.6 dBc fIN = 170.3 MHz 25°C 85 dBc fIN = 240.3 MHz 25°C 88 88 85 dBc

TWO-TONE INTERMOD DISTORTION (IMD)

f

= 140.2 MHz, f

IN1

= 141.3 MHz,

IN2

AIN1 and AIN2 = −7.0 dBFS

f

= 170.2 MHz, f

IN1

= 171.3 MHz,

IN2

AIN1 and AIN2 = −7.0 dBFS

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.

2

Tested at 210 MSPS and 250 MSPS only.

MIN

2

= −40°C, T

= +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless

MAX

10.1

10.3 Bits

4

25°C 78 77 76 dBc

25°C 77 76 dBc

Rev. 0 | Page 4 of 40

AD9239

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DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T otherwise noted.

Table 3.

AD9239BCPZ-170 AD9239BCPZ-210 AD9239BCPZ-250 Parameter

CLOCK INPUTS (CLK+, CLK–)

LOGIC INPUTS (PDWN, CSB, SDI/

LOGIC OUTPUTS (SDO)

DIGITAL OUTPUTS

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.

2

Specified for 13 SDI/SDIO pins sharing the same connection.

1

Logic Compliance Full LVPECL/LVDS/CMOS LVPECL/LVDS/CMOS LVPECL/LVDS/CMOS Differential Input Voltage Full 0.2 6 0.2 6 0.2 6 V p-p Input Voltage Range Full AVDD −

Internal Common-Mode Bias Full 1.2 1.2 1.2 V Input Common-Mode Voltage Full 1.1 AVDD 1.1 AVDD 1.1 AVDD V High Level Input Voltage (VIH) Full 1.2 3.6 1.2 3.6 1.2 3.6 V Low Level Input Voltage (VIL) Full 0 0.8 0 0.8 0 0.8 V High Level Input Current (IIH) Full −10 +10 −10 +10 −10 +10 µA Low Level Input Current (IIL) Full −10 +10 −10 +10 −10 +10 µA Differential Input Resistance 25°C 16 20 24 16 20 24 16 20 24 kΩ Input Capacitance 25°C 4 4 4 pF

2

SDIO, SCLK, RESET, PGMx) Logic 1 Voltage Full 0.8 ×

Logic 0 Voltage Full 0.2 ×

Logic 1 Input Current (CSB) Full 0 0 0 µA Logic 0 Input Current (CSB) Full −60 −60 −60 µA Logic 1 Input Current

(SCLK, PDWN, SDI/SDIO,

RESET, PGMx) Logic 0 Input Current

(SCLK, PDWN, SDI/SDIO,

RESET, PGMx) Input Resistance 25°C 30 30 30 kΩ Input Capacitance 25°C 4 4 4 pF

Logic 1 Voltage Full 1.2 AVDD +

Logic 0 Voltage Full 0 0.3 0 0.3 0 0.3 V

(DOUT + x, DOUT − x) Logic Compliance Current

Differential Output Voltage Full 0.8 0.8 0.8 V Common-Mode Level Full DRVDD/2 DRVDD/2 DRVDD/2 V

= −40°C, T

MIN

Temp Min Typ Max Min Typ Max Min Typ Max Unit

0.3

AVDD

Full 55 55 55 µA

Full 0 0 0 µA

= +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless

MAX

AVDD +

1.6

0.8 ×

AVDD

0.3

Current mode logic

AVDD −

0.3

AVDD

0.2 ×

1.2 AVDD +

AVDD +

1.6

0.8 ×

AVDD

0.3

Current mode logic

AVDD −

0.3

AVDD

0.2 ×

1.2 AVDD +

AVDD +

V

mode logic

1.6

V

AVDD

V

0.3

Rev. 0 | Page 5 of 40

AD9239

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SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T otherwise noted.

Table 4.

AD9239BCPZ-170 AD9239BCPZ-210 AD9239BCPZ-250 Parameter

CLOCK

DATA OUTPUT PARAMETERS

TERMINATION CHARACTERISTICS

APERTURE

OUT-OF-RANGE RECOVERY TIME 25°C 1 1 1 CLK cycles

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.

2

Receiver dependent.

3

See the section. Digital Start-Up Sequence

1

Clock Rate Full 170 100 210 100 250 100 MSPS Clock Pulse Width High (tEH) Full 2.65 2.9 2.15 2.4 1.8 2.0 ns Clock Pulse Width Low (tEL) Full 2.65 2.9 2.15 2.4 1.8 2.0 ns

Data Output Period or UI

(DOUT + x, DOUT − x) Data Output Duty Cycle 25°C 50 50 50 % Data Valid Time 25°C 0.8 0.8 0.8 UI PLL Lock Time (t Wake-Up Time (Standby) 25°C 250 250 250 ns Wake-Up Time (Power-Down) Pipeline Latency Full 40 40 40 CLK cycles Data Rate per Channel (NRZ) 25°C 2.72 3.36 4.0 Gbps Deterministic Jitter 25°C 10 10 10 ps max Random Jitter 25°C 6 6 6 ps rms Channel-to-Channel Bit Skew 25°C 0 0 0 sec Channel-to-Channel Packet Skew Output Rise/Fall Time 25°C 50 50 50 ps

Differential Termination Resistance 25°C 100 100 100 Ω

Aperture Delay (tA) 25°C 1.2 1.2 1.2 ns Aperture Uncertainty (Jitter) 25°C 0.2 0.2 0.2 ps rms

) 25°C 4 4 4 µs

LOCK

2

= −40°C, T

MIN

Temp Min Typ Max Min Typ Max Min Typ Max Unit

Full 1/(16 × f

25°C 50 50 50 s

3

25°C +1 +1 +1 CLK cycles

= +85°C, 1.25 V p-p differential input, AIN = –1.0 dBFS, DCS enabled, unless

MAX

) 1/(16 × f

CLK

) 1/(16 × f

CLK

) sec

CLK

Rev. 0 | Page 6 of 40

AD9239

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TIMING DIAGRAM

SAMPLE

N + 1

N

ANALOG

INPUT SIGNAL

RATE CLOCK

SAMPLE

N – 40

N – 39

N – 38

N – 37

SAMPLE

RATE CLOCK

SERIAL

DATA OUT

SERIAL CODED SAMPLES: N – 40, N – 39, N – 38, N – 37 ...

... ... ...

8-BIT HEADER

CHANNEL ID

Figure 2. Timing Diagram

...

DATA PACKET 1

(64 BITS)

48-BIT ADC

DATA-WORD

...

...... ...

8-BIT ERROR

CORRECTION

06980-002

Table 1. Packet Protocol

Bits[64:57] Bits[56:45] Bits[44:33] Bits[32:21] Bits[20:9] Bits[8:1]

Header Data 1 Data 2 Data 3 Data 4 ECC

(8 bits MSB first) (12 bits MSB first) (12 bits MSB first) (12 bits MSB first) (12 bits MSB first) (8 bits MSB first)

Rev. 0 | Page 7 of 40

AD9239

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ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Electrical

AVDD to AGND −0.3 V to +2.0 V DRVDD to DRGND −0.3 V to +2.0 V AGND to DRGND −0.3 V to +0.3 V AVDD to DRVDD −2.0 V to +2.0 V DOUT ± x to DRGND −0.3 V to DRVDD + 0.3 V SDO, SDI/SDIO, CLK± , VIN ± x,

VCMx, TEMPOUT, RBIAS to AGND

SCLK, CSB, PGMx, RESET,

PDWN to AGND

Environmental

Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature

(Soldering 10 sec)

Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

−0.3 V to AVDD + 0.3 V

300°C

THERMAL RESISTANCE

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package.

Table 6. Thermal Resistance

Package Type θJA θJB θJC Unit

72-Lead LFCSP (CP-72-3) 16.2 7.9 0.6 °C/W

Typical θJA, θJB, and θJC values are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θ

. In addition, metal in direct contact with the package leads

JA

from metal traces and through holes, ground, and power planes reduces the θ

.

JA

ESD CAUTION

Rev. 0 | Page 8 of 40

AD9239

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PIN CONFIGURATION AND FUNCTION DESCRIPTION

NC

AVDD

VCM C

AVDD

VIN – C

VIN + C

AVDD

AVDDNCAVDD

AVDD

VIN + B

VIN – B

AVDD

VCM B

AVDD

NC

TEMPOUT

RBIAS

AVDD

NC NC

AVDD

VCM D

AVDD VIN – D VIN + D

AVDD

CLK–

7271706968676665646362616059585756

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17CLK+ 18AVDD

PIN 1 INDICAT OR

PIN 0 = EPAD = AGND

AD9239

TOP VIEW

(Not to Scale)

55

54

NC

53

PGM0

52

PGM1

51

PGM2

50

PGM3

49

NC

48

AVDD

47

VCM A

46

AVDD

45

VIN – A

44

VIN + A

43

AVDD

42

AVDD

41

AVDD

40

CSB

39

SCLK

38

SDI/SDIO

37

SDO

192021222324252627282930313233

NC

AVDD

RESET

DRVDD

DRGND

DOUT – D

DOUT – C

DOUT + D

DOUT + C

NOTES

1. NC = NO CONNECT .

2. THE EXPO SED PADDLE MUST BE SOLDERED T O THE GRO UND PLANE FOR THE L FCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE CUSTOMER BOARD INCREASES T HE RELIABIL ITY OF THE SOL DER JOINTS, MAXIMIZ ING THE THERMAL CAPABILITY O F THE PACKAGE.

DOUT + B

DOUT – B

34

35PDWN

36NC

DRVDD

DRGND

DOUT – A

DOUT + A

06980-004

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

0 AGND Analog Ground (Exposed Paddle). 23, 34 DRGND Digital Output Driver Ground. 4, 7, 9, 12, 13, 14,

AVDD 1.8 V Analog Supply. 15, 18, 20, 21, 41, 42, 43, 46, 48, 55, 57, 60, 61, 62, 64, 65, 66, 69, 71

24, 33 DRVDD 1.8 V Digital Output Driver Supply. 2 TEMPOUT Output Voltage to Monitor Temperature. 3 RBIAS External Resistor to Set the Internal ADC Core Bias Current. 8 VCM D Common-Mode Output Voltage Reference (0.5 × AVDD). 10 VIN − D ADC D Analog Complement. 11 VIN + D ADC D Analog True. 16 CLK− Input Clock Complement. 17 CLK+ Input Clock True. 22 RESET Digital Output Timing Reset. 25 DOUT + D ADC D True Digital Output. 26 DOUT − D ADC D Complement Digital Output. 27 DOUT + C ADC C True Digital Output. 28 DOUT − C ADC C Complement Digital Output. 29 DOUT + B ADC B True Digital Output. 30 DOUT − B ADC B Complement Digital Output. 31 DOUT + A ADC A True Digital Output. 32 DOUT − A ADC A Complement Digital Output. 35 PDWN Power-Down.

Rev. 0 | Page 9 of 40

AD9239

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Pin No. Mnemonic Description

37 SDO Serial Data Output. Used for 4-wire SPI interface. 38 SDI/SDIO Serial Data Input/Serial Data IO for 3-Wire SPI Interface. 39 SCLK Serial Clock. 40 CSB Chip Select Bar. 44 VIN + A ADC A Analog Input True. 45 VIN − A ADC A Analog Input Complement. 47 VCM A Common-Mode Output Voltage Reference (0.5 × AVDD). 50 PGM3 Optional Pin to be Programmed by Customer. 51 PGM2 Optional Pin to be Programmed by Customer. 52 PGM1 Optional Pin to be Programmed by Customer. 53 PGM0 Optional Pin to be Programmed by Customer. 56 VCM B Common-Mode Output Voltage Reference (0.5 × AVDD). 58 VIN − B ADC B Analog Input Complement. 59 VIN + B ADC B Analog Input True. 67 VIN + C ADC C Analog Input True. 68 VIN − C ADC C Analog Input Complement. 70 VCM C Common-Mode Output Voltage Reference (0.5 × AVDD). 1, 5, 6, 19, 36,

49, 54, 63, 72

NC No Connection.

Rev. 0 | Page 10 of 40

AD9239

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TYPICAL PERFORMANCE CHARACTERISTICS

0

AIN = –1.0dBF S SNR = 64.88dB ENOB = 10.49 BI TS

–20

SFDR = 77.57d Bc

–20

0

AIN = –1.0dBFS SNR = 63.13dB ENOB = 10.19 BI TS SFDR = 76.07dBc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 10 20304050607080

FREQUENCY (MHz)

Figure 4. Single-Tone 32k FFT with fIN = 84.3 MHz, f

0

AIN = –1.0dBF S SNR = 63.95dB ENOB = 10.33 BI TS

–20

SFDR = 78.90dBc

–40

–60

–80

AMPLITUDE (dBFS)

–100

= 170 MSPS

SAMPLE

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

020406080100

06980-059

Figure 7. Single-Tone 32k FFT with fIN = 240.3 MHz, f

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

FREQUENCY (MHz)

= 210 MSPS

SAMPLE

AIN = –1.0dBF S SNR = 64.62dB ENOB = 10.44 BI TS SFDR = 75.48d Bc

06980-062

–120

0 10 20304050607080

FREQUENCY (MHz)

Figure 5. Single-Tone 32k FFT with fIN = 240.3 MHz, f

0

AIN = –1.0dBFS SNR = 64.65dB ENOB = 10.44 BI TS

–20

SFDR = 77.54d Bc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 20 40 60 80 100

FREQUENCY (MHz)

Figure 6. Single-Tone 32k FFT with fIN = 84.3 MHz, f

SAMPLE

= 170 MSPS

= 210 MSPS

–120

06980-060

0 20 40 60 80 100 120

Figure 8. Single-Tone 32k FFT with fIN = 10.3 MHz, f

0

AIN = –1.0dBFS SNR = 64.50dB ENOB = 10.42 BI TS

–20

SFDR = 77.97dBc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

06980-061

0 20 40 60 80 100 120

Figure 9. Single-Tone 32k FFT with fIN = 84.3 MHz, f

FREQUENCY (MHz)

SAMPLE

06980-063

= 250 MSPS

06980-064

= 250 MSPS

Rev. 0 | Page 11 of 40

AD9239

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0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 20 40 60 80 100 120

FREQUENCY (MHz)

Figure 10. Single-Tone 32k FFT with fIN = 171.3 MHz, f

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 20 40 60 80 100 120

FREQUENCY (MHz)

Figure 11. Single-Tone 32k FFT with fIN = 240.3 MHz, f

AIN = –1.0dBFS SNR = 63.90dB ENOB = 10.32 BI TS SFDR = 73.10d Bc

= 250 MSPS

SAMPLE

AIN = –1.0dBFS SNR = 63.41dB ENOB = 10.24 BI TS SFDR = 77.49dBc

= 250 MSPS

SAMPLE

90

88

86

84

82

80

78

SFDR (dBFS)

76

74

72

70

06980-065

170MSPS

210MSPS

50 70 90 110 130 150 170 190 210 230 250

ENCODE (MSPS)

250MSPS

06980-068

Figure 13. SFDR vs. Encode, fIN = 84.3 MHz

100

90

80

70

60

50

40

SNR/SFDR (dB)

30

20

10

0

–90 –80 –70 –60 –50 –40 –30 –20 –10 0

06980-066

Figure 14. SNR/SFDR vs. Analog Input Level, fIN = 84.3 MHz, f

SFDR (dBFS)

SNR (dBFS)

SFDR (dB)

ANALOG INPUT LEVEL (dBFS)

SNR (dB)

SAMPLE

06980-069

= 170 MSPS

70

69

68

170MSPS

250MSPS

210MSPS

ENCODE (MSPS)

06980-067

Figure 15. SNR/SFDR vs. Analog Input Level, fIN = 84.3 MHz, f

67

66

65

64

SNR (dBFS)

63

62

61

60

50 70 90 110 130 150 170 190 210 230 250

Figure 12. SNR vs. Encode, fIN = 84.3 MHz

Rev. 0 | Page 12 of 40

100

90

80

70

60

50

40

SNR/SFDR (dB)

30

20

10

0

–90 –80 –70 –60 –50 –40 –30 –20 –10 0

SFDR (dBFS)

SNR (dBFS)

SFDR (dB)

SNR (dB)

ANALOG INPUT LEVEL (dBFS)

SAMPLE

06980-070

= 210 MSPS

ANALOG DEVICES AD9239 Service Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING DIAGRAM

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTION

TYPICAL PERFORMANCE CHARACTERISTICS