ANALOG DEVICES AD9237 Service Manual
12-Bit, 20 MSPS/40 MSPS/65 MSPS
FEATURES
Ultralow power
85 mW at 20 MSPS
135 mW at 40 MSPS
190 mW at 65 MSPS
SNR = 66 dBc to Nyquist at 65 MSPS
SFDR = 80 dBc to Nyquist at 65 MSPS
DNL = ±0.7 LSB
Differential input with 500 MHz bandwidth
Flexible analog input: 1 V p-p to 4 V p-p range
Offset binary, twos complement, or gray code data formats
Output enable pin
2-step power-down
Full power-down and sleep mode
Clock duty cycle stabilizer
APPLICATIONS
Ultrasound and medical imaging
Battery-powered instruments
Hand-held scope meters
Low cost digital oscilloscopes
Low power digital still cameras and copiers
Low power communications
GENERAL DESCRIPTION
The AD9237 is a family of monolithic, single 3 V supply, 12-bit,
20 MSPS/40 MSPS/65 MSPS analog-to-digital converters
(ADC). This family features a high performance sample-andhold amplifier (SHA) and voltage reference. The AD9237 uses a
multistage differential pipelined architecture with output error
correction logic to provide 12-bit accuracy at 20 MSPS/
40 MSPS/65 MSPS data rates and guarantees no missing codes
over the full operating temperature range.
With significant power savings over previously available ADCs,
the AD9237 is suitable for applications in imaging and medical
ultrasound.
Fabricated on an advanced CMOS process, the AD9237 is
available in a 32-lead LFCSP and is specified over the industrial
temperature range (−40°C to +85°C).
3 V Low Power A/D Converter
AD9237
FUNCTIONAL BLOCK DIAGRAM
AVDD
VIN+
VIN–
REFT
REFB
MODE2
VREF
SENSE
SHA
REF
SELECT
A/D
AGND
MDAC1
4 15
CORRECTION LOGIC
OUTPUT BUFFERS
AD9237
CLOCK
DUTY CYCLE
STABILIZER
0.5V
CLK PDWN MODE
Figure 1.
PRODUCT HIGHLIGHTS
1. Operating at 65 MSPS, the AD9237 consumes a low 190 mW
at 65 MSPS, 135 mW at 40 MSPS, and 85 mW at 20 MSPS.
2. Power scaling reduces the operating power further when
running at lower speeds.
3. The AD9237 operates from a single 3 V power supply and
features a separate digital output driver supply to
accommodate 2.5 V and 3.3 V logic families.
4. The patented SHA input maintains excellent performance
for input frequencies beyond Nyquist and can be configured
for single-ended or differential operation.
5. The AD9237 is optimized for selectable and flexible input
ranges from 1 V p-p to 4 V p-p.
6. An output enable pin allows for multiplexing of the outputs.
7. Two-step power-down supports a standby mode in addition
to a power-down mode.
8. The OTR output bit indicates when the signal is beyond the
selected input range.
9. The clock duty cycle stabilizer (DCS) maintains converter
performance over a wide range of clock pulse widths.
DRVDD
10-STAGE
1 1/2-BIT
PIPELINE
12
MODE
SELECT
A/D
3
OE
OTR
D11
D0
DGND
05455-001
Rev. A
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Fax: 781.461.3113 © 2005–2010 Analog Devices, Inc. All rights reserved.
AD9237
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions ..............................8
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
DC Specifications ......................................................................... 3
Digital Specifications ................................................................... 4
AC Specifications .......................................................................... 4
Switching Specifications .............................................................. 5
Timing Diagram ............................................................................... 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
REVISION HISTORY
Terminology .......................................................................................9
Equivalent Circuits ......................................................................... 10
Typical Performance Characteristics ........................................... 11
Applying the AD9237 .................................................................... 16
Theory of Operation .................................................................. 16
Analog Input and Reference Overview ................................... 16
Voltage Reference ....................................................................... 18
Clock Input Considerations ...................................................... 19
Power Dissipation, Power Scaling, and Standby Mode ......... 19
Digital Outputs ........................................................................... 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
5/10—Rev. 0 to Rev. A
Changes to Product Highlights Section ......................................... 1
Changes to Pipeline Delay Parameter in Table 4 .......................... 5
Changes to Figure 2 .......................................................................... 6
Changes to Figure 3 and Table 6 ..................................................... 8
10/05—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD9237
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, −0.5 dBFS input, 1.0 V internal reference, T
unless otherwise noted.
Table 1.
AD9237BCP-20 AD9237BCP-40 AD9237BCP-65
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 12 12 12 Bits
ACCURACY
No Missing Codes Guaranteed 12 12 12 Bits
Offset Error ±1.30 ±1.95 ±1.30 ±1.95 ±1.30 ±1.95 % FSR
Gain Error1 ±0.70 ±2.10 ±0.75 ±2.10 ±1.05 ±2.25 % FSR
Differential Nonlinearity (DNL)2 ±0.70 ±0.95 ±0.70 ±0.95 −1.00 ±0.70 +1.25 LSB
Integral Nonlinearity (INL)2 ±0.90 ±1.35 ±0.90 ±1.35 ±0.90 ±2.00 LSB
TEMPERATURE DRIFT
Offset Error ±2 ±2 ±2 ppm/°C
Gain Error1 ±12 ±12 ±12 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) ±5 ±25 ±5 ±25 ±5 ±25 mV
Load Regulation @ 1.0 mA 0.8 0.8 0.8 mV
Output Voltage Error (0.5 V Mode) ±2.5 ±2.5 ±2.5 mV
Load Regulation @ 0.5 mA 0.1 0.1 0.1 mV
Reference Input Resistance 7 7 7 kΩ
INPUT REFERRED NOISE
VREF = 0.5 V 1.35 1.35 1.35 LSB rms
VREF = 1.0 V 0.70 0.70 0.70 LSB rms
ANALOG INPUT
Input Span
VREF = 0.5 V; MODE2 = 0 V 1 1 1 V p-p
VREF = 1.0 V; MODE2 = 0 V 2 2 2 V p-p
VREF = 0.5 V; MODE2 = AVDD 2 2 2 V p-p
VREF = 1.0 V; MODE2 = AVDD 4 4 4 V p-p
Input Capacitance3 7 7 7 pF
POWER SUPPLIES
Supply Voltages
AVDD 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V
DRVDD 2.25 2.5 3.6 2.25 2.5 3.6 2.25 2.5 3.6 V
Supply Current
IAVDD2 30.5 45.5 64.5 mA
IDRVDD2 3.0 4.5 5.5 mA
PSRR ±0.01 ±0.01 ±0.01 % FSR
POWER CONSUMPTION
DC Input4 85 135 190 mW
Sine Wave Input2 100 120 150 180 210 270 mW
Power-Down Mode 1 1 1 mW
Standby Power 20 20 20 mW
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
2
Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to for the equivalent analog input structure. Figure 4
4
Measured with dc input at maximum clock rate.
MIN
to T
MAX
,
Rev. A | Page 3 of 24
AD9237
DIGITAL SPECIFICATIONS
Table 2.
AD9237BCP-20 AD9237BCP-40 AD9237BCP-65
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage 2.0 2.0 2.0 V
Low Level Input Voltage 0.8 0.8 0.8 V
High Level Input Current –10 +10 –10 +10 –10 +10 μA
Low Level Input Current –10 +10 –10 +10 –10 +10 μA
Input Capacitance 2 2 2 pF
LOGIC OUTPUTS1
DRVDD = 3.3 V
High-Level Output Voltage (IOH = 50 μA) 3.29 3.29 3.29 V
High-Level Output Voltage (IOH = 0.5 mA) 3.25 3.25 3.25 V
Low-Level Output Voltage (IOL = 1.6 mA) 0.2 0.2 0.2 V
Low-Level Output Voltage (IOL = 50 μA) 0.05 0.05 0.05 V
DRVDD = 2.5 V
High-Level Output Voltage (IOH = 50 μA) 2.49 2.49 2.49 V
High-Level Output Voltage (IOH = 0.5 mA) 2.45 2.45 2.45 V
Low-Level Output Voltage (IOL = 1.6 mA) 0.2 0.2 0.2 V
Low-Level Output Voltage (IOL = 50 μA) 0.05 0.05 0.05 V
1
Output voltage levels measured with 5 pF load on each output.
AC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, AIN = –0.5 dBFS, 1.0 V internal reference, T
unless otherwise noted.
Table 3.
AD9237BCP-20 AD9237BCP-40 AD9237BCP-65
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)
f
= 2.4 MHz 66.8 66.5 66.5 dBc
INPUT
f
= 9.7 MHz 65.6 66.6 dBc
INPUT
f
= 19.6 MHz 65.3 66.6 dBc
INPUT
f
= 34.2 MHz 64.0 66.1 dBc
INPUT
f
= 70 MHz 66.0 66.3 65.9 dBc
INPUT
SIGNAL-TO-NOISE RATIO AND DISTORTION (SINAD)
f
= 2.4 MHz 66.7 66.4 66.3 dBc
INPUT
f
= 9.7 MHz 65.1 66.5 dBc
INPUT
f
= 19.6 MHz 64.4 66.4 dBc
INPUT
f
= 34.2 MHz 63.5 65.8 dBc
INPUT
f
= 70 MHz 65.6 65.8 65.2 dBc
INPUT
EFFECTIVE NUMBER OF BITS (ENOB)
f
= 9.7 MHz 10.8 Bits
INPUT
f
= 19.6 MHz 10.7 Bits
INPUT
f
= 34.2 MHz 10.6 Bits
INPUT
MIN
to T
MAX
,
Rev. A | Page 4 of 24
AD9237
AD9237BCP-20 AD9237BCP-40 AD9237BCP-65
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
= 2.4 MHz 88.0 83.5 85.5 dBc
INPUT
f
= 9.7 MHz 72.4 87.5 dBc
INPUT
f
= 19.6 MHz 72.2 82.4 dBc
INPUT
f
= 34.2 MHz 69.4 80.1 dBc
INPUT
f
= 70 MHz 80.5 77.9 74.9 dBc
INPUT
WORST HARMONIC (SECOND OR THIRD)
f
= 2.4 MHz −88.0 −83.5 −85.5 dBc
INPUT
f
= 9.7 MHz −72.4 −87.5 dBc
INPUT
f
= 19.6 MHz −72.2 −82.4 dBc
INPUT
f
= 34.2 MHz −69.4 −80.1 dBc
INPUT
f
= 70 MHz −80.5 −77.9 −74.9 dBc
INPUT
WORST OTHER SPUR
f
= 2.4 MHz −90 −90 −90 dBc
INPUT
f
= 9.7 MHz −73.4 −90 dBc
INPUT
f
= 19.6 MHz −73.1 −90 dBc
INPUT
f
= 34.2 MHz −72.0 −90 dBc
INPUT
f
= 70 MHz −90 −90 −90 dBc
INPUT
SWITCHING SPECIFICATIONS
Table 4.
AD9237BCP-20 AD9237BCP-40 AD9237BCP-65
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
CLK INPUT PARAMETERS
Maximum Conversion Rate 20 40 65 MSPS
Minimum Conversion Rate 1 1 1 MSPS
CLK Period 50.0 25.0 15.4 ns
CLK Pulse Width High1 15.0 8.8 6.2 ns
CLK Pulse Width Low1 15.0 8.8 6.2 ns
DATA OUTPUT PARAMETERS
Output Delay (tPD)2 3.5 3.5 3.5 ns
Pipeline Delay (Latency) 9 9 9 Cycles
Output Enable Time 6 6 6 ns
Output Disable Time 3 3 3 ns
Aperture Delay (tA) 1.0 1.0 1.0 ns
Aperture Uncertainty (Jitter, tJ) 0.5 0.5 0.5 ps rms
Wake-Up Time (Sleep Mode)3 3.0 3.0 3.0 ms
Wake-Up Time (Standby Mode)3 3.0 3.0 3.0 μs
OUT-OF-RANGE RECOVERY TIME 1 1 2 Cycles
1
With duty cycle stabilizer enabled.
2
Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
3
Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
Rev. A | Page 5 of 24
AD9237
TIMING DIAGRAM
N+1
ANALOG
INPUT
CLK
N
N–1
N+2
t
A
N+3
N+4
N+5 N+6
N+8
N+7
DATA
OUT
N–10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1
N–11
t
PD
05455-002
Figure 2. Timing Diagram
Rev. A | Page 6 of 24
AD9237
ABSOLUTE MAXIMUM RATINGS
Table 5.
With
Pin Name
ELECTRICAL
AVDD AGND –0.3 +3.9 V
DRVDD DGND –0.3 +3.9 V
AGND DGND –0.3 +0.3 V
AVDD DRVDD –3.9 +3.9 V
Digital
Outputs, OE
CLK, MODE,
MODE2
VIN+, VIN– AGND –0.3 AVDD + 0.3 V
VREF AGND –0.3 AVDD + 0.3 V
SENSE AGND –0.3 AVDD + 0.3 V
REFB, REFT AGND –0.3 AVDD + 0.3 V
PDWN AGND –0.3 AVDD + 0.3 V
ENVIRONMENTAL1
Operating Temperature –40 +85 °C
Junction Temperature 150 °C
Lead Temperature (10 sec) 300 °C
Storage Temperature –65 +150 °C
1
Typical thermal impedances (32-lead LFCSP), θJA = 32.5°C/W, θJC = 32.71°C/W.
These measurements were taken on a 4-layer board in still air, in accordance
with EIA/JESD51-1.
Respect to Min Max Unit
DGND –0.3 DRVDD + 0.3 V
AGND −0.3 AVDD + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings are limiting values to be applied
individually and beyond which the serviceability of the circuit
may be impaired. Functional operability is not necessarily
implied. Exposure to absolute maximum rating conditions for
an extended period may affect device reliability.
ESD CAUTION
Rev. A | Page 7 of 24
AD9237
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DD
AGND
AV
32
AVDD
VIN–
VIN+
REFT
AGND
31
30
REFB
29
28
27
26
25
14
D7
15
16
DGND
DRVDD
24 VREF
23 SENSE
22 MODE
21 OTR
20 D11 (MSB)
19 D10
18 D9
17 D8
05455-003
1MODE2
PIN 1
2CLK
INDICATOR
3OE
4PDWN
AD9237
5GC
TOP VIEW
6DNC
(Not to Scale)
7D0 (LSB)
8D1
9
11
10
12
13
D2
D3
D4
D5
D6
NOTES
1. DNC = DO NOT CONNECT.
2. IT I S RECOMMENDED T HAT THE EXPO SED PADDLE
BE SOLDEREDTO THE GROUND PLANE.
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin Number Mnemonic Description
1 MODE2 SHA Gain Select and Power Scaling Control (see Tabl e 8).
2 CLK Clock Input Pin.
3 OE Output Enable Pin (Active Low).
4 PDWN Power-Down Function Selection (see Table 9).
5 GC Gray Code Control (Active High).
6 DNC Do Not Connect.
7 to 14, 17 to 20 D0 (LSB) to D11 (MSB) Data Output Bits.
15 DGND Digital Output Ground.
16 DRVDD
Digital Output Driver Supply. Must be decoupled to DGND with a minimum 0.1 μF capacitor.
Recommended decoupling is 0.1 μF in parallel with 10 μF.
21 OTR Out-of-Range Indicator.
22 MODE Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection (see Table 1 0).
23 SENSE Reference Mode Selection (see Table 7).
24 VREF Voltage Reference Input/Output (see Table 7).
25 REFB Differential Reference (−). Must be decoupled to REFT with a minimum 10 μF capacitor.
26 REFT Differential Reference (+).
27, 32 AVDD
Analog Power Supply. Must be decoupled to AGND with a minimum 0.1 μF capacitor.
Recommended decoupling is 0.1 μF in parallel with 10 μF.
28, 31 AGND Analog Ground.
29 VIN+ Analog Input Pin (+).
30 VIN− Analog Input Pin (−).
EP
It is recommended that the exposed paddle be soldered to the ground plane. There is an
increased reliability of the solder joints and maximum thermal capability of the package is
achieved with exposed paddle soldered to the customer board.
Rev. A | Page 8 of 24
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