ANALOG DEVICES AD9230-11 Service Manual

11-Bit, 200 MSPS,

A

FEATURES

SNR = 62.5 dBFS @ fIN up to 70 MHz @ 200 MSPS ENOB of 10.2 @ f SFDR = −77 dBc @ f Excellent linearity

DNL = ±0.15 LSB typical

INL = ±0.5 LSB typical LVDS at 200 MSPS (ANSI-644 levels) 700 MHz full power analog bandwidth On-chip reference, no external decoupling required Integrated input buffer and track-and-hold amplifier Low power dissipation

373 mW @ 200 MSPS (LVDS SDR mode)

328 mW @ 200 MSPS (LVDS DDR mode) Programmable input voltage range

1.0 V to 1.5 V, 1.25 V nominal

1.8 V analog and digital supply operation Selectable output data format (offset binary, twos

complement, gray code) Clock duty cycle stabilizer Integrated data capture clock

up to 70 MHz @ 200 MSPS (−1.0 dBFS)

IN

up to 70 MHz @ 200 MSPS (−1.0 dBFS)

IN

1.8 V Analog-to-Digital Converter AD9230-11

FUNCTIONAL BLOCK DIAGRAM

REFERENCE

CML

VIN+

VIN–

CLK+

CLK–

TRACK-AND-HO LD

CLOCK

MANAGEM ENT

RESET

AGNDPWDNRBIAS

12 11

ADC 12-BIT CORE

SERIAL PORT

SCLK SDIO CSB

Figure 1.

VDD

AD9230-11

OUTPUT

STAGING

LVDS

DRVDD

DRGND

D10 TO D0

OR+

OR–

DCO+

DCO–

07101-001

APPLICATIONS

Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization

GENERAL DESCRIPTION

The AD9230-11 is an 11-bit monolithic sampling analog-todigital converter (ADC) optimized for high performance, low power, and ease of use. The product operates at up to a 200 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) amplifier and voltage reference, are included on the chip to provide a complete signal conversion solution.

The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.

Fabricated on an advanced CMOS process, the AD9230-11 is available in a 56-lead lead frame chip scale package, specified over the industrial temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS

1. High Performance. Maintains 62.5 dBFS SNR

@ 200 MSPS with a 70 MHz input.

2. Low Power. Consumes only 373 mW @ 200 MSPS.

3. Ease of Use. LVDS output data and output clock signal

allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design.

4. Serial Port Control. Standard serial port interface (SPI)

supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation.

5. Pin-Compatible Family. 10-bit and 12-bit pin-compatible

family offered as AD9211 and AD9230.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9230-11

REVISION HISTORY

10/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

AD9230-11

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

MAX

Table 1.

1

Parameter

Temp Min Typ Max Unit

RESOLUTION 11 Bits ACCURACY

No Missing Codes Full Guaranteed Offset Error 25°C 4.2 mV Full −12 +12 mV Gain Error 25°C 0.89 % FS Full −2.2 +4.3 % FS Differential Nonlinearity (DNL) 25°C ±0.15 LSB Full −0.4 +0.4 LSB Integral Nonlinearity (INL) 25°C ±0.5 LSB Full −0.5 +0.5 LSB

TEMPERATURE DRIFT

Offset Error Full ±9 μV/°C Gain Error Full 0.019 %/°C

ANALOG INPUTS (VIN+, VIN−)

Differential Input Voltage Range

2

Full 0.98 1.25 1.5 V p-p

Input Common-Mode Voltage Full 1.4 V Input Resistance (Differential) Full 4.3 kΩ Input Capacitance 25°C 2 pF

POWER SUPPLY

AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V Supply Currents

3

I

Full 152 164 mA

AVDD

I

DRVDD

I

DRVDD

3

/SDR Mode

3

/DDR Mode

4

Full 55 58 mA

5

Full 36 mA

Power Dissipation3 Full

SDR Mode DDR Mode

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were

completed.

2

The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the section. Memory Map

3

I

and I

AVDD

4

Single data rate mode; this is the default mode of the AD9230-11.

5

Double data rate mode; user-programmable feature. See the section.

4

Full 373 400 mW

5

Full 338 mW

are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate.

DRVDD

Memory Map

Rev. 0 | Page 3 of 28

AD9230-11

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 2.

Parameter2 Temp Min Typ Max Unit

SNR

fIN = 10 MHz 25°C 62.4 62.9 dB Full 62.2 dB fIN = 70 MHz 25°C 62.2 62.5 dB Full 62.0 dB fIN = 170 MHz 25°C 61.8 dB

SINAD

fIN = 10 MHz 25°C 62.3 62.8 dB Full 62.1 dB fIN = 70 MHz 25°C 62.0 62.3 dB Full 61.8 dB fIN = 170 MHz 25°C 61.5 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 10 MHz 25°C 10.3 Bits fIN = 70 MHz 25°C 10.2 Bits fIN = 170 MHz 25°C 10.1 Bits

WORST HARMONIC (SECOND OR THIRD)

fIN = 10 MHz 25°C −86 −77 dBc Full −77 dBc fIN = 70 MHz 25°C −79 −77 dBc Full −76 dBc fIN = 170 MHz 25°C −76 dBc

WORST OTHER (SFDR EXCLUDING SECOND AND THIRD)

fIN = 10 MHz 25°C −88 −84 dBc Full −79 dBc fIN = 70 MHz 25°C −84 −82 dBc Full −81 dBc fIN = 170 MHz 25°C −82 dBc

ANALOG INPUT BANDWIDTH 25°C 700 MHz

1

All ac specifications tested by driving CLK+ and CLK− differentially.

2

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were

completed.

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.1

MAX

Rev. 0 | Page 4 of 28

AD9230-11

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 3.

Parameter1 Temp Min Typ Max Unit

CLOCK INPUTS

Logic Compliance Full CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 V Differential Input Voltage Full 0.2 6 V p-p Input Voltage Range Full AGND − 0.3 AVDD + 1.6 V Input Common-Mode Range Full 1.1 AVDD V High Level Input Voltage (VIH) Full 1.2 3.6 V Low Level Input Voltage (VIL) Full 0 0.8 V High Level Input Current (IIH) Full −10 +10 μA Low Level Input Current (IIL) Full −10 +10 μA Input Resistance (Differential) Full 16 20 24 kΩ Input Capacitance Full 4 pF

LOGIC INPUTS

Logic 1 Voltage Full 0.8 × AVDD V Logic 0 Voltage Full 0.2 × AVDD V Logic 1 Input Current (SDIO) Full 0 μA Logic 0 Input Current (SDIO) Full −60 μA Logic 1 Input Current (SCLK, PWDN, CSB, RESET) Full 55 μA Logic 0 Input Current (SCLK, PWDN, CSB, RESET) Full 0 μA Input Capacitance 25°C 4 pF

LOGIC OUTPUTS2

VOD Differential Output Voltage Full 247 454 mV VOS Output Offset Voltage Full 1.125 1.375 V Output Coding Twos complement, gray code, or offset binary (default)

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were

completed.

2

LVDS R

TERMINATION

= 100 Ω.

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

MAX

Rev. 0 | Page 5 of 28

AD9230-11

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 4.

Parameter Temp Min Typ Max Unit

CONVERSION RATE

Maximum Conversion Rate Full 200 Minimum Conversion Rate Full

PULSE WIDTH

CLK+ Pulse Width High (tCH) Full 2.25 2.5 ns CLK+ Pulse Width Low (tCL) Full 2.25 2.5 ns

OUTPUT (LVDS, SDR MODE)

1

Data Propagation Delay (tPD) Full 3.8 ns Rise Time (tR) (20% to 80%) 25°C 0.2 ns Fall Time (tF) (20% to 80%) 25°C 0.2 ns DCO Propagation Delay (t Data to DCO Skew (t

CPD

) Full −0.3 0.1 0.5 ns

SKEW

Latency Full 6 Cycles

OUTPUT (LVDS, DDR MODE)

2

Data Propagation Delay (tPD) Full 3.8 ns Rise Time (tR) (20% to 80%) 25°C 0.2 ns Fall Time (tF) (20% to 80%) 25°C 0.2 ns DCO Propagation Delay (t Data to DCO Skew (t

CPD

) Full −0.5 0.1 0.3 ns

SKEW

Latency Full 6 Cycles

APERTURE UNCERTAINTY (JITTER, tJ) 25°C 0.2 ps rms

1

See Figure 2.

2

See Figure 3.

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

MAX

40 MSPS

MSPS

) Full 3.9 ns

Rev. 0 | Page 6 of 28

AD9230-11

TIMING DIAGRAMS

VIN

CLK+

CLK–

DCO+

DCO–

Dx+

Dx–

VIN

N – 1

t

CH

N – 1

t

A

N

N + 3

N + 1

t

CL

t

CPD

1/

f

S

t

SKEW

t

PD

N – 6 N – 5 N – 4 N – 3 N – 2

N + 2

N + 4

N + 5

07101-002

Figure 2. Single Data Rate Mode

t

A

N

N + 3

N + 1

N + 2

N + 4

N + 5

t

CLK+

CLK–

DCO+

DCO–

D5+

D5–

D4/D10+

D4/D10–

t

CH

CL

t

CPD

1/

f

S

t

SKEW

t

PD

D5

N – 7NODATAD5N – 6NODATAD5N – 5NODATAD5N – 4NODATAD5N – 3NODATA

D10

N – 7D4N – 6

6 MSBs

5 LSBs

D10

N – 6D4N – 5

D10

N – 5D4N – 4

D10

N – 4D4N – 3

D10

N – 3D4N – 2

07101-003

Figure 3. Double Data Rate Mode

Rev. 0 | Page 7 of 28

AD9230-11

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Electrical

AVDD to AGND −0.3 V to +2.0 V DRVDD to DRGND −0.3 V to +2.0 V AGND to DRGND −0.3 V to +0.3 V AVDD to DRVDD −2.0 V to +2.0 V D0+/D0− through D10+/D10−

to DRGND DCO+/DCO− to DRGND −0.3 V to DRVDD + 0.3 V OR+/OR− to DGND −0.3 V to DRVDD + 0.3 V CLK+ to AGND −0.3 V to +3.9 V CLK− to AGND −0.3 V to +3.9 V VIN+ to AGND −0.3 V to AVDD + 0.2 V VIN− to AGND −0.3 V to AVDD + 0.2 V SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V PWDN to AGND −0.3 V to +3.9 V CSB to AGND −0.3 V to +3.9 V SCLK/DFS to AGND −0.3 V to +3.9 V

Environmental

Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature

(Soldering, 10 sec) Junction Temperature 150°C

−0.3 V to DRVDD + 0.3 V

300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package.

Table 6.

Package Type θJA θ

56-Lead LFCSP (CP-56-2) 30.4 2.9 °C/W

Unit

JC

Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θ

JA

. In addition, metal that is in direct contact with the package leads reduces the θ

.

JA

ESD CAUTION

Rev. 0 | Page 8 of 28

AD9230-11

2

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

D1–

D1+

55

56

DCO+

DNC

D0– (LSB)

D0+ (LSB)

52

53

54

50

51

CLK–

AVDD

DRVDD

DRGND

DCO–

48

49

CLK+

AVDD

44

43

45

46

47

1D2– 2D2+ 3D3– 4D3+ 5D4– 6D4+ 7DRVDD 8DRGND

9D5– 10D5+ 11D6– 12D6+ 13D7– 14D7+

NOTES

1. DNC = DO NOT CONNECT. . PIN 0 (EXPOSED PADDLE) = AGND.

PIN 1 INDICATO R

16

15

D8–

D8+

AD9230-11

TOP VIEW

(Not to Scale)

17

19

20

18

D9–

D9+

(MSB) D10–

(MSB) D10+

42 AVDD 41 AVDD 40 CML 39 AVDD 38 AVDD 37 AVDD 36 VIN– 35 VIN+ 34 AVDD 33 AVDD 32 AVDD 31 RBIAS 30 AVDD 29 PWDN

21

22

23

24

25

26

27

28

OR–

OR+

DRGND

CSB

RESET

DRVDD

SDIO/DCS

SCLK/DFS

7101-004

Figure 4. Single Data Rate Mode Pin Configuration

Table 7. Single Data Rate Mode Pin Function Descriptions

Pin No. Mnemonic Description

30, 32 to 34, 37 to 39, 41 to

AVDD 1.8 V Analog Supply.

43, 46 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 0 AGND 8, 23, 48 DRGND

1

Analog Ground. The exposed paddle should be connected to the analog ground.

1

Digital Output Ground.

35 VIN+ Analog Input (True). 36 VIN− Analog Input (Complement). 40 CML

Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the

optimized internal bias voltage for VIN+/VIN−. 44 CLK+ Clock Input (True). 45 CLK− Clock Input (Complement). 31 RBIAS Set Pin for Chip Bias Current. Place 1% 10 kΩ resistor terminated to ground. Nominally 0.5 V. 28 RESET CMOS-Compatible Chip Reset (Active Low). 25 SDIO/DCS

Serial Port Interface (SPI) Data Input/Output (Serial Port Mode). Duty Cycle Stabilizer Select

(External Pin Mode). 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode). Data Format Select Pin (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 29 PWDN Chip Power-Down. 49 DCO− Data Clock Output (Complement). 50 DCO+ Data Clock Output Input (True). 51, 52 DNC Do No Connect. 53 D0− (LSB) D0 Complement Output Bit (LSB). 54 D0+ (LSB) D0 True Output Bit (LSB). 55 D1− D1 Complement Output Bit. 56 D1+ D1 True Output Bit. 1 D2− D2 Complement Output Bit. 2 D2+ D2 True Output Bit.

Rev. 0 | Page 9 of 28

ANALOG DEVICES AD9230-11 Service Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS