Analog Devices AD9229 Service Manual

Quad, 12-Bit, 50/65 MSPS,

FEATURES

Four ADCs in 1 package Serial LVDS digital output data rates

to 780 Mbps (ANSI-644) Data and frame clock outputs SNR = 69.5 dB (to Nyquist) Excellent linearity

DNL = ±0.3 LSB (typical)

INL = ±0.4 LSB (typical) 400 MHz full power analog bandwidth Power dissipation

1,350 mW at 65 MSPS

985 mW at 50 MSPS 1 V p-p to 2 V p-p input voltage range

3.0 V supply operation Power-down mode Digital test pattern enable for timing alignments

APPLICATIONS

Digital beam-forming systems for ultrasound Wireless and wired broadband communications Communication test equipment

GENERAL DESCRIPTION

Serial, LVDS, 3 V A/D Converter

AD9229

FUNCTIONAL BLOCK DIAGRAM

PDWN DTP DRVDD DRGND

AD9229

VIN+A VIN–A

VIN+B VIN–B

VIN+C VIN–C

VIN+D VIN–D

VREF

SENSE

REFT REFB

REF

SELECT

SHA

0.5V

AGND CLKLVDSBIAS

PRODUCT HIGHLIGHTS

PIPELINE

Figure 1.

ADC

12

SERIAL

12

SERIAL

12

SERIAL

12

SERIAL

DATA RATE MULTIPLIER

LVDS

D+A D–A

D+B D–B

D+C D–C

D+D D–D

FCO+ FCO–

DCO+ DCO–

04418-001

The AD9229 is a quad, 12-bit, 65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The product operates at up to a 65 MSPS conversion rate and is optimized for outstanding dynamic performance in applications where a small package size is critical.

The ADC requires a single 3 V power supply and TTL-/CMOScompatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) trigger for signaling a new output byte are provided. Power-down is supported and typically consumes 3 mW when enabled.

Fabricated with an advanced CMOS process, the AD9229 is available in a Pb-free, 48-lead LFCSP package. It is specified over the industrial temperature range of –40°C to +85°C.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

1. Four ADCs are contained in a small, space-saving package.

2. A data clock out (DCO) is provided, which operates up to

390 MHz and supports double-data rate operation (DDR).

3. The outputs of each ADC are serialized LVDS with data

rates up to 780 Mbps (12 bits × 65 MSPS).

4. The AD9229 operates from a single 3.0 V power supply.

5. Packaged in a Pb-free, 48-lead LFCSP package.

6. The internal clock duty cycle stabilizer maintains

performance over a wide range of input clock duty cycles.

AD9229

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications.............................................................. 6

Timing Diagram ............................................................................... 7

Absolute Maximum Ratings............................................................ 8

Explanation of Test Levels........................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Equivalent Circuits......................................................................... 10

Typical Performance Characteristics........................................... 11

Terminology.................................................................................... 16

Theory of Operation ...................................................................... 18

Analog Input Considerations ................................................... 18

Clock Input Considerations...................................................... 19

Evaluation Board............................................................................ 24

Power Supplies............................................................................ 24

Input Signals................................................................................ 24

Output Signals ............................................................................ 24

Default Operation and Jumper Selection Settings ................. 25

Alternate Analog Input Drive Configuration......................... 25

Outline Dimensions....................................................................... 39

Ordering Guide .......................................................................... 39

REVISION HISTORY

9/05—Rev. 0 to Rev. A

Change to Specifications.................................................................. 3

Changes to Differential Input Configurations Section.............. 19

Changes to Exposed Paddle Thermal Heat Slug

Recommendations Section........................................................ 23

Changes to Evaluation Board Section.......................................... 24

Changes to Table 11........................................................................ 36

3/05—Revision 0: Initial Version

Rev. A | Page 2 of 40

AD9229

SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted.

Table 1.

AD9229-50 AD9229-65

Te st

Parameter Temperature

RESOLUTION 12 12 Bits ACCURACY

No Missing Codes Full VI Guaranteed Guaranteed Offset Error Full VI ±5 ±25 ±5 ±25 mV Offset Matching Full VI ±5 ±25 ±5 ±25 mV Gain Error1 Full VI ±0.3 ±2.5 ±0.3 ±2.5 % FS Gain Matching1 Full VI ±0.2 ±1.5 ±0.2 ±1.5 % FS Differential Nonlinearity (DNL) 25°C V ±0.3 ±0.3 LSB Full VI ±0.3 ±0.6 ±0.3 ±0.7 LSB Integral Nonlinearity (INL) 25°C V ±0.6 ±0.4 LSB Full VI ±0.6 ±1 ±0.4 ±1 LSB

TEMPERATURE DRIFT

Offset Error Full V ±2 ±3 ppm/°C Gain Error1 Full V ±12 ±12 ppm/°C Reference Voltage, VREF = 1 V Full V ±16 ±16 ppm/°C

REFERENCE

Output Voltage Error, VREF = 1 V Full VI ±10 ±30 ±10 ±30 mV Load Regulation @ 1.0 mA, VREF = 1 V Full V 3 3 mV Output Voltage Error, VREF = 0.5 V Full VI ±8 ±17 ±8 ±17 mV Load Regulation @ 0.5 mA,

Full V 0.2 0.2 mV

VREF = 0.5 V

Input Resistance Full V 7 7 kΩ

ANALOG INPUTS

Differential Input Voltage Range

Full VI 2 2 V p-p

VREF = 1 V

Differential Input Voltage Range

Full VI 1 1 V p-p

VREF = 0.5 V Common Mode Voltage Full V 1.5 1.5 V Input Capacitance2 Full V 7 7 pF Analog Bandwidth, Full Power Full V 400 400 MHz

POWER SUPPLY

AVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 V DRVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 V IAVDD Full VI 300 330 420 455 mA DRVDD Full VI 28 31 29 33 mA Power Dissipation3 Full VI 985 1083 1350 1465 mW Power-Down Dissipation Full V 3 3 mW

CROSSTALK4 Full V –95 –95 dB

1

Gain error and gain temperature coefficients are based on the ADC only, with a fixed 1.0 V external reference and a 2 V p-p differential analog input.

2

Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.

3

Power dissipation measured with rated encode and 2.4 MHz analog input at –0.5 dBFS.

4

Typical specification over the first Nyquist zone.

Level Min Typ Max Min Typ Max Unit

Rev. A | Page 3 of 40

AD9229

AC SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted.

Table 2.

AD9229-50 AD9229-65

Te st

Parameter Temperature

SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz Full IV 69.5 70.4 69.0 70.2 dB f f f f

= 10.3 MHz 25°C V 70.4 70.2 dB

IN

= 25 MHz Full VI 68.7 69.6 dB

IN

= 30 MHz Full VI 68.0 69.5 dB

IN

= 70 MHz 25°C V 67.2 67.1 dB

IN

SIGNAL-TO-NOISE RATIO (SINAD) fIN = 2.4 MHz Full V 70.0 69.8 dB f f f f EFFECTIVE NUMBER OF BITS

= 10.3 MHz 25°C V 70.0 69.8 dB

IN

= 25 MHz Full VI 68.4 69.4 dB

IN

= 30 MHz Full VI 67.3 69.0 dB

IN

= 70 MHz 25°C V 66.8 66.7 dB

IN

= 2.4 MHz Full V 11.3 11.3 Bits

f

IN

(ENOB) f f f f SPURIOUS-FREE DYNAMIC RANGE

= 10.3 MHz 25°C V 11.3 11.3 Bits

IN

= 25 MHz Full VI 11.1 11.2 Bits

IN

= 30 MHz Full VI 10.9 11.2 Bits

IN

= 70 MHz 25°C V 10.8 10.8 Bits

IN

= 2.4 MHz Full V 85 85 dBc

f

IN

(SFDR) f f f f

= 10.3 MHz 25°C V 85 85 dBc

IN

= 25 MHz Full VI 76 85 dBc

IN

= 30 MHz Full VI 73 85 dBc

IN

= 70 MHz 25°C V 78 77 dBc

IN

WORST HARMONIC fIN = 2.4 MHz Full V –85 –85 dBc

(Second or Third) fIN = 10.3 MHz 25°C V –85 –85 dBc f f f

= 25 MHz Full VI –85 –76 dBc

IN

= 30 MHz Full VI –85 –73 dBc

IN

= 70 MHz 25°C V –78 –77 dBc

IN

WORST OTHER fIN = 2.4 MHz Full V –90 –90 dBc

(Excluding Second or Third) fIN = 10.3 MHz 25°C V –90 –90 dBc f f f TWO-TONE INTERMODULATION

= 25 MHz Full VI –88 –81.7 dBc

IN

= 30 MHz Full VI –88 –79.7 dBc

IN

= 70 MHz 25°C V –85 –83 dBc

IN

= 15 MHz 25°C V –73 –73 dBc

f

IN1

DISTORTION (IMD)

AIN1 and AIN2 = –7.0 dBFS f f f

= 16 MHz

IN2

= 69 MHz 25°C V –68.5 –68.5 dBc

IN1

= 70 MHz

IN2

Level

Min Typ Max Min Typ Max Unit

Rev. A | Page 4 of 40

AD9229

DIGITAL SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted.

Table 3.

AD9229-50 AD9229-65

Te st

Parameter Temperature

CLOCK INPUT

Logic Compliance TTL/CMOS TTL/CMOS High Level Input Voltage Full IV 2.0 2.0 V Low Level Input Voltage Full IV 0.8 0.8 V High Level Input Current Full VI 0.5 ±10 0.5 ±10 µA Low Level Input Current Full VI 0.5 ±10 0.5 ±10 µA Input Capacitance 25°C V 2 2 pF

LOGIC INPUTS (PDWN)

Logic 1 Voltage Full IV 2.0 2.0 V Logic 0 Voltage Full IV 0.8 0.8 V High Level Input Current Full IV 0.5 ±10 0.5 ±10 µA Low Level Input Current Full IV 0.5 ±10 0.5 ±10 µA Input Capacitance 25°C V 2 2 pF

DIGITAL OUTPUTS (D+, D–)

Logic Com plian ce LVDS LVDS Differential Output Voltage Full VI 260 440 260 440 mV Output Offset Voltage Full VI 1.15 1.25 1.35 1.15 1.25 1.35 V Output Coding Full VI

Level

Min Typ Max Min Typ Max Unit

Offset binary

Rev. A | Page 5 of 40

AD9229

SWITCHING SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted.

Table 4.

AD9229-50 AD9229-65

Test

Parameter Temp

CLOCK

Maximum Clock Rate Full VI 50 65 MSPS

Minimum Clock Rate Full IV 10 10 MSPS

Clock Pulse Width High

)

(t

EH

Clock Pulse Width Low

(t

)

EL

Full VI 8 10 6.2 7.7 ns

OUTPUT PARAMETERS

Propagation Delay (tPD) Full VI 3.3 6.5 7.9 3.3 6.5 7.9 ns

Rise Time (tR)

Full V 250 250 ps

(20% to 80%)

Fall Time (tF)

Full V 250 250 ps

(20% to 80%)

FCO Propagation Delay

)

(t

FCO

DCO Propagation Delay

)

(t

CPD

DCO-to-Data Delay (t

DCO-to-FCO Delay (t

Data-to-Data Skew

– t

(t

DATA-MAX

DATA-MIN

Full V 6.5 6.5 ns

Full V t

) Full IV (t

DATA

) Full IV (t

FRAME

Full IV ±100 ±250 ±100 ±250 ps

) Wake-Up Time 25°C V 4 4 ms Pipeline Latency Full IV 10 10 CLK

APERTURE

Aperture Delay (tA) 25°C V 1.8 1.8 ns Aperture Uncertainty

25°C V <1 <1 ps

(Jitter)

OUT-OF-RANGE RECOVERY

25°C V 2 2 CLK

TIME

Level

Min Typ Max Min Typ Max Unit

SAMPLE

250

SAMPLE

250

/24) –

FCO

(t (t

(t

SAMPLE

+

/24) /24) (t

/24) (t

t

SAMPLE

250

SAMPLE

250

/24) +

(t

SAMPLE

250 (t

SAMPLE

250

/24) –

FCO

(t (t

(t

SAMPLE

+

/24) /24) (t

/24) (t

ns

SAMPLE

/24) +

ps

250

SAMPLE

/24) +

ps

250

cycles

rms

cycles

Rev. A | Page 6 of 40

AD9229

TIMING DIAGRAM

N–1

AIN

t

A

CLK

DCO–

DCO+

FCO–

FCO+

D+

t

EH

t

CPD

t

FCO

t

D–

PD

t

FRAME

MSB

D10

(N – 10)

(N–10)D9(N–10)D8(N – 10)D7(N – 10)D6(N – 10)D5(N – 10)D4(N–10)D3(N – 10)D2(N – 10)D1(N – 10)D0(N–10)

t

EL

t

DATA

Figure 2. Timing Diagram

N

D10

MSB

(N – 9)

04418-002

Rev. A | Page 7 of 40

AD9229

ABSOLUTE MAXIMUM RATINGS

Table 5.

With

Parameter

ELECTRICAL

AVDD AGND –0.3 V to +3.9 V DRVDD DRGND –0.3 V to +3.9 V AGND DRGND –0.3 V to +0.3 V AVDD DRVDD –3.9 V to +3.9 V

Digital Outputs (D+, D–,

DCO+, DCO–, FCO+, FCO–)

LVDSBIAS DRGND –0.3 V to DRVDD CLK AGND –0.3 V to AVDD VIN+, VIN– AGND –0.3 V to AVDD PDWN, DTP AGND –0.3 V to AVDD REFT, REFB AGND –0.3 V to AVDD VREF, SENSE AGND –0.3 V to AVDD

ENVIRONMENTAL

Operating Temperature

Range (Ambient)

Maximum Junction

Temperature

Lead Temperature

(Soldering, 10 sec)

Storage Temperature Range

(Ambient)

Thermal Impedance1 25°C/W

Respect To

DRGND –0.3 V to DRVDD

–40°C to +85°C

150°C

300°C

–65°C to +150°C

Rating

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

EXPLANATION OF TEST LEVELS

I. 100% production tested.

II. 100% production tested at 25°C and guaranteed by design

and characterization at specified temperatures.

III. Sample tested only. IV. Parameter is guaranteed by design and characterization

testing.

V. Parameter is a typical value only.

VI. 100% production tested at 25°C and guaranteed by design

and characterization for industrial temperature range.

1

θ

for a 4-layer PCB with a solid ground plane in still air.

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 8 of 40

AD9229

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DCO+

DCO–

FCO+

FCO–

D+A

D–A

D+B

D–B

D+C

D–C

D+D

D–D

DRGND

DRVDD

NC

DTP

AVDD

AGND

PDWN

AVDD

AGND

VIN+A

VIN–A AGND

4847464544434241403938

PIN 1

1 2 3 4 5 6 7 8

9 10 11 12

INDICATOR

EXPOSED PADDLE, PIN 0 (Bottom of Package)

AD9229

TOP VIEW

(Not to Scale)

37

DRGND36 DRVDD

35

LVDSBIAS

34

AGND

33

AVDD

32

AGND

31

CLK

30

AVDD

29

AGND

28

VIN+D

27

VIN–D

26

AGND

25

NC = NO CONNECT

13141516171819

VIN–B

AGND

VIN+B

Figure 3. LFCSP Top View

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

5, 8, 16, 21,

AVDD Analog Supply

29, 32 6, 9, 12, 15, 22,

AGND Analog Ground

25, 28, 31, 33 2, 35 DRVDD Digital Output Supply 1, 36 DRGND Digital Ground 0 AGND

Exposed Paddle/Thermal Heat Slug (Located on Bottom of

Package) 3 NC No Connect 4 DTP Digital Test Pattern Enable 7 PDWN

Power-Down Selection (AVDD =

Power Down) 10 VIN+A ADC A Analog Input—True 11 VIN–A

ADC A Analog Input—

Complement 13 VIN–B

ADC B Analog Input—

Complement 14 VIN+B ADC B Analog Input—True 17 SENSE Reference Mode Selection 18 VREF Voltage Reference Input/Output 19 REFB Differential Reference (Bottom) 20 REFT Differential Reference (Top) 23 VIN+C ADC C Analog Input—True 24 VIN–C

ADC C Analog Input—

Complement

AVDD

SENSE

2021222324

REFT

VREF

REFB

AVDD

AGND

VIN–C

VIN+C

04418-003

Pin No. Mnemonic Description

26 VIN–D

ADC D Analog Input—

Complement 27 VIN+D ADC D Analog Input—True 30 CLK Input Clock 34 LVDSBIAS

LVDS Output Current Set

Resistor Pin 37 D–D

ADC D Complement Digital

Output 38 D+D ADC D True Digital Output 39 D–C

ADC C Complement Digital

Output 40 D+C ADC C True Digital Output 41 D–B

ADC B Complement Digital

Output 42 D+B ADC B True Digital Output 43 D–A

ADC A Complement Digital

Output 44 D+A ADC A True Digital Output 45 FCO–

Frame Clock Indicator—

Complement Output 46 FCO+

Frame Clock Indicator—True

Output 47 DCO–

Data Clock Output—

Complement 48 DCO+ Data Clock Output—True

Rev. A | Page 9 of 40

AD9229

CLK

EQUIVALENT CIRCUITS

AVDD

DRVDD

VIN+, VIN–

AGND

04418-004

Figure 4. Equivalent Analog Input Circuit

AVDD

170Ω

AGND

04418-005

V

D– D+

V

DRGND

V

04418-007

Figure 7. Equivalent Digital Output Circuit

AVDD

DTP

375Ω

AGND

100kΩ

04418-051

Figure 5. Equivalent Clock Input Circuit

AVDD

PDWN

375Ω

AGND

04418-006

Figure 8. Equivalent DTP Input Circuit

Figure 6. Equivalent Digital Input Circuit

Rev. A | Page 10 of 40

AD9229

TYPICAL PERFORMANCE CHARACTERISTICS

–20

0

AIN = –0.5dBFS SNR = 70.4dB ENOB = 11.4 BITS SFDR = 85.8dBC

–20

0

AIN = –0.5dBFS SNR = 68.1dB ENOB = 11.0 BITS SFDR = 77.0dBC

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 8.14.1 12.2 16.3 20.3 24.4 28.4 32.5

Figure 9. Single-Tone 32k FFT with f

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 8.14.1 12.2 16.3 20.3 24.4 28.4 32.5

Figure 10. Single-Tone 32k FFT with f

FREQUENCY (MHz)

= 2.4 MHz, f

IN

AIN = –0.5dBFS SNR = 69.6dB ENOB = 11.3 BITS SFDR = 82.4dBC

FREQUENCY (MHz)

= 30 MHz, f

IN

SAMPLE

= 65 MSPS

04418-009

04418-010

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 8.14.1 12.2 16.3 20.3 24.4 28.4 32.5

Figure 12. Single-Tone 32k FFT with f

90

85

80

75

SNR/SFDR (dB)

70

65

60

10 2015 25 30 35 40 45 50

Figure 13. SNR/SFDR vs. f

FREQUENCY (MHz)

= 120 MHz, f

IN

1V p-p, SFDR (dBc)

2V p-p, SFDR (dBc)

2V p-p, SNR (dB)

1V p-p, SNR (dB)

ENCODE (MSPS)

, fIN = 10.3 MHz, f

SAMPLE

AIN = –0.5dBFS

SAMPLE

= 65 MSPS

SAMPLE

= 50 MSPS

04418-012

04418-013

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 8.14.1 12.2 16.3 20.3 24.4 28.4 32.5

Figure 11. Single-Tone 32k FFT with f

FREQUENCY (MHz)

IN

AIN = –0.5dBFS SNR = 68.5dB ENOB = 11.1 BITS SFDR = 81.3dBC

= 70 MHz, f

SAMPLE

= 65 MSPS

Rev. A | Page 11 of 40

04418-011

90

85

80

75

SNR/SFDR (dB)

70

65

60

10 2015 25 30 35 40 45 50

Figure 14. SNR/SFDR vs. f

1V p-p, SFDR (dBc)

2V p-p, SFDR (dBc)

2V p-p, SNR (dB)

1V p-p, SNR (dB)

ENCODE (MSPS)

, fIN = 25 MHz, f

SAMPLE

AIN = –0.5dBFS

SAMPLE

04418-014

= 50 MSPS

AD9229

95

90

85

80

75

SNR/SFDR (dB)

70

65

60

Figure 15. SNR/SFDR vs. f

1V p-p, SFDR (dBc)

2V p-p, SFDR (dBc)

2V p-p, SNR (dB)

1V p-p, SNR (dB)

10 2015 25 30 35 40 45 6550 55 60

ENCODE (MSPS)

, fIN = 10.3 MHz, f

SAMPLE

AIN = –0.5dBFS

= 65 MSPS

SAMPLE

04418-015

90

80

1V p-p, SFDR (dBc)

70

60

50

40

SNR/SFDR (dB)

30

20

10

0

–60 –10–20–30–40–50 0

1V p-p, SNR (dB)

2V p-p, SFDR (dBc)

80 dB REFERENCE

2V p-p, SNR (dB)

ANALOG INPUT LEVEL (dBFS)

Figure 18. SNR/SFDR vs. Analog Input Level,

=25 MHz, f

f

IN

SAMPLE

= 50 MSPS

04418-018

85

80

75

70

SNR/SFDR (dB)

65

60

10 2015 25 30 35 40 45 6550 55 60

Figure 16. SNR/SFDR vs. f

90

80

70

1V p-p, SFDR (dBc)

60

50

40

SNR/SFDR (dB)

30

20

10

0

–60 –10–20–30–40–50 0

1V p-p, SNR (dB)

2V p-p, SFDR (dBc)

1V p-p, SFDR (dBc)

2V p-p, SNR (dB)

1V p-p, SNR (dB)

ENCODE (MSPS)

, fIN = 30 MHz, f

SAMPLE

2V p-p, SFDR (dBc)

2V p-p, SNR (dB)

ANALOG INPUT LEVEL (dBFS)

SAMPLE

80 dB REFERENCE

AIN = –0.5dBFS

Figure 17. SNR/SFDR vs. Analog Input Level,

= 10.3 MHz, f

f

IN

SAMPLE

= 50 MSPS

= 65 MSPS

04418-016

04418-017

90

80

1V p-p, SFDR (dBc)

70

60

50

40

SNR/SFDR (dB)

30

20

10

0

–60 –10–20–30–40–50 0

1V p-p, SNR (dB)

ANALOG INPUT LEVEL (dBFS)

2V p-p, SFDR (dBc)

80 dB REFERENCE

2V p-p, SNR (dB)

Figure 19. SNR/SFDR vs. Analog Input Level,

= 10.3 MHz, f

f

IN

90

80

70

1V p-p, SFDR (dBc)

60

50

40

SNR/SFDR (dB)

30

20

10

0

–60 –10–20–30–40–50 0

1V p-p, SNR (dB)

ANALOG INPUT LEVEL (dBFS)

= 65 MSPS

SAMPLE

2V p-p, SFDR (dBc)

80 dB REFERENCE

2V p-p, SNR (dB)

Figure 20. SNR/SFDR vs. Analog Input Level,

= 30 MHz, f

f

IN

SAMPLE

= 65 MSPS

04418-019

04418-020

Rev. A | Page 12 of 40