ANALOG DEVICES AD9128 Service Manual

Dual 16 Bit, 1.25GSPS Signal Processing

DAC with JESD204A Serial Interface

Preliminary Technical Data

FEATURES

Low power: 1.4 W @ 1.0 GSPS, 1.2 @ 614 MSPS,

full operating conditions

Data Interface through Four 3.125Gbps JESD204A compliant

data lanes Single carrier WCDMA ACLR = 76 dBc @ 80 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω 2x/4x/8x interpolator/complex modulator allows carrier

placement anywhere in DAC bandwidth Multi-chip synchronization interface with latency locking High performance, low noise PLL clock multiplier Digital inverse sinc filter 56-lead, exposed paddle LFCSP package

APPLICATIONS

Wireless infrastructure Transmit diversity Wideband communications: LMDS/MMDS, point-to-point

GENERAL DESCRIPTION

The AD9128 is a dual, 16-bit, high dynamic range, digital-toanalog converter (DAC) that provides a sample rate of 1.25 GSPS, permitting a multi-carrier generation up to the Nyquist frequency. The AD9128 includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs can interface seamlessly with Analog Devices’

AD9128

quadrature modulators such as the ADL537x Broadband QMOD series.

The AD9128 incorporates four high-speed serial data lanes reducing the interface connections between the DAC and its digital companion chip compared with CMOS or LVDS parallel interfaces. The serial interfaces are capable of receiving data with voltage swings of 200 to 700mV receiver equalization, the receiver is capable of capturing data sent across 0 to 20 cm traces on an FR4 board. The AD9128 also features multi-chip deterministic latency capability, allowing multiple dual DACs to be in alignment with one another.

A serial port interface provides read/write access to on-chip registers. Full-scale output current is programmable over a range of 8.5 mA to 31 mA. TheAD9128 operates on 1.8 V and

3.3 V supply rails.

PRODUCT HIGHLIGHTS

1. Small package size 8mm x 8mm footprint

2. Fewer pins for data input word width with only Four

JESD204A data lines

3. Ultra low noise and intermodulation distortion (IMD)

enables high quality transmission of wideband signals from baseband to high intermediate frequencies.

4. A proprietary DAC output switching technique enhances

dynamic performance.

. With 3 dB of typical

p-p

TYPICAL SIGNAL CHAIN

COMPLEX I AND

DIGITAL INTERPOLATION FILTERS

FPGA/ASIC/DSP

Rev. PrI

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infri ngements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

SERialiser

DESerialiser

Figure 1. Typical signal chain with simplified block diagram of the AD9128

QUADRATURE

MODULATOR/

MIXER/

I DAC

Q DAC

AMPLIFIER

POST DAC

ANALOG FILTER

www.analog.com

AD9128 Preliminary Technical Data

FUNCTIONAL BLOCK DIAGRAM

Rev. PrI | Page 2 of 67

Preliminary Technical Data AD9128

TABLE OF CONTENTS

FEATURES ......................................................................................... 1

Applications ....................................................................................... 1

General Description .......................................................................... 1

Product Highlights ............................................................................ 1

Typical Signal Chain ......................................................................... 1

Functional Block Diagram ............................................................... 2

Specifications ..................................................................................... 4

DC Specifications .......................................................................... 4

Digital Specifications .................................................................... 5

Digital Input Data Timing ........................................................... 6

AC Specifications .......................................................................... 6

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ....................................................................... 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ............................................ 11

Ter minology ..................................................................................... 12

Theory of Operation ....................................................................... 13

High Speed Serial Data Interface .................................................. 15

Receiver circuit ............................................................................ 15

Link Layer .................................................................................... 15

Descrambler ................................................................................. 16

Transport Layer ........................................................................... 16

JESD204A serial Link establishment ........................................ 16

FIFO Operation ........................................................................... 17

Frame Clocking ........................................................................... 18

SERDES PLL ................................................................................ 18

Configuring the JESD204A Serial Interface ............................ 18

Interrupts and SYNCb Control ................................................. 21

Enabling the Link ........................................................................ 21

Serial Port Interface ........................................................................ 22

Serial Port Pin Descriptions ...................................................... 22

Digital Data Path ............................................................................. 24



Interpolation Filters .................................................................... 24

Fine Modulation .......................................................................... 26

Coarse Modulation ..................................................................... 26

Quadrature Phase Correction ................................................... 26

DC Offset Correction ................................................................. 27

Inverse Sinc Filter ........................................................................ 27

DAC Clock Configuration ............................................................. 28

Driving the DACCLK, REFCLK and FRAME Inputs ............ 28

Direct Clocking ........................................................................... 28

Clock Multiplication ................................................................... 28

PLL Settings ................................................................................. 29

Configuring the VCO Tuning Band ......................................... 29

Analog Outputs ............................................................................... 30

Transmit Dac Operation ............................................................ 30

Applications Circuits ...................................................................... 32

Baseband Filter Implementation ............................................... 32

Driving the ADL5375-15 ........................................................... 32

Reducing LO Leakage and Unwanted Sidebands ................... 32

SERDES Link Printed Circuit Board Design Considerations

....................................................................................................... 33

Multi-chip Alignment and Latency lock ..................................... 34

External Alignment Signal ......................................................... 34

SYNCb Interface ......................................................................... 34

SYNCb Usage Models ................................................................. 35

AD9128 Startup Sequence and Latency Alignment Procedure 37

Startup Flowchart ........................................................................ 37

Multi-chip Latency Alignment Flowchart ............................... 38

Testing the SERDES Link at the Board Level .............................. 41

Outline Dimensions ........................................................................ 67

Ordering Guide ............................................................................... 67



Rev. PrI | Page 3 of 67

AD9128 Preliminary Technical Data

SPECIFICATIONS

DC SPECIFICATIONS

to T

MIN

sample rate, unless otherwise noted.

Table 1. DC Specifications

Parameter Min Typ Max Unit

RESOLUTION 16 Bits ACCURACY

Differential Nonlinearity (DNL) TBD LSB Integral Nonlinearity (INL) TBD LSB

MAIN DAC OUTPUTS

Offset Error TBD 0 TBD % FSR Gain Error (with Internal Reference) TBD TBD TBD % FSR Full-Scale Output Current1 TBD TBD TBD mA Output Compliance Range TBD TBD V Output Resistance 10 M Gain DAC Monotonicity Guaranteed Settling Time to Within ±0.5 LSB 20 ns

MAIN DAC TEMPERATURE DRIFT

Offset 0.04 ppm/°C Gain 100 ppm/°C Reference Voltage 30 ppm/°C

REFERENCE

Internal Reference Voltage 1.2 V Output Resistance 5 k

VTT - SERDES Lane Input Termination Voltage 0.8 1.3 V

ANALOG SUPPLY VOLTAGES

AVDD33 3.13 3.3 3.47 V CVDD18 1.71 1.8 1.89 V

DIGITAL SUPPLY VOLTAGES

DVDD18 1.71 1.8 1.89 V IOVDD VTTVDD PLLVDD SVDD

POWER CONSUMPTION

2× Mode, f 4× Mode, f 4× Mode, f AVDD33 TBD mA CVDD18 TBD mA DVDD18

VTTVDD SVDD PLLVDD

Power-Down Mode TBD mW Power Supply Rejection Ratio, AVDD33 −0.3 +0.3 % FSR/V

OPERATING RANGE −40 +25 +85 °C

, AVDD33 = 3.3 V, IOVDD = 3.3V, DVDD18 = SVDD = PLLVDD = VTTVDD = CVDD18 =1.8 V, I

MAX

1.71

= 614.4 MSPS, 4 lanes @ 3072 MHz, PLL Off, Fs/4 TBD mW

DAC

= 1228.8 MSPS, 4 lanes @ 3072 MHz, NCO On TBD mW

DAC

= 983 MSPS, 4 lanes @ 2457.6 MHz, NCO On TBD mW

DAC

1.8/3.3

1.8

TBD

OUTFS

3.47

1.89

mA TBD TBD TBD

= 20 mA, maximum

V V V V

mA mA mA

Rev. PrI | Page 4 of 67

Preliminary Technical Data AD9128

DIGITAL SPECIFICATIONS

to T

MIN

sample rate, unless otherwise noted.

Table 2. Digital specifications

Parameter Conditions Min Typ Max Unit

CMOS INPUT LOGIC LEVEL

Input VIN Logic High IOVDD = 1.8 V 1.2 V Input VIN Logic High IOVDD = 2.5 V 1.6 V Input VIN Logic High IOVDD = 3.3 V 2.0 V Input VIN Logic Low IOVDD = 1.8 V 0.6 V Input VIN Logic Low IOVDD = 2.5 V, 3.3 V 0.8 V

CMOS OUTPUT LOGIC LEVEL

Output V Output V Output V Output V

JESD204 DATA INTERFACE

Number of JESD204A lanes JESD204A Serial interface speed DAC sample rate Input Data rate

RX0P/RX0N, RX1P/RX1N, RX2P/RX2N, RX3P/RX3N

Input Impedance

DAC CLOCK INPUT (DACCLKP, DACCLKN)

Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage Self biased input, ac coupled 1.25 V Receiver Differential Input Impedance, RIN TBD TBD Ω Maximum Clock Rate 1250 MHz

REFCLK INPUT (REFCLKP, REFCLKN)

Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage 1.25 V REFCLK Frequency (PLL Mode) 1 GHz ≤ f

FRAME INPUT (FRAMEP, FRAMEN)

, AVDD33 = 3.3 V, IOVDD = 3.3V, DVDD18 = SVDD = PLLVDD = VTTVDD = CVDD18 =1.8 V, I

MAX

Logic High IOVDD = 1.8 V 1.4 V

OUT

Logic High IOVDD = 2.5 V 1.8 V

OUT

Logic High IOVDD = 3.3 V 2.4 V

OUT

Logic Low IOVDD = 1.8 V, 2.5 V, 3.3 V 0.4 V

OUT

Per lane

1.5

= 20 mA, maximum

OUTFS

4x interpolation All 4 lanes enabled

Current Mode Logic (CML) Compliant, per JESD204

Terminated to a Common Voltage (VTT) with an

Integrated Resistor

≤ 2.1 GHz 15.625 312 MHz

VCO

3.125

1.25

312.5

Lanes Gbps GSPS MSPS

Ω

Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage 1.25 V

SYNCIN INPUT (SYNCINP, SYNCINN)

Input Voltage Range, VIA or VIB 825 1575 mV Input Differential Threshold, V Input Differential Hysteresis, V

−100 +100 mV

IDTH

– V

IDTHH

20 mV

IDTHL

Receiver Differential Input Impedance, RIN 80 120 Ω

SYNCOUT OUTPUTS (SYNCOUT1P, SYNCOUT1N and SYNCOUT2P, SYNCOUT2N)

Output Voltage High, VOA or VOB 1375 mV Output Voltage Low, VOA or VOB 1025 mV Output Differential Voltage, |VOD| 150 200 250 mV Output Offset Voltage, VOS 1150 1250 mV Output Impedance, Single-Ended, RO 80 100 120 Ω

Rev. PrI | Page 5 of 67

AD9128 Preliminary Technical Data

SERIAL PERIPHERAL INTERFACE

Maximum Clock Rate (SCLK) 20 MHz Minimum Pulse Width High (t Minimum Pulse Width Low (t Setup Time, SDI to SCLK (tDS) 1.9 ns Hold Time, SDI to SCLK (tDH) 0.2 ns Data Valid, SDO to SCLK (tDV) 2.3 ns

Setup Time, CS to SCLK (t

DIGITAL INPUT DATA TIMING

Table 3. Input data timing specifications

Parameter Min Typ Max Unit

LATENCY (DACCLK Cycles)

1× Interpolation (With or Without Modulation) TBD Cycles 2× Interpolation (With or Without Modulation) TBD Cycles 4× Interpolation (With or Without Modulation) TBD Cycles 8× Interpolation (With or Without Modulation) TBD Cycles Inverse Sinc TBD Cycles Fine Modulation TBD Cycles Power-Up Time TBD ms

) 25 ns

PWH

) 25 ns

PWOL

DCSB

)

1.4 ns

AC SPECIFICATIONS

TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3V, DVDD18 = SVDD = PLLVDD = VTTVDD = CVDD18 =1.8 V, IOUTFs = 20 mA, maximum sample rate, unless otherwise noted.

Table 4. AC Specifications

Parameter Min Typ Max Unit

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

= 100 MSPS, f

DAC

= 200 MSPS, f

DAC

= 400 MSPS, f

DAC

= 800 MSPS, f

DAC

TWO-TONE INTERMODULATION DISTORTION (IMD)

= 200 MSPS, f

DAC

= 400 MSPS, f

DAC

= 400 MSPS, f

DAC

= 800 MSPS, f

DAC

NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING

= 200 MSPS, f

DAC

= 400 MSPS, f

DAC

= 800 MSPS, f

DAC

W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER

= 491.52 MSPS, f

DAC

= 491.52 MSPS, f

DAC

= 983.04 MSPS, f

DAC

W-CDMA SECOND ACLR, SINGLE CARRIER

= 491.52 MSPS, f

DAC

= 491.52 MSPS, f

DAC

= 983.04 MSPS, f

DAC

= 20 MHz TBD dBc

OUT

= 50 MHz TBD dBc

OUT

= 70 MHz TBD dBc

OUT

= 70 MHz TBD dBc

OUT

= 50 MHz TBD dBc

OUT

= 60 MHz TBD dBc

OUT

= 80 MHz TBD dBc

OUT

= 100 MHz TBD dBc

OUT

= 80 MHz TBD dBm/Hz

OUT

= 80 MHz TBD dBm/Hz

OUT

= 80 MHz TBD dBm/Hz

OUT

= 10 MHz TBD dBc

OUT

= 122.88 MHz TBD dBc

OUT

= 122.88 MHz TBD dBc

OUT

= 10 MHz TBD dBc

OUT

= 122.88 MHz TBD dBc

OUT

= 122.88 MHz TBD dBc

OUT

Rev. PrI | Page 6 of 67

Preliminary Technical Data AD9128

ABSOLUTE MAXIMUM RATINGS

Table 5. Absolute Maximum Ratings

With Respe

Parameter

AVDD33 AVSS,

IOVDD AVSS,

DVDD18, CVDD18, SVDD,

PLLVDD, VTTVDD

AVSS EPAD,

EPAD AVSS,

CVSS AVSS,

DVSS AVSS,

BIAS_RES, REFIO,

IOUT1P/IOUT1N, IOUT2P/IOUT2N

RXN[3:0]/RXP[15:0],

JESD_FRAMEP/JESD_FRAME N

DACCLKP/DACCLKN,

REFCLKP/REFCLKN

ct To Rating

−0.3 V to +3.6 V EPAD, CVSS, DVSS

AVSS, EPAD, CVSS, DVSS

CVSS, DVSS

EPAD, DVSS

EPAD, CVSS

AVSS −0.3 V to AVDD33 +

EPAD, DVSS

CVSS −0.3 V to CVDD18 +

−0.3 V to +2.1 V

−0.3 V to +0.3 V

0.3 V

−0.3 V to DVDD18 +

0.3 V

RESET

SDIO, SDO Junction Temperature 125°C Storage Temperature

Range

IRQ, CS

, SCLK,

EPAD, DVSS

−65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 6. Thermal Resistance

Package Type θJA θJB θJC Unit

56 pin LFCSP TBD TBD TBD °C/W

ESD CAUTION

−0.3 V to IOVDD +

0.3 V

Rev. PrI | Page 7 of 67

AD9128 Preliminary Technical Data

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2.

Table 7. Pin List and Description

Pin Name Description I/O Pin

1 CVDD18 1.8V Clock Supply – Analog Clock Supply I 2 CVDD18 1.8V Clock Supply – Analog Clock Supply I 3 CVDD18 1.8V Clock Supply – PLL Supply (DAC clock generator) I 4 REFCLKP/DACALIGNP If PLL enabled, Reference Clock positive, else DAC align positive1. REFCLKP

can be AC coupled. DACALIGNP cannot be AC coupled and needs 100 ohm (LVDS) resistor

5 REFCLKN/DACALIGNN If PLL enabled, Reference Clock negative, else DAC align negative1.

REFLCKN can be AC coupled. DACALIGNN cannot be AC coupled and

needs 100 ohm (LVDS) resistor 6 JESD_FRAMEP JESD204A Compliant frame clock, positive. Can be AC coupled. I 7 JESD_FRAMEN JESD204A Compliant frame clock, negative. Can be AC coupled. I 8 DVDD18 1.8V Digital Supply – for frame clock and timing DLL. I 9 JESD_SYNCOUT1P JESD204A SYNC Signal, Positive. LVDS compliant. O 10 JESD_SYNCOUT1N JESD204A SYNC Signal, Negative. LVDS compliant. O 11 DVDD18 1.8V Digital Supply (Core) I

Single Edge DAC Alignment input if PLL is disabled. LVDS resistor required between this pin and REFCLK in align mode.

Rev. PrI | Page 8 of 67

Preliminary Technical Data AD9128

12 DVDD18 1.8V Digital Supply (Core) I 13 JESD_SYNCOUT2P JESD204A SYNC Signal Auxiliary, Positive. LVDS compliant. O 14

15 RXN0 Serial Channel input 0, Negative. CML compliant. 50 ohm-terminated to

16 RXP0 Serial channel input 0, Positive. CML compliant. 50 ohm-terminated to Vtt

17 SVDD18 1.8V Deserializer Supply for RX0 and RX1 I 18 RXN1 Serial channel input 1, Negative. CML compliant. 50 ohm-terminated to

19 RXP1 Serial channel input 1, Positive. CML compliant. 50 ohm-terminated to Vtt

20 VTTVDD18 (SVDD18) 1.8V Deserializer supply (Vtt and bias generation supply) I 21 VTT SERDES Lane Input Termination Voltage. Used for supplying external

22 PLLVDD18 1.8V PLL Supply I 23 DVSS (GND) Tied to ground I 24 RXP2 Serial channel input 2, Positive . CML compliant. 50 ohm-terminated to Vtt

25 RXN2 Serial channel input 2, Negative. CML compliant. 50 ohm-terminated to

26 SVDD18 1.8V Deserializer Supply for Rx2 and RX3 I 27 RXP3 Serial channel input 3, Positive. CML compliant. 50 ohm-terminated to Vtt

28 RXN3 Serial channel input 3, Negative . CML compliant. 50 ohm-terminated to

29 JESD_SYNCINN JESD204A SYNC signal input, Negative. LVDS compliant SYNC input with

30 JESD_SYNCINP JESD204A SYNC signal input, Positive. LVDS compliant SYNC input with

31 DVDD18 1.8V Digital Supply (Core) I 32 DVDD18 1.8V Digital Supply (Core) I 33 DVDD18 1.8V Digital Supply I 34 DVDD18 1.8V Digital Supply I 35 IRQB Interrupt Request. Open Drain, Active Low Output O 36 CSB Serial Port Chip Select. Active Low (CMOS levels w.r.t. IOVDD) I 37 SDO Serial Port Data Output (CMOS levels w.r.t. IOVDD) O 38 SDIO Serial Port Data Input/Output (CMOS levels w.r.t. IOVDD) I/O 39 SCLK Serial Port Clock Input (CMOS levels w.r.t. IOVDD) I 40 IOVDD 1.8V – 3.3V Serial Port Supply I 41 RESETB Reset. Active Low. (CMOS levels w.r.t. IOVDD) I 42 TXENABLE Transmit Enable Function pin, programmable parameters through SPI. I 43 AVDD33 3.3V Analog Supply – DAC supply I 44 IOUT2P Q DAC Positive Current Output O 45 IOUT2N Q DAC Negative Current Output O 46 AVDD33 3.3V Analog Supply O 47 REFIO Voltage Reference. Nominally 1.2V output. Should be decoupled to

48 BIAS_RES External reference resistance. Used to set LVDS swing, DAC full-scale

JESD_SYNCOUT2N JESD204A SYNC Signal Auxiliary, Negative. LVDS compliant. O

Vtt pin voltage. Can be AC coupled. Resistance calibrated.

pin voltage. Can be AC coupled. Resistance calibrated.

Vtt pin voltage. Can be AC coupled. Resistance calibrated.

pin voltage. Can be AC coupled. Resistance calibrated.

termination voltage. Load should be < 100pF if internal voltage is used.

pin voltage. Can be AC coupled. Resistance calibrated.

Vtt pin voltage. Can be AC coupled. Resistance calibrated.

pin voltage. Can be AC coupled. Resistance calibrated.

Vtt pin voltage. Can be AC coupled. Resistance calibrated.

internal differential termination only. Resistance calibrated.

Analog Ground.

I current, and deserializer input termination. Place 10K ohm resistor to analog ground.

Rev. PrI | Page 9 of 67

AD9128 Preliminary Technical Data

49 AVDD33 3.3V Analog Supply I 50 AVDD33 3.3V Analog Supply I 51 IOUT1N I DAC Negative Current Output O 52 IOUT1P I DAC Positive Current Output O 53 AVDD33 3.3V Analog Supply I 54 DACCLKN/DACALIGNN DAC Clock Negative input if PLL disabled. DAC Alignment Negative input

if PLL is enabled. DACCLKN can be AC coupled. DACALIGNN cannot be AC coupled and needs 100 ohm (LVDS) resistor

55 DACCLKP/DACALIGNP DAC Clock Positive input if PLL disabled. DAC Alignment Positive input if

PLL is enabled. DACCLKP can be AC coupled. DACALIGNP cannot be AC coupled and needs 100 ohm (LVDS) resistor

56 CVDD18 1.8V Supply – Clock Supply Voltage I

Rev. PrI | Page 10 of 67

Preliminary Technical Data AD9128

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 3

Figure 4

Figure 6

Figure 7

Figure 5

Rev. PrI | Page 11 of 67

AD9128 Preliminary Technical Data

TERMINOLOGY

Integral Nonlinearity (INL)

INL is the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.

Offset Error

Offset error is the deviation of the output current from the ideal of 0 mA. For IOUT1P, 0 mA output is expected when all inputs are set to 0. For IOUT1N, 0 mA output is expected when all inputs are set to 1.

Gain Error

Gain error is the difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0.

Output Compliance Range

The output compliance range is the range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T

MIN

or T

MAX

. For offset and gain drift, the drift is reported in ppm of fullscale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of f

(interpolation rate), a digital filter can be constructed that

DATA

has a sharp transition band near f appear around f

(output data rate) can be greatly suppressed.

DAC

/2. Images that typically

DATA

Adjacent Channel Leakage Ratio (ACLR)

ACLR is the ratio in decibels relative to the carrier (dBc) between the measured power within a channel relative to its adjacent channel.

Complex Image Rejection

In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.

Current Mode Logic (CML)

CML is a differential digital logic family. Signal transmission is point-to-point, unidirectional and terminated at the destination with 50  resistors to a voltage, VTT, on both differential lines. CML is the physical layer for JESD204.

Power Supply Rejection (PSR)

PSR is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages.

Settling Time

Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition.

Spurious Free Dynamic Range (SFDR)

SFDR is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to Nyquist frequency of the DAC. Typically, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths on the DAC output.

Rev. PrI | Page 12 of 67

Preliminary Technical Data AD9128

THEORY OF OPERATION

The AD9128 is a 16-bit Dual DAC with a SERDES interface that is fully compliant with the JESD204A specifications. Figure 8 shows a top-level diagram of the AD9128. Four high-speed serial lanes carry data with a maximum speed of 3.125Gbps, resulting in a 312.5 MSPS (maximum) input data rate for each of the two DACs. The AD9128 can be configured to operate in 1, 2 or 4 JESD204A lane modes, depending on the required DAC input data rate. It can also operate in single DAC mode, with either 1-lane or 2-lane mode.

The two DACs can operate as I and Q channels in a direct conversion transmitter. Or as two independent DACs running at the same DAC sampling rate. The digital data-path of the AD9128 offers four interpolation modes (1X, 2X, 4X or 8X) through three half-band filters with a maximum DAC sampling rate of 1.25 GSPS.

is the DAC sampling frequency. The input signal data-rate for

DAC

both DACs is

For I/Q applications a Numerically Controlled Oscillator (NCO) provides a means for modulating the signal with a programmable carrier signal. The NCO generates the carrier signal for a complex modulator in the digital data path. The resolution of the NCO is 32 bits, allowing the signal to be placed in the output spectrum with very fine resolution. The AD9128 Startup Sequence). The following sections describe elements of the AD9128 in detail.

the interpolation factor.

DAC

AD9128 also features coarse modulation. Coarse modulation up converts a digital signal centered at DC center frequency of F

/4. This option consumes significantly less power compared

DAC

with the NCO modulation approach. Digital gain, offset and phase compensation are included in the AD9128 to help with unwanted sideband suppression in direct conversion transmitters. An inverse Sinc filter is provided to compensate for DAC output sinc-related roll-off.

The DAC Clock (DACCLK) can be sourced externally. Or generated on chip using a PLL synthesizer with externally supplied reference signal.

The AD9128 DAC core provides a fully differential current output with a nominal full-scale current of 20mA. The full-scale current is user adjustable between 8.7mA and 31.7mA. The differential current outputs are complementary.

The AD9128 is capable of multi-chip synchronization and can both synchronize devices and establish deterministic latency (latency locking) among multiple AD9128 devices. The latency for each of the DACs remains constant from link establishment to link establishment.

A SPI interface provides read and write access to registers. The various functional blocks and the data interface need to be setup in a specific sequence for proper operation (See section

Rev. PrI | Page 13 of 67

AD9128 Preliminary Technical Data

Figure 8. AD9128 Functional Block Diagram

Rev. PrI | Page 14 of 67

Preliminary Technical Data AD9128

HIGH SPEED SERIAL DATA INTERFACE

The AD9128 has four JESD204A data ports that receive data for both I and Q transmit paths. Figure 9 describes the communication layers implemented in the AD9128 for each high speed serial data interface to recover the clock, descramble and deserialize the data before it is sent to the Digital Signal Processing section of the AD9128. If a lower data speed is

SYNC

RX P/N

FRAME

RECEIVER LINK LAYER DESCRAMBLER

Figure 9. Functional block diagram of Serial receiver

As the AD9128 can operate with more than one active high speed serial data lane, both achieving synchronization and handling loss of synchronization of the lanes are very important. To simplify the interface to the companion digital chip, theAD9128 designates one master signal (SYNCb) as far as multiple lane synchronization is concerned. If one lane loses synchronization, a resynchronization request is sent to the transmitter and the transmitter stops sending data to all lanes until resynchronization has been achieved.

RECEIVER CIRCUIT

The AD9128 provides four 1.8V differential serial input interfaces compliant with the JESD204A specifications. These interfaces can accept signals at frequencies up to 3.125Gbps using the input topology in Figure 10.

RXP

RDIFF

RXN

Figure 10. Receiver line termination

The receiver eye mask in Figure 11 specifies the signal

amplitude and jitter tolerance for the AD9128 High Speed Serial Data Interface receiver.

acceptable the part can be configured to operate with either two or one JESD204A lanes. The maximum data speed is directly linked to the number of lanes used. In the 4 lane, 2 lane and 1 lane configurations, the maximum supported data speeds are

312.5 MSPS, 156.25 MSPS and 78.125 MSPS respectively.

I DSP + DAC

TRANSPORT LAYER

Q DSP + DAC

500mV

87.5mV

DIFFERENTI

VOLTAG E

- 87.5mV

-500mV

0.22 / DATA RATE

0.44 / DATA RATE

Figure 11. Receiver Eye Mask

The receiver is equipped with a Clock/Data Recovery circuit (CDR) based on a PLL. The PLL effectively multiplies the Frame clock input by 5 X F (F=Number of bytes per frame) and the CDR synchronizes the phase used to sample the data on each serial lane independently. This independent phase adjustment per serial interface ensures accurate data sampling and eases the implementation of multiple serial interfaces on a PCB. A byte rate PLL clock is then used in the link layer, descrambler and transport layers to deserialize the serial input and provide data to the DAC inputs.

LINK LAYER

The AD9128 can operate with more than one active high speed serial data interface. Link layer communications such as code group synchronization, frame alignment and frame synchronization are handled by all four lanes. However, the configuration data is always checked only on a single logical high speed serial data interface: LN0. This logical serial interface can be connected to any of the four JESD204A physical receivers RXn. It is important to note that logical LN0 must be active in all modes of operation.

The AD9128 decodes 8B/10B control characters allowing marking of start and end of frame and alignment between serial lanes. The AD9128 serial interface can issue a synchronization

Rev. PrI | Page 15 of 67

AD9128 Preliminary Technical Data

request by setting the SYNCb pin low. The synchronization protocol follows the JESD204A standard. When a stream of 8 consecutive /K/ symbols is received, the AD9128 deactivates the synchronization request by setting SYNCb pin high and waits for the transmitter to issue an Initial Lane Alignment Sequence (ILAS).

DESCRAMBLER

The AD9128 provides an optional descrambler block using a self-synchronous descrambler with polynomial: 1 + x

Data scrambling can be selected at the transmitter to reduce spectral peaks that would be produced when the same data octets repeat from frame to frame. Another advantage of scrambling is that it makes the spectrum data independent so that possible frequency-selective effects on the electrical interface will not cause data-dependent errors.

+ x15.

TRANSPORT LAYER

The transport layer maps the incoming descrambled data to DAC samples. It provides control of the JESD204A parameters shown in Table 8.

all 4 lanes cannot be used in single-DAC mode). The maximum input data rate in single-DAC mode is the same as the dual DAC mode (312.5MHz).

Table 10. AD9128 interface speeds

Parameter Value

Serial interface speed

Effective serial interface speed

3.125Gbps

2.5Gbps

# of lanes used 4 2 1 DAC Data update

rate (MHz)

312.5 156.25 78.125

Table 8. JESD204A Transport Layer Parameters

Parameter Description

F Number of bytes per frame: 1, 2 or 4 depending on

K Number of frame per multi-frame: K = 32 if F=1,

K=16 otherwise. L Number of lanes per converter device: 1, 2 or 4 M Number of converter per device = 1, 2

Since the AD9128 uses the Frame input as the reference clock for the deserializer PLL, the Frame input needs to be greater than 50 MHz. A number of transport layer configurations are defined to fit the AD9128 definition, as shown in

Ta bl e 9.

Table 9. JESD204A Configuration Parameters

Parameter Description

Number of control words per frame clock per link

= 0. No control word is embedded with samples

CS Number of control bits per conversion sample = 0

High density user data format. Used when samples

need to be split across lanes.

Set to 1 when F=1, 0 otherwise.

N Converter resolution = 16

N’ Total number of bits per sample = 16

Since the AD9128 has four high speed serial data interfaces, several combinations of lanes per converter can be used depending on the data rate desired.

The AD9128 can also operate in real single-DAC mode. In this case, it can be configured in either 2-lane or 1-lane mode (Note:

Figure 12. Serial data interface with 4 lanes active

Configuration CF=0 CS=0 F=2 HD=0 L=2 M=2 N=16 N’=16

FRAME INPUT

Configuration CF=0 CS=0 F=4 HD=0 L=1 M=2 N=16 N’=16

IDACn[15:8]

QDACn[15:8] QDACn[7:0]QDAC

Figure 13. Serial data interface with 2 lanes active

FRAME INPUT

Figure 14. Serial data interface with 1 lane active

IDACn[7:0] IDAC

IDACn[15:8]

[15:8] IDAC

n+1

[15:8]QDAC

n+1

IDACn[7:0] QDACn[15:8] QDACn[7:0]

n+1

[7:0]

JESD204A SERIAL LINK ESTABLISHMENT

A brief summary of the high speed serial link establishment process is given below. Please see the JESD204A Specifications document (reference) for complete details.

1. Code group synchronization a. Each receiver must locate K (K28.5) characters in its

input data stream

Rev. PrI | Page 16 of 67

Preliminary Technical Data AD9128

b. Once 8 consecutive K characters have been detected

on all link lanes, the receiver block de-asserts the SYNCb signal to the transmitter block.

c. The transmitter captures the change in SYNCb and

after a fixed number of frame clocks, starts the Initial Lane Alignment Sequence (ILAS).

2. Initial Lane Alignment Sequence a. The main purposes of this phase are to align all the

lanes of the link and verify the parameters of the link.

b. Before the link is established, each of the link

parameters is written to the receiver device to designate how data will be sent to the receiver block.

c. ILAS consists of 4 or more multi-frames. The last

character or each multi-frame is a multi-frame alignment character /A/

d. The first, third, and fourth multi-frames are populated

with pre-determined data values. The de-framer uses the final /A/ of each lane to align the ends of the multi-frames within the receiver.

e. The second multi-frame contains an R (K.28.0),

Q(K.28.4), and then data corresponding to the link parameters.

f. Additional multi-frames can be added to ILAS if

needed by the receiver. The AD9128 uses 8 multiframes in its ILAS. (When alignment scheme or deterministic latency are used.)

g. After the last /A/ character of the last ILAS multi-

frame data begins to be streamed.

3. Data Streaming a. In this phase data is streamed from the transmitter

block to the receiver block.

b. Data can be optionally scrambled. Scrambling does

not start until the very first octet following the ILAS.

c. The receiver block processes and monitors the data it

receives for errors including:

i. Bad running disparity (8b/10b error)

ii. Not in Table (8b/10b error) iii. Unexpected control-character iv. Bad ILAS

v. Inter-lane skew error (through character

replacement)

d. If any of these errors exists, it is reported back to the

transmitter in one of a few ways

i. SYNCb assertion: Resynchronization (SYNCb

pulled low) is called for at each error. For the first

FIFO OPERATION

The AD9128 contains several stages of FIFO to deal with the high speed serial data interface protocol and to synchronize the data input with the DAC clock input (See Figure 15).

The FIFO in the SERDES deframer interface is used to synchronize the samples sent on the high speed serial data interface with the deframer clock. This FIFO absorbs timing variations between the data source and the deframer. When the FIFO reaches either full or empty state, it is recommended that the user reset it through Register 35 bit 0 and, if necessary, reestablish the SERDES data link. Note that resetting the SERDES link does not reset the FIFO to half-full automatically.

A second 2 channel x 16-bit wide, 8- word deep FIFO exists in the DAC (datapath FIFO) to absorb timing variations between the DAC clock and the Deframer clock. Figure 16 shows the block diagram of the data path through the FIFO. The data is latched into the device, formatted and then written into the FIFO register determined by the FIFO write-pointer. The value of the write-pointer is incremented every time a new word is loaded into the FIFO. Meanwhile, data is read from the FIFO register determined by the read-pointer and fed into the digital datapath. The value of the read-pointer is updated every rising edge of the internal DAC based data clock. The one exception to this occurs when a resynchronization request is in progress: the write side of the FIFO does not increment and the read side is held in reset at a fixed value. Once the ILAS is completed in the AD9128, then the Datapath FIFO is automatically reset to “half full”. During a synchronization request, the DAC outputs are forced to mid-scale and the datapath is flushed. This is done to prevent corrupted data from passing from the DAC.

Valid data will be transmitted through the FIFOs as long as the FIFOs do not overflow or become empty. Nominally, data will be written to the FIFO at the same rate as data is read from the FIFO. This keeps the data level in the FIFO constant. If data is written to the FIFO faster than data is read, the data level in the FIFO increases. If the data is written to the device slower than data is read, the data level in the FIFO decreases.

three errors, SYNCb is asserted after an error counter reaches a given error threshold.

ii. SYNCb reporting: SYNCb is pulsed low for a frame

clock period if an error occurs

iii. Reporting may also be done via interrupt (not

covered by the JESD204A specification). See (i) for error thresholds.

Rev. PrI | Page 17 of 67

AD9128 Preliminary Technical Data

CHARACTER ALIGNMENT

RECEIVER

FIFO

XBAR

FIFO

Figure 15. Block Diagram of AD9128 FIFOs

INPUT LATCH

DATA ASSEMBLER

Figure 16 – Block Diagram of Datapath FIFO

FRAME CLOCKING

The frame clock is the master reference for the high speed serial interface of the AD9128. It drives a PLL in the JESD204A part of the system and needs to be set to the input data rate of the system. The user has three options for the frame clock in AD9128:

 Externally sourced through pins JESD_FRAMEP/N: the

input should be AC coupled and will be self-biased internally.

 Externally sourced through REFCLKP/N: this is possible

only if the internal DAC PLL is used and the supplied reference clock supplied to the PLL (via REFCLKP/N) is at the data rate of the system. (abd equal to the FRAME rate) The input should be AC coupled and will be self-biased internally.

 Internally sourced by using a divided down version of the

DAC clock: this helps minimize the number of low frequency clocks in the user system.

The frame clock source is controlled and monitored through register 0x001D.

SERDES PLL

The SERDES PLL generates clocks at half the rate of the serial data rate and supplies them to the Clock and Data Recovery

Rev. PrI | Page 18 of 67

10-BIT/ 8-BIT

WRITE POINTER

READ POINTE

REG 0

REG 1

REG 2

REG 3

REG 4

REG 5

REG 6

REG 7

64-BITS

FIFO

DESCRAMBLE

DATA PAT HS

SAMPLE RECONSTRUCTION

DACS

FIFO

DAC

(CDR) block. The SERDES PLL settings are controlled and monitored in the register 0x01E. The PLL divide ratio (register 0x01E, bits [3:0]) is dependent on the F value (number of bytes per frame) of the JESD204A link. The F value of the link (1,2 or

4) should be written to this register. The SERDES PLL can be monitored for lock by reading register 0x01E, bit 6.

The SERDES PLL lock can also be accessed through the interrupt controller by writing Register 0x006, bits 7 and/or 6 high. Bit7 enables the interrupt if the SERDES PLL has lost lock, and Bit6 enables the interrupt if the SERDES PLL is locked. These interrupts can be found by reading register 0x009 bits 7 and 6 (when the interrupt output of the AD9128 falls,).

Note that the SERDES PLL must lock before parameters can be written to the deframer.

CONFIGURING THE JESD204A SERIAL INTERFACE

After the SERDES PLL has been successfully locked, the Deserializer SPI is available and can be verified by reading register 0x02 bit 0. The Deserializer SPI is a synchronous read/write SPI (See section Serial Peripheral Interface for SPI interface details). It is addressed through the long addressing mode (default for the AD9128). The addresses for this part of the circuit range from 0x100-0x17F.

Preliminary Technical Data AD9128

Input termination

The AD9128 will auto-calibrate to 50 ohms termination on power-up as register 0x010 bit 5 has a default setting of high. The auto-calibrated value found will be held constant until bit 5 is disabled. Alternatively, a manual calibration value can be entered through register 0x011 bit 3:0 (highest resistor value is 0000 and lowest value is 1111). Manual calibration requires register 0x10 bit5 to be low and 0x11 bit4 to be high. All settings for input termination can be setup and controlled through registers 0x010 and 0x011.

The input termination voltage of the DAC can be sourced either externally or internally:

 External: An external voltage can be driven through the

VTT pin. In order to support DC compliance, its value should match the common mode voltage of the CML driver at the transmitter. It may be bypassed at the pin to local ground.

 Internal: The termination voltage can be supplied

internally by enabling register 0x010 bit 4. The VTT buffer drives both the internal VTT termination and the VTT pin. The termination voltage value can be set through register 0x010 its 3:0. In this case, the VTT pin should not be bypassed to ground. As in option 1, to meet DC compliance, the value of the voltage should be chosen to be close to the value of the CML driver output common-mode. This will ensure minimum power consumption.

For AC coupled systems, in order to minimize power consumption, VTT should be set close to 600mV.

Clock Data Recovery (CDR)

The CDR circuits for the four lanes of the high speed serial interface can be enabled through register 0x012 bits 3:0. For two-lane or one-lane operation, any of the two or any one lane can be chosen. Unused lanes, if enabled, will consume unnecessary power.

Logical Lane Mapping/Enabling

Each of the four physical high speed serial interface lanes, if used, must be mapped to an appropriate logical lane. For example, if four physical lanes are enabled for use with two converters then each of the four logical lanes are mapped to a distinct physical lane. Logical lanes 0, 1, 2 and 3 will contain IMSB, ILSB, QMSB, QLSB respectively. The logical lanes are enabled through register 0x17D and their mapping is controlled through register 0x016, as shown in Tab l e 11.

Table 11. Logical lane mapping for JESD204A link

Rev. PrI | Page 19 of 67

AD9128

configuration

# of

Lanes

# of

DAC

4 2 Each physical lane is mapped to a

2 2 Logical 0 should be mapped to the

data I serial input and logical 2 to

the data Q serial input. Logical

lanes 3 and 4 are unused in this

2 1 Logical 0 should be mapped to

data MSBs and logical 2 to the data

1 2 Logical 0 should to be mapped to

the one serial link and others are

1 1 Logical 0 should both be mapped

to the input lane carrying data

Description Reg.

0x017

D value

0x0F

distinct logical lane

0x05

case

0x05

LSBs

0x01

ignored

0x01

Each of the input lanes can be individually controlled as far as serial symbol mapping is concerned. Both the ordering of the bits (MSB to LSB or LSB to MSB) on bits 7:4, and the individual polarities on bits 3:0 are controlled through register 0x017.

A few mode bits are required in order to operate the non default mode of 4 Lanes or 2 Lanes and F = 1. These are contained in the Register 0x177. They enable sub-modes of the base configuration of the deframer:

 If F=2, Register 0x177 bits 5:2 must be set to 0111 (1 lane

per DAC) and 0x176 must be set to 2.

 If F=4, Register 0x177 bits 5:2 must be set to 1011 (2 DACs

1 line) and 0x176 must be set to 4.

 If F=1, Register 0x177 bits 5:2 must be set to 0000

Programming the JESD204A link parameters

This section provides details of the link parameters with respect to the modes of operations supported by the AD9128. The link parameters are programmed through registers 0x150 to 0x15D. In order to achieve an accurate comparison, all the register values must be programmed the same at the transmitter and receiver end of the link.

1. 0x150: Provides the DID (Device ID or link ID). This is a

comparison only value to identify the link name.

2. 0x151 bits 3:0: Provides the BID (Bank ID). It is an

extension of the DID and meets the same requirements as the DID.

3. 0x152 bits 3:0: Provides the LID0 (lane ID for lane 0 within

a link). The AD9128 will check the lane identification values on lane 0 only.

4. 0x153 bit7: Enables the scrambling function on the link.

5. 0x153 Bits4:0: Provides the number of lanes of the link

associated with DID. This value L will be set based on the number of lanes used and is programmed as one less than

AD9128 Preliminary Technical Data

the number of lanes. The possible values for different DAC modes are:

 4 Lanes, 2 DACs L=3  2 Lanes, 2 DACs L=1  1 Lane, 2 DACs L=0  2 Lanes, 1 DAC L=1  1 Lane, 1 DAC L=0

6. 0x154: Provides the F value or number of octets per frame

per lane. Possible values for different modes are shown in Table 12.

Table 12. JESD204A link “F” value

AD9128 configuration JESD204A

F parameter

# of Lanes # of DAC

0x0154

value

4 2 0 1 2 2 1 2 1 2 3 4 2 1 0 1 1 1 1 2

7. 0x155 bits4:0: Provide the K value (number of frames in a

multiframe). This value is programmed at one less than the actual number. For the AD9128, the value can be:

 K = 31 when F = 0 - 0x1F  K = 31 or 15 when F = 1 or 3- 0x1F or 0x0

8. 0x156: Provides the value of M (number of converters on

the DAC used by the link). This value is programmed as one less than the actual number of converters.

 2 Converters – 0x01  1 Converter – 0x00  2 Lanes, 1 DAC HD = 1 (0x15A = 0x80  1 Lane, 1 DAC HD = 0 (0x15A = 0x00)

9. 0x157 bits 7:6: Provide number of control words per frame.

For the AD9128, this value is always 0 since it does not support control bits.

10. 0x157 bits 5:0: Represents the number of bits of resolution

of the converter. It is programmed at one less than the actual value. The value is 0x0F for the AD9128.

INTERRUPT ENA REGISTER

INTERRUPT EDGE DETECTOR

INTERRUPT SOURCE

Figure 21. Interrupt control on the AD9128

11. 0x158 bits 5:0: Represents the number of bits in each

sample being sent to the deframer. It is programmed at one less than the actual value. The value is 0x0F for the AD9128.

12. 0x159: Represents the number of samples per frame per

converter and is programmed as one less than actual. The AD9128 supports only S = 1 (Reg. 0x159 set to 0).

13. 0x15A bit 7: Represents the high density HD parameter.

ENA = 0

ENA = 1

ISR READ BACK

INTERRUPT

OTHER INTERRUPTS

IRQ

14. 0x15A bits 4:0: Represents CF (the number of control

words per frame clock per lane). Possible values for register 0x15A are shown in Table 13.

Table 13. JESD204A link “HD” value

Rev. PrI | Page 20 of 67

Preliminary Technical Data AD9128

AD9128 configuration JESD204A

HD parameter

# of Lanes # of DAC

4 2 1 0x80 2 2 0 0x00 1 2 0 0x00 2 1 1 0x80 1 1 0 0x00

15. 0x15B, 0x15C: Reserved fields. Should be set to 0 on both

receiver and transmitter ends.

16. 0x15D: Checksum value equal to the sum of all the

registers from 0x150 to 0x15C modulo 256.

Programming ILAS (Initial Lane Alignment Sequence) length:

In the AD9128 the length of the ILAS is programmed in register 0x178. It is programmed as the actual number of multi-frames times four (for a value of 1, the ILAS will be 4 multi-frames long). The AD9128 uses 8 multi-frames during the ILAS to accomplish multichip alignment (or 4 if multi-chip alignment is not needed).

In order to enable multichip alignment or latency locking, register 0x178 should be set to 0x02 and register 0x17B bit 0 should be set to 1. When latency locking/alignment is not needed in the system, register 0x178 should be set to 1 and 0x17B bit 0 to 0.

0x015A

value

INTERRUPTS AND SYNCB CONTROL

The deframer monitors the link for errors, and in the AD9128 these errors can be reported back to the transmitter through different methods:

 Through interrupts  Through the SYNCb signal as frame width assertion

pulses on the line

 Through the SYNCb interface as forced SYNC requests.

Figure 27 shows a block diagram of the AD9128 interrupt control. Errors are counted on a lane by lane basis and either an error interrupt or a SYNCb event is triggered as the count reaches an Error Threshold. This threshold is programmed in Register 0x17C. Error counts for each lane can be monitored through the use of Registers 0x16D – 0x16F. The errors that the deframer will detect are: Bad Disparity Error, Not in Table Error, Unexpected control character, Alignment issue, Bad ILS Sequence, Configuration mismatch

The Interrupt request is masked by bits in registers 0x17A and 0x17B as follows:

0x17A, Bit7 – Bad Disparity (set high to trigger Interrupt request) 0x17A, Bit 6 – Not in Table 0x017A, Bit 5 – Unexpected control character 0x017A, Bit 4 – Interlane Alignment good

Rev. PrI | Page 21 of 67

0x017A, Bit 3 – Good ILAS sequence 0x017A, Bit2 – Good Checksum 0x017A, Bit1 – Good Frame Sync 0x017A, Bit0 – Good Code Group Sync

The SYNCb frame width error reporting can be enabled by setting bit 1 of Register 0x175 high (Bad disparity, not in Table, and Unexpected control character will actuate this error reporting mode).

The SYNC force is masked by bits in 0x17B as follows:

0x17B, Bit7 – Bad disparity error (set high for error to force SYNCb high upon error threshold) 0x17B, Bit6 – Not in Table error 0x17B, Bit5 - Unexpected control character

ENABLING THE LINK

Once SYNCb setup/calibration is completed and clocks have settled, the link is ready to be established. The link can be established by setting bit 7 of Register 0x00A high. A startup sequence is performed for the delay path from DAC clock to SYNCb.

1. The SYNCb phase selector is reset to zero

2. The SYNCb FIFO is reset.

3. The previously programmed value of the SYNCb

launch phase is programmed back to the SYNCb phase selector.

Once the startup sequence concludes inside the DAC, the SYNCb signal is allowed to fall. Conditional upon the link parameters being consistent at both ends and the DAC being able to capture data, the link will be established.

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