ANALOG DEVICES AD9122 Service Manual

Dual, 16-Bit, 1230 MSPS,

TxDAC+ Digital-to-Analog Converter

FEATURES

Flexible LVDS interface allows word, byte, or nibble load
Single-carrier W-CDMA ACLR = 82 dBc at 122.88 MHz IF
Analog output: adjustable 8.7 mA to 31.7 mA,

R

= 25 Ω to 50 Ω

L

Integrated 2×/4×/8× interpolator/complex modulator allows

carrier placement anywhere in the DAC bandwidth

Gain, dc offset, and phase adjustment for sideband

suppression
Multiple chip synchronization interfaces
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
Low power: 1.5 W at 1.2 GSPS, 800 mW at 500 MSPS,

full operating conditions
72-lead, exposed paddle LFCSP

APPLICATIONS

Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE
Digital high or low IF synthesis
Transmit diversity
Wideband communications: LMDS/MMDS, point-to-point

GENERAL DESCRIPTION

The AD9122 is a dual, 16-bit, high dynamic range digital-to­analog converter (DAC) that provides a sample rate of 1230 MSPS,
permitting multicarrier generation up to the Nyquist frequency.

TYPICAL SIGNAL CHAIN

COMPLEX BAS EBAND

COMPL E X I F

AD9122

The AD9122 TxDAC+® includes features optimized for direct
conversion transmit applications, including complex digital mod­ulation, and gain and offset compensation. The DAC outputs
are optimized to interface seamlessly with analog quadrature
modulators, such as the ADL537x F-MOD series from Analog
Devices, Inc. A 4-wire serial port interface provides for program­ming/readback of many internal parameters. Full-scale output
current can be programmed over a range of 8.7 mA to 31.7 mA.
The AD9122 comes in a 72-lead LFCSP.

PRODUCT HIGHLIGHTS

1. Ultralow noise and intermodulation distortion (IMD)

enable high quality synthesis of wideband signals from
baseband to high intermediate frequencies (IF).

2. Proprietary DAC output switching technique enhances

dynamic performance.

3. Current outputs are easily configured for various single-

ended or differential circuit topologies.

4. Flexible LVDS digital interface allows the standard 32-wire

bus to be reduced to one-half or one-quarter of the width.

COMPANION PRODUCTS

IQ Modulators: ADL5370, ADL537x family
IQ Modulators with PLL and VCO: ADRF6701, ADRF670x family
Clock Drivers: AD9516, AD951x family
Voltage Regulator Design Tool: ADIsimPower
Additional companion products on the AD9122 product page

RF

DC

2

DIGITAL

BASEBAND

PROCESSOR

NOTES

1. AQM = ANALOG QUADRATURE MODULATOR.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

SIN

COS

2

2/4

2/4

f

IF

I DAC

ANTIALIASING

FILTER

Q DAC

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009–2011 Analog Devices, Inc. All rights reserved.

LO – f

IF

AQM

LO

PA

08281-001

AD9122

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Companion Products ....................................................................... 1

Typical Signal Chain ......................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

Specifications ..................................................................................... 5

DC Specifications ......................................................................... 5

Digital Specifications ................................................................... 6

Digital Input Data Timing Specifications ................................. 6

AC Specifications .......................................................................... 7

Absolute Maximum Ratings ............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 11

Terminolog y .................................................................................... 17

Differences Between AD9122R1 and AD9122R2 ...................... 18

Device Marking of AD9122R1 and AD9122R2 ..................... 18

Theory of Operation ...................................................................... 19

Serial Port Operation ................................................................. 19

Data Format ................................................................................ 19

Serial Port Pin Descriptions ...................................................... 19

Serial Port Options ..................................................................... 20

Device Configuration Register Map and Descriptions ......... 21

LVDS Input Data Ports .................................................................. 32

Word Interface Mode ................................................................. 32

Byte Interface Mode ................................................................... 32

Nibble Interface Mode ............................................................... 32

Interface Timing ......................................................................... 32

FIFO Operation .......................................................................... 33

Digital Datapath .............................................................................. 36

Premodulation ............................................................................ 36

Interpolation Filters ................................................................... 36

NCO Modulation ....................................................................... 39

Datapath Configuration ............................................................ 39

Determining Interpolation Filter Modes ................................ 40

Datapath Configuration Examples........................................... 41

Rev. B | Page 2 of 60

Data Rates vs. Interpolation Modes ......................................... 42

Coarse Modulation Mixing Sequences .................................... 42

Quadrature Phase Correction ................................................... 43

DC Offset Correction ................................................................ 43

Inverse Sinc Filter ....................................................................... 43

DAC Input Clock Configurations ................................................ 44

Driving the DACCLK and REFCLK Inputs ........................... 44

Direct Clocking .......................................................................... 44

Clock Multiplication .................................................................. 44

PLL Settings ................................................................................ 45

Configuring the VCO Tuning Band ........................................ 45

Analog Outputs............................................................................... 46

Transmit DAC Operation .......................................................... 46

Auxiliary DAC Operation ......................................................... 47

Interfacing to Modulators ......................................................... 48

Baseband Filter Implementation .............................................. 48

Driving the ADL5375-15 .......................................................... 48

Reducing LO Leakage and Unwanted Sidebands .................. 49

Device Power Management ........................................................... 50

Power Dissipation....................................................................... 50

Temperature Sensor ................................................................... 51

Multichip Synchronization ............................................................ 52

Synchronization with Clock Multiplication ............................... 52

Synchronization with Direct Clocking .................................... 53

Data Rate Mode Synchronization ............................................ 53

FIFO Rate Mode Synchronization ........................................... 54

Additional Synchronization Features ...................................... 55

Interrupt Request Operation ........................................................ 56

Interrupt Service Routine .......................................................... 56

Interface Timing Validation .......................................................... 57

SED Operation ............................................................................ 57

SED Example .............................................................................. 58

Example Start-Up Routine ............................................................ 59

Device Configuration ................................................................ 59

Derived PLL Settings ................................................................. 59

Derived NCO Settings ............................................................... 59

Start-Up Sequence ...................................................................... 59

Outline Dimensions ....................................................................... 60

Ordering Guide .......................................................................... 60

AD9122

REVISION HISTORY

5/11—Rev. A to Rev. B

Change to General Description Section ......................................... 1

Added Companion Products Section ............................................. 1

Moved Power Supply Rejection Ratio Parameter from Power
Consumption Section of Table 1 to Main DAC Outputs Section

of Table 1 ............................................................................................. 5

Moved Power-Up Time Parameter from Table 3 to Table 1 ........ 5

Changed Maximum Clock Rate Parameter in Table 2 ................. 6

Changes to Table 3 ............................................................................ 6

Changes to Table 5 ............................................................................ 7

Changes to Table 6 ............................................................................ 8

Changes to Figure 3 and Table 8 ..................................................... 9

Changes to Differences Between AD9122R1 and AD9122R2
Section and Device Marking of AD9122R1 and AD9122R2

Section .............................................................................................. 18

Changes to Figure 40 and Figure 41 ............................................. 20

Changes to Table 10 ........................................................................ 21

Changes to Table 11 ........................................................................ 23

Changes to LVDS Input Data Ports Section and Figure 45 ....... 32

Moved Interface Timing Section ................................................... 32

Moved Figure 46 and Table 13; Changes to Interface

Timing Section ................................................................................ 33

Changes to Resetting the FIFO Section, Serial Port Initiated

FIFO Reset Section, and Figure 48 ............................................... 34

Changes to FRAME Initiated Absolute FIFO Reset Section

and Monitoring the FIFO Status Section ..................................... 35

Changes to Table 22 ........................................................................ 42

Changes to Inverse Sinc Filter Section ......................................... 43

Change to Driving the DACCLK and REFCLK Inputs Section .... 44

Changes to Manual VCO Band Select Section ............................ 45

Changes to Transmit DAC Operation Section ............................ 46

Changes to Figure 69, Figure 70, Figure 71, and Figure 72 ....... 47

Changes to Power Dissipation Section ......................................... 50

Replaced Temperature Sensor Section ......................................... 51

Changes to Multichip Synchronization Section, Synchronization
with Clock Multiplication Section, and Procedure for

Synchronization When Using the PLL Section ........................... 52

Changes to Procedure for Data Rate Synchronization When

Directly Sourcing the DAC Sampling Clock Section ................. 53

Moved Table 25 and Figure 85 ...................................................... 54

Changes to Procedure for FIFO Rate Synchronization When

Directly Sourcing the DAC Sampling Clock Section ................. 54

Changes to Additional Synchronization Features Section and

Timing Optimization Section ........................................................ 55

Added One-Time Synchronization Section ................................ 55

Changes to Interrupt Request Operation Section ...................... 56

Changes to SED Operation Section .............................................. 57

Changes to SED Example Section ................................................. 58

Changes to Example Start-Up Routine Section .......................... 59

3/10—Rev. 0 to Rev. A

Changes to Reflect Differences Between R1 and R2

Silicon .................................................................................. Universal

Changes to Features Section ............................................................ 1

Changes to Table 1 ............................................................................ 5

Changes to Table 2 ............................................................................ 6

Changes to Table 5 ............................................................................ 7

Change to IOVDD Rating in Table 6 ............................................. 8

Changes to Table 8 ............................................................................ 9

Changes to Figure 10 through Figure 15 ...................................... 12

Added Differences Between AD9122R1 and AD9122R2
Section; Added Figure 36 and Figure 37; Renumbered Figures

Sequentially ...................................................................................... 18

Changes to Table 10 ........................................................................ 21

Changes to Table 11 ........................................................................ 23

Changes to FIFO Operation Section ............................................ 33

Changes to Resetting the FIFO Section; Replaced Table 13;
Added Serial Port Initiated FIFO Reset Section and FRAME

Initiated Relative FIFO Reset Section ........................................... 34

Added FRAME Initiated Absolute FIFO Reset Section;

Replaced Table 14 ............................................................................ 35

Changes to Figure 54 ...................................................................... 38

Changes to Table 18 ........................................................................ 39

Changes to SED Example Section ................................................. 58

Added Example Start-Up Routine Section .................................. 59

9/09—Revision 0: Initial Version

Rev. B | Page 3 of 60

AD9122

FUNCTIONAL BLOCK DIAGRAM

D15P/D15N

D0P/D0N

DCI

FRAME

f

/2

DATA

PRE

FIFO HB1 HB2 HB3

MOD

DATA

RECEIVER

MODE

PROGRAMMING

REGISTERS

SERIAL

INPUT/OUTPUT

PORT

SDO

NCO
AND
MOD

HB1_CLK

INTERNAL CLO CK TIMING AND CONTROL L OGIC

CS

SDIO

IRQ

SCLK

POWER-ON

RESET

RESET

HB2_CLK

SYNCHRONIZATI ON

HB3_CLK

MULTICHIP

Figure 2.

16

16

I OFFSET

10

Q OFFSET

16

INTP

FACTOR

PHASE

CORRECTION

SYNC

INV

SINC

INVSINC_CLK

PLL

CONTRO L

DAC_CLK

PLL_LOCK

16

GAIN 110GAIN 2

10

DAC CLK_SEL

0

1

1.2G

DAC 1
16-BIT

DAC_CLK

1.2G

DAC 2
16-BIT

CLOCK

MULTIPLIER

(2× TO 16× )

REF
AND

BIAS

AUX

AUX

CLK

RCVR

CLK

RCVR

IOUT1P

IOUT1N

IOUT2P

IOUT2N

REFIO

FSADJ

DACCLKP
DACCLKN

REFCLKP
REFCLKN

08281-002

Rev. B | Page 4 of 60

AD9122

SPECIFICATIONS

DC SPECIFICATIONS

T

to T

MIN

Table 1.

Parameter Min Typ Max Unit

RESOLUTION 16 Bits
ACCURACY

Differential Nonlinearity (DNL) ±2.1 LSB

Integral Nonlinearity (INL) ±3.7 LSB

MAIN DAC OUTPUTS

Offset Error −0.001 0 +0.001 % FSR

Gain Error (with Internal Reference) −3.6 ±2 +3.6 % FSR

Full-Scale Output Current

Output Compliance Range −1.0 +1.0 V

Power Supply Rejection Ratio, AVDD33 −0.3 +0.3 % FSR/V

Output Resistance 10 MΩ

Gain DAC Monotonicity Guaranteed

Settling Time to Within ±0.5 LSB 20 ns

MAIN DAC TEMPERATURE DRIFT

Offset 0.04 ppm/°C

Gain 100 ppm/°C

Reference Voltage 30 ppm/°C

REFERENCE

Internal Reference Voltage 1.2 V

Output Resistance 5 kΩ

ANALOG SUPPLY VOLTAGES

AVDD33 3.13 3.3 3.47 V

CVDD18 1.71 1.8 1.89 V

DIGITAL SUPPLY VOLTAGES

DVDD18 1.71 1.8 1.89 V

IOVDD 1.71 1.8/3.3 3.47 V

POWER CONSUMPTION

2× Mode, f

2× Mode, f

8× Mode, f

AVDD33 55 57 mA

CVDD18 85 90 mA

DVDD18 444 495 mA

Power-Down Mode (Register 0x01 = 0xF0) 6.5 18.8 mW

POWER-UP TIME 260 ms
OPERATING RANGE −40 +25 +85 °C

1

Based on a 10 kΩ external resistor between FSADJ and AVSS.

, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise noted.

MAX

1

= 491.22 MSPS, IF = 10 MHz, PLL Off 834 mW

DAC

= 491.22 MSPS, IF = 10 MHz, PLL On 913 mW

DAC

= 800 MSPS, IF = 10 MHz, PLL Off 1135 1241 mW

DAC

8.66 19.6 31.66 mA

Rev. B | Page 5 of 60

AD9122

DIGITAL SPECIFICATIONS

T

to T

MIN

noted.

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

CMOS INPUT LOGIC LEVEL

Input VIN Logic High IOVDD = 1.8 V 1.2 V
IOVDD = 2.5 V 1.6 V
IOVDD = 3.3 V 2.0 V
Input VIN Logic Low IOVDD = 1.8 V 0.6 V
IOVDD = 2.5 V, 3.3 V 0.8 V

CMOS OUTPUT LOGIC LEVEL

Output V
IOVDD = 2.5 V 1.8 V
IOVDD = 3.3 V 2.4 V
Output V

LVDS RECEIVER INPUTS

Input Voltage Range, VIA or VIB 825 1675 mV
Input Differential Threshold, V
Input Differential Hysteresis, V
Receiver Differential Input Impedance, RIN 80 120 Ω
LVDS Input Rate See Tab le 5

DAC CLOCK INPUT (DACCLKP, DACCLKN)

Differential Peak-to-Peak Voltage 100 500 2000 mV
Common-Mode Voltage Self-biased input, ac-coupled 1.25 V
Maximum Clock Rate 1230 MHz

REFCLK INPUT (REFCLKP, REFCLKN)

Differential Peak-to-Peak Voltage 100 500 2000 mV
Common-Mode Voltage 1.25 V
REFCLK Frequency (PLL Mode) 1 GHz ≤ f
REFCLK Frequency (SYNC Mode)

SERIAL PORT INTERFACE

Maximum Clock Rate (SCLK) 40 MHz
Minimum Pulse Width High (t
Minimum Pulse Width Low (t
Setup Time, SDIO to SCLK (tDS) 1.9 ns
Hold Time, SDIO to SCLK (tDH) 0.2 ns
Data Valid, SDO to SCLK (tDV) 2.3 ns
Setup Time, CS to SCLK (t

1

LVDS receiver is compliant with the IEEE 1596 reduced range link, unless otherwise noted.

DIGITAL INPUT DATA TIMING SPECIFICATIONS

Table 3.

Parameter Value Unit

LATENCY (DACCLK CYCLES)

1× Interpolation (With or Without Modulation) 64 Cycles
2× Interpolation (With or Without Modulation) 135 Cycles
4× Interpolation (With or Without Modulation) 292 Cycles
8× Interpolation (With or Without Modulation) 608 Cycles
Inverse Sinc 20 Cycles
Fine Modulation 8 Cycles

, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise

MAX

Logic High IOVDD = 1.8 V 1.4 V

OUT

Logic Low IOVDD = 1.8 V, 2.5 V, 3.3 V 0.4 V

OUT

1

−100 +100 mV

IDTH

to V

IDTHH

IDTHL

Applies to data, DCI, and FRAME inputs

20 mV

≤ 2.1 GHz 15.625 600 MHz

VCO

See the Multichip Synchronization section

0 600 MHz

for conditions

) 12.5 ns

PWH

) 12.5 ns

PWL

DCSB

)

1.4 ns

Rev. B | Page 6 of 60

AD9122

AC SPECIFICATIONS

T

to T

MIN

Table 4.

Parameter Min Typ Max Unit

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f

DAC

f

DAC

f

DAC

f

DAC

TWO-TONE INTERMODULATION DISTORTION (IMD)

f

DAC

f

DAC

f

DAC

f

DAC

NOISE SPECTRAL DENSITY (NSD), EIGHT-TONE, 500 kHz TONE SPACING

f

DAC

f

DAC

f

DAC

W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE-CARRIER

f

DAC

f

DAC

f

DAC

W-CDMA SECOND ACLR, SINGLE-CARRIER

f

DAC

f

DAC

f

DAC

, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise noted.

MAX

= 100 MSPS, f
= 200 MSPS, f
= 400 MSPS, f
= 800 MSPS, f

= 200 MSPS, f
= 400 MSPS, f
= 400 MSPS, f
= 800 MSPS, f

= 200 MSPS, f
= 400 MSPS, f
= 800 MSPS, f

= 491.52 MSPS, f
= 491.52 MSPS, f
= 983.04 MSPS, f

= 491.52 MSPS, f
= 491.52 MSPS, f
= 983.04 MSPS, f

= 20 MHz 78 dBc

OUT

= 50 MHz 80 dBc

OUT

= 70 MHz 69 dBc

OUT

= 70 MHz 72 dBc

OUT

= 50 MHz 84 dBc

OUT

= 60 MHz 86 dBc

OUT

= 80 MHz 84 dBc

OUT

= 100 MHz 81 dBc

OUT

= 80 MHz −162 dBm/Hz

OUT

= 80 MHz −163 dBm/Hz

OUT

= 80 MHz −164 dBm/Hz

OUT

= 10 MHz 84 dBc

OUT

= 122.88 MHz 82 dBc

OUT

= 122.88 MHz 83 dBc

OUT

= 10 MHz 88 dBc

OUT

= 122.88 MHz 86 dBc

OUT

= 122.88 MHz 88 dBc

OUT

Table 5. Maximum Rate (MSPS) with DVDD and CVDD Supply Regulation

f

Bus Width

Interpolation
Fac tor

(MSPS) f

INTERFACE

DVDD18, CVDD18 = DVDD18, CVDD18 =

1.8 V ± 5% 1.8 V ± 2% 1.9 V ± 2% 1.8 V ± 5% 1.8 V ± 2% 1.9 V ± 2%

(MSPS)

DAC

Nibble (4 Bits) 1× 1100 1200 1230 137.5 150 153.75
2× 1100 1200 1230 275 300 307.5
4× 1100 1200 1230 550 600 615
8× 1100 1200 1230 1100 1200 1230
Byte (8 Bits) 1× 1100 1200 1230 275 300 307.5
2× 1100 1200 1230 550 600 615
4× 1100 1200 1230 1100 1200 1230
8× 550 600 615 1100 1200 1230
Word (16 Bits) 1× 1100 1200 1230 550 600 615
2× (HB1) 900 1000 1000 900 1000 1000
2× (HB2) 1100 1200 1230 1100 1200 1230
4× 550 600 615 1100 1200 1230
8× 275 300 307.5 1100 1200 1230

Rev. B | Page 7 of 60

AD9122

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

AVDD33 to AVSS, EPAD, CVSS, DVSS −0.3 V to +3.6 V
IOVDD to AVSS, EPAD, CVSS, DVSS −0.3 V to +3.6 V
DVDD18, CVDD18 to AVSS, EPAD,

CVSS, DVSS
AVSS to EPAD, CVSS, DVSS −0.3 V to +0.3 V
EPAD to AVSS, CVSS, DVSS −0.3 V to +0.3 V
CVSS to AVSS, EPAD, DVSS −0.3 V to +0.3 V
DVSS to AVSS, EPAD, CVSS −0.3 V to +0.3 V
FSADJ, REFIO, IOUT1P, IOUT1N,

IOUT2P, IOUT2N to AVSS
D[15:0]P, D[15:0]N, FRAMEP, FRAMEN,

DCIP, DCIN to EPAD, DVSS
DACCLKP, DACCLKN, REFCLKP,

REFCLKN to CVSS
RESET, IRQ, CS, SCLK, SDIO, SDO

to EPAD, DVSS
Junction Temperature 125°C
Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

−0.3 V to +2.1 V

−0.3 V to AVDD33 + 0.3 V

−0.3 V to DVDD18 + 0.3 V

−0.3 V to CVDD18 + 0.3 V

−0.3 V to IOVDD + 0.3 V

THERMAL RESISTANCE

The exposed pad (EPAD) of the 72-lead LFCSP must be
soldered to the ground plane (AVSS). The EPAD provides an
electrical, thermal, and mechanical connection to the board.

Typical θ

, θJB, and θJC values are specified for a 4-layer board in

JA

still air. Airflow increases heat dissipation, effectively reducing
θ

and θJB.

JA

Table 7. Thermal Resistance

Package θJA θJB θJC Unit Conditions

72-Lead LFCSP 20.7 10.9 1.1 °C/W

EPAD soldered
to ground plane

ESD CAUTION

Rev. B | Page 8 of 60

AD9122

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CVDD18

CVDD18

REFCLKP

REFCLKN

AVDD33

IOUT1P

IOUT1N

AVDD33

AVSS

FSADJ

REFIO

AVSS

AVDD33

IOUT2N

IOUT2P

AVDD33

AVSS

NC

CVDD18
DACCLKP
DACCLKN

CVSS
FRAMEP
FRAMEN

IRQ
D15P
D15N

NC

IOVDD

DVDD18

D14P
D14N
D13P
D13N

7271706968676665646362616059585756

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17D12P
18D12N

PIN 1
INDICATO R

AD9122

TOP VIEW

(Not to Scale)

55

RESET

54

CS

53

SCLK

52

SDIO

51

SDO

50

DVDD18

49

D0N

48

D0P

47

D1N

46

D1P

45

DVSS

44

DVDD18

43

D2N

42

D2P

41

D3N

40

D3P

39

D4N

38

D4P

37

192021222324252627282930313233

D9P

D8P

D9N

D8N

DCIP

D11P

D10P

D11N

D10N

NOTES

1. EXPOSED PAD (EPAD) MUST BE SOLDERED TO THE GROUND PLANE (AVSS).
THE EPAD PROVI DES AN ELECTRICAL, THERMAL, AND MECHANICAL
CONNECTION T O THE BOARD.

2. NC = NO CONNECT . DO NOT CONNECT TO THIS PI N.

DCIN

DVDD18

34

35D5P

36D5N

D7P

D6P

D7N

D6N

DVSS

08281-003

Figure 3. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1 CVDD18 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry.
2 DACCLKP DAC Clock Input, Positive.
3 DACCLKN DAC Clock Input, Negative.
4 CVSS Clock Supply Common.
5 FRAMEP Frame Input, Positive. This pin must be tied to DVSS if not used.
6 FRAMEN Frame Input, Negative. This pin must be tied to DVDD18 if not used.
7

IRQ

Interrupt Request. Open-drain, active low output. Connect an external pull-up to IOVDD through a 10 kΩ

resistor.
8 D15P Data Bit 15 (MSB), Positive.
9 D15N Data Bit 15 (MSB), Negative.
10 NC No Connect. Do not connect to this pin.
11 IOVDD

Supply Pin for Serial Port I/O Pins, RESET

, and IRQ. 1.8 V to 3.3 V can be supplied to this pin.
12 DVDD18 1.8 V Digital Supply. Supplies power to digital core and digital data ports.
13 D14P Data Bit 14, Positive.
14 D14N Data Bit 14, Negative.
15 D13P Data Bit 13, Positive.
16 D13N Data Bit 13, Negative.
17 D12P Data Bit 12, Positive.
18 D12N Data Bit 12, Negative.
19 D11P Data Bit 11, Positive.
20 D11N Data Bit 11, Negative.
21 D10P Data Bit 10, Positive.
22 D10N Data Bit 10, Negative.
23 D9P Data Bit 9, Positive.
24 D9N Data Bit 9, Negative.

Rev. B | Page 9 of 60

AD9122

Pin No. Mnemonic Description

25 D8P Data Bit 8, Positive.
26 D8N Data Bit 8, Negative.
27 DCIP Data Clock Input, Positive.
28 DCIN Data Clock Input, Negative.
29 DVDD18 1.8 V Digital Supply. Supplies power to digital core and digital data ports.
30 DVSS Digital Common.
31 D7P Data Bit 7, Positive.
32 D7N Data Bit 7, Negative.
33 D6P Data Bit 6, Positive.
34 D6N Data Bit 6, Negative.
35 D5P Data Bit 5, Positive.
36 D5N Data Bit 5, Negative.
37 D4P Data Bit 4, Positive.
38 D4N Data Bit 4, Negative.
39 D3P Data Bit 3, Positive.
40 D3N Data Bit 3, Negative.
41 D2P Data Bit 2, Positive.
42 D2N Data Bit 2, Negative.
43 DVDD18 1.8 V Digital Supply. Supplies power to digital core and digital data ports.
44 DVSS Digital Common.
45 D1P Data Bit 1, Positive.
46 D1N Data Bit 1, Negative.
47 D0P Data Bit 0 (LSB), Positive.
48 D0N Data Bit 0 (LSB), Negative.
49 DVDD18 1.8 V Digital Supply. Supplies power to digital core and digital data ports.
50 SDO Serial Port Data Output (CMOS Levels with Respect to IOVDD).
51 SDIO Serial Port Data Input/Output (CMOS Levels with Respect to IOVDD).
52 SCLK Serial Port Clock Input (CMOS Levels with Respect to IOVDD).
53

54

CS

RESET
55 NC No Connect. Do not connect to this pin.
56 AVSS Analog Supply Common.
57 AVDD33 3.3 V Analog Supply.
58 IOUT2P Q DAC Positive Current Output.
59 IOUT2N Q DAC Negative Current Output.
60 AVDD33 3.3 V Analog Supply.
61 AVSS Analog Supply Common.
62 REFIO Voltage Reference. Nominally 1.2 V output. Should be decoupled to AVSS.
63 FSADJ Full-Scale Current Output Adjust. Place a 10 kΩ resistor from this pin to AVSS.
64 AVSS Analog Supply Common.

65 AVDD33 3.3 V Analog Supply.
66 IOUT1N I DAC Negative Current Output.
67 IOUT1P I DAC Positive Current Output.
68 AVDD33 3.3 V Analog Supply.
69 REFCLKN PLL Reference Clock Input, Negative. This pin has a secondary function as a synchronization input.
70 REFCLKP PLL Reference Clock Input, Positive. This pin has a secondary function as a synchronization input.
71 CVDD18 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry.
72 CVDD18 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry.
EPAD

Serial Port Chip Select, Active Low (CMOS Levels with Respect to IOVDD).
Reset, Active Low (CMOS Levels with Respect to IOVDD).

The exposed pad (EPAD) must be soldered to the ground plane (AVSS). The EPAD provides an electrical,
thermal, and mechanical connection to the board.

Rev. B | Page 10 of 60

AD9122

TYPICAL PERFORMANCE CHARACTERISTICS

0

f

= 250MSPS, SECO ND HARMONIC

DATA

f

–10

–20

–30

–40

–50

–60

HARMONICS (dBc)

–70

–80

–90

–100

0 50 100 150 200 250 300 350 400 450

Figure 4. Harmonics vs. f

= 250MSPS, T HIRD HARMONIC

DATA

f

= 400MSPS, SECO ND HARMONIC

DATA

f

= 400MSPS, T HIRD HARMONIC

DATA

f

(MHz)

OUT

over f

OUT

Digital Scale = 0 dBFS, I

, 2× Interpolation,

DATA

= 20 mA

FS

08281-101

0

0dBFS

–10

–20

–30

–40

–50

–60

–70

SECOND HARMONIC (dBc)

–80

–90

–100

Figure 7. Second Harmonic vs. f

–6dBFS
–12dBFS
–18dBFS

0 50 100 150 200 250 300 350 400 450

f

(MHz)

OUT

over Digital Scale, 2× Interpolation,

OUT

= 400 MSPS, IFS = 20 mA

f

DATA

08281-104

0

f

= 100MSPS, SECO ND HARMONIC

DATA

f

–10

–20

–30

–40

–50

–60

HARMONICS (dBc)

–70

–80

–90

–100

0 50 100 150 200 250 300 350 400 450

Figure 5. Harmonics vs. f

0

–10

–20

–30

–40

–50

–60

HARMONICS (dBc)

–70

–80

–90

–100

0 100 200 300 400 500 600 700

Figure 6. Harmonics vs. f

= 100MSPS, T HIRD HARMONIC

DATA

f

= 200MSPS, SECO ND HARMONIC

DATA

f

= 200MSPS, T HIRD HARMONIC

DATA

f

(MHz)

OUT

over f

OUT

Digital Scale = 0 dBFS, I

f

= 100MSPS, SECO ND HARMONIC

DATA

f

= 100MSPS, T HIRD HARMONIC

DATA

f

= 150MSPS, SECO ND HARMONIC

DATA

f

= 150MSPS, T HIRD HARMONIC

DATA

f

(MHz)

OUT

over f

OUT

Digital Scale = 0 dBFS, I

, 4× Interpolation,

DATA

= 20 mA

FS

, 8× Interpolation,

DATA

= 20 mA

FS

0

0dBFS

–10

–20

–30

–40

–50

–60

–70

THIRD HARMONIC (dBc)

–80

–90

–100

08281-102

Figure 8. Third Harmonic vs. f

–10

–20

–30

–40

–50

–60

HARMONICS (dBc)

–70

–80

–90

–100

08281-103

–6dBFS
–12dBFS
–18dBFS

0 50 100 150 200 250 300 350 400 450

f

(MHz)

OUT

over Digital Scale, 2× Interpolation,

OUT

= 400 MSPS, IFS = 20 mA

f

DATA

0

IFS = 10mA, SECOND HARMONIC
IFS = 20mA, SECOND HARMONIC
IFS = 30mA, SECOND HARMONIC
IFS = 10mA, THIRD HARMONI C
IFS = 20mA, THIRD HARMONI C
IFS = 30mA, THIRD HARMONI C

0 50 100 150 200 250 300 350 400 450

f

(MHz)

OUT

Figure 9. Harmonics vs. f

= 400 MSPS, Digital Scale = 0 dBFS

f

DATA

over IFS, 2× Interpolation,

OUT

08281-105

08281-106

Rev. B | Page 11 of 60

AD9122

–

–

–

69

–70

–71

–72

–73

–74

–75

–76

HIGHEST DI GITAL SPUR (dBc)

–77

–78

–79

Figure 10. Highest Digital Spur vs. f

f

= 250MSPS

DATA

f

= 400MSPS

DATA

0 50 100 150 200 250 300 350 400 450

Digital Scale = 0 dBFS, I

f

OUT

(MHz)

OUT

over f

= 20 mA

FS

, 2× Interpolation,

DATA

2× INTERPOLATION,
SINGLE-TONE SPECTRUM,

f

= 250MSPS,

DATA

f

= 101MHz

OUT

START 1.0MHz

08281-107

#RES BW 10kHz

VBW 10kHz STOP 500.0MHz

SWEEP 6.017s (601 PTS)

08281-110

Figure 13. Single-Tone Spectrum, 2× Interpolation,

= 250 MSPS, f

f

DATA

= 101 MHz

OUT

60

–65

–70

–75

HIGHEST DI GITAL SPUR (dBc)

–80

–85

0 50 100 150 200 250 300 350 400 450

Figure 11. Highest Digital Spur vs. f

f

OUT

(MHz)

OUT

Digital Scale = 0 dBFS, I

60

f

= 100MSPS

DATA

f

= 150MSPS

–65

–70

–75

DATA

over f

= 20 mA

FS

f

DATA

f

DATA

, 4× Interpolation,

DATA

= 100MSPS
= 200MSPS

4× INTERPOLATION,
SINGLE-TONE SPECTRUM,

f

= 200MSPS,

DATA

f

= 151MHz

OUT

START 1.0MHz

08281-108

#RES BW 10kHz

VBW 10kHz STOP 800. 0MHz

SWEEP 9. 634s (601 PTS)

08281-111

Figure 14. Single-Tone Spectrum, 4× Interpolation,

= 200 MSPS, f

f

DATA

8× INTERPOLATION,
SINGLE-TONE SPECTRUM,

f

= 100MSPS,

DATA

f

= 131MHz

OUT

= 151 MHz

OUT

–80

–85

HIGHEST DI GITAL SPUR (dBc)

–90

–95

0 100 200 300 400 500 600 700

f

(MHz)

OUT

Figure 12. Highest Digital Spur vs. f

Digital Scale = 0 dBFS, I

OUT

over f

= 20 mA

FS

, 8× Interpolation,

DATA

08281-109

START 1.0MHz
#RES BW 10kHz

VBW 10kHz STOP 800.0MHz

SWEEP 9.634s (601 PTS)

Figure 15. Single-Tone Spectrum, 8× Interpolation,

= 100 MSPS, f

f

DATA

= 131 MHz

OUT

08281-112

Rev. B | Page 12 of 60

AD9122

–

–

0

f

= 250MSPS

DATA

f

= 400MSPS

–10

–20

–30

–40

–50

IMD (dBc)

–60

–70

–80

–90

DATA

0 50 100 150 200 250 300 350 400 450

f

(MHz)

OUT

Figure 16. IMD vs. f

Digital Scale = 0 dBFS, I

OUT

over f

DATA

, 2× Interpolation,

= 20 mA

FS

08281-113

0

0dBFS

–10

–20

–30

–40

–50

IMD (dBc)

–60

–70

–80

–90

–6dBFS
–12dBFS
–18dBFS

0 50 100 150 200 250 300 350 400 450

f

(MHz)

OUT

Figure 19. IMD vs. f

over Digital Scale, 2× Interpolation,

OUT

= 400 MSPS, IFS = 20 mA

f

DATA

08281-116

0

f

= 100MSPS

DATA

f

= 200MSPS

–10

–20

–30

–40

–50

IMD (dBc)

–60

–70

–80

–90

–10

–20

–30

–40

–50

IMD (dBc)

–60

–70

–80

–90

–100

DATA

0 50 100 150 200 250 300 350 400 450

f

(MHz)

OUT

Figure 17. IMD vs. f

Digital Scale = 0 dBFS, I

0

f

= 100MSPS

DATA

0 50 100 150 200 250 300 350 400 450

Figure 18. IMD vs. f

Digital Scale = 0 dBFS, I

over f

OUT

DATA

f

(MHz)

OUT

, 8× Interpolation, f

OUT

, 4× Interpolation,

= 20 mA

FS

= 100 MSPS,

DATA

= 20 mA

FS

50

–55

–60

–65

–70

IMD (dBc)

–75

–80

–85

08281-114

40

–45

–50

–55

–60

–65

IMD (dBc)

–70

–75

–80

–85

–90

08281-115

IFS = 10mA

IFS = 20mA
IFS = 30mA

0 50 100 150 200 250 300 350 400 450

f

(MHz)

OUT

Figure 20. IMD vs. f

= 400 MSPS, Digital Scale = 0 dBFS

f

DATA

0 50 100 150 200 250 300 350 400 450

Figure 21. IMD vs. f

Digital Scale = 0 dBFS, I

over IFS, 2× Interpolation,

OUT

PLL ON

PLL OFF

f

(MHz)

OUT

, 4× Interpolation, f

OUT

= 20 mA, PLL On and PLL Off

FS

= 200 MSPS,

DATA

08281-117

08281-118

Rev. B | Page 13 of 60

AD9122

–

–

–

–

–

–

152

–154

–156

–158

–160

NSD (dBm/Hz)

–162

–164

–166

0 50 100 150 200 250 300 350 400 450

Figure 22. One-Tone NSD vs. f

1×,

f

= 200MSPS

DATA

2×,

f

= 200MSPS

DATA

4×,

f

= 200MSPS

DATA

8×,

f

= 100MSPS

DATA

f

OUT

Digital Scale = 0 dBFS, I

(MHz)

over Interpolation,

OUT

= 20 mA, PLL Off

FS

161.0

–161.5

–162.0

–162.5

–163.0

–163.5

NSD (dBm/Hz)

–164.0

–164.5

–165.0

–165.5

08281-119

1×,

f

= 200MSPS

DATA

2×,

f

= 200MSPS

DATA

4×,

f

= 200MSPS

DATA

8×,

f

= 100MSPS

DATA

0 50 100 150 200 250 300 350 400 450

f

(MHz)

OUT

Figure 25. Eight-Tone NSD vs. f

Digital Scale = 0 dBFS, I

over Interpolation,

OUT

= 20 mA, PLL Off

FS

08281-122

154

–156

–158

–160

–162

NSD (dBm/Hz)

–164

–166

–168

Figure 23. One-Tone NSD vs. f

158

–159

–160

–161

–162

0dBFS
–6dBFS
–12dBFS
–18dBFS

0 50 100 150 200 250 300 350 400 450

f

(MHz)

OUT

over Digital Scale, 4× Interpolation,

OUT

= 200 MSPS, IFS = 20 mA, PLL Off

f

DATA

2×,

f

= 200MSPS

DATA

4×,

f

= 200MSPS

DATA

8×,

f

= 100MSPS

DATA

161.0

–161.5

–162.0

–162.5

–163.0

–163.5

–164.0

NSD (dBm/Hz)

–164.5

–165.0

–165.5

–166.0

–166.5

08281-120

Figure 26. Eight-Tone NSD vs. f

160

–161

–162

–163

0dBFS
–6dBFS
–12dBFS
–18dBFS

0 50 100 150 200 250 300 350 400 450

f

(MHz)

OUT

over Digital Scale, 4× Interpolation,

= 200 MSPS, IFS = 20 mA, PLL Off

f

DATA

2×,

f

DATA

4×,

f

DATA

8×,

f

DATA

OUT

= 200MSPS
= 200MSPS
= 100MSPS

08281-123

–163

NSD (dBm/ Hz)

–164

–165

–166

0 50 100 150 200 250 300 350 400 450

f

(MHz)

OUT

Figure 24. One-Tone NSD vs. f

Digital Scale = 0 dBFS, I

over Interpolation,

OUT

= 20 mA, PLL On

FS

08281-121

NSD (dBm/ Hz)

–164

–165

–166

0 50 100 150 200 250 300 350 400 450

f

(MHz)

OUT

Figure 27. Eight-Tone NSD vs. f

Digital Scale = 0 dBFS, I

over Interpolation,

OUT

= 20 mA, PLL On

FS

08281-124

Rev. B | Page 14 of 60

AD9122

–

–

–

–

–

–

ACLR (dBc)

–78

–79

–80

–81

–82

–83

77

0dBFS
–3dBFS
–6dBFS

ACLR (dBc)

–55

–60

–65

–70

–75

–80

–85

50

INTERPOLATION FACTOR = 2×, PLL OFF
INTERPOLATION FACTOR = 4×, PLL OFF
INTERPOLATION FACTOR = 2×, PLL ON
INTERPOLATION FACTOR = 4×, PLL ON

–84

0 50 100 150 200 250

f

(MHz)

OUT

Figure 28. One-Carrier W-CDMA ACLR vs. f

over Digital Scale,

OUT

Adjacent Channel, PLL Off

78

0dBFS
–3dBFS

–80

–82

–84

ACLR (dBc)

–86

–88

–90

Figure 29. One-Carrier W-CDMA ACLR vs. f

–6dBFS

0 50 100 150 200 250

f

(MHz)

OUT

over Digital Scale,

OUT

First Alternate Channel, PLL Off

70

0dBFS
–3dBFS

–75

–6dBFS

–90

0 100 200 300 400 500

f

(MHz)

08281-125

Figure 31. One-Carrier W-CDMA ACLR vs. f

OUT

over Interpolation,

OUT

08281-128

Adjacent Channel, PLL On and PLL Off

70

INTERPOLATION FACTOR = 2×, PLL OFF

–72

–74

–76

–78

–80

–82

ACLR (dBc)

–84

–86

–88

–90

08281-126

Figure 32. One-Carrier W-CDMA ACLR vs. f

INTERPOLATION FACTOR = 4×, PLL OFF
INTERPOLATION FACTOR = 2×, PLL ON
INTERPOLATION FACTOR = 4×, PLL ON

0 100 200 300 400 500

f

(MHz)

OUT

over Interpolation,

OUT

08281-129

First Alternate Channel, PLL On and PLL Off

70

INTERPOLATION FACTOR = 2×, PLL OFF
INTERPOLATION FACTOR = 4×, PLL OFF
INTERPOLATION FACTOR = 2×, PLL ON

–75

INTERPOLATION FACTOR = 4×, PLL ON

–80

–85

ACLR (dBc)

–90

–95

0 50 100 150 200 250

f

(MHz)

OUT

Figure 30. One-Carrier W-CDMA ACLR vs. f

over Digital Scale,

OUT

Second Alternate Channel, PLL Off

08281-127

–80

ACLR (dBc)

–85

–90

–95

0 100 200 300 400 500

f

(MHz)

OUT

Figure 33. One-Carrier W-CDMA ACLR vs. f

over Interpolation,

OUT

Second Alternate Channel, PLL On and PLL Off

08281-130

Rev. B | Page 15 of 60

AD9122

START 133.06M Hz
#RES BW 30kHz

RMS RESULTS FREQ LO WER UPPER

CARRIER POWER 5.00MHz 3.840MHz –75.96 –85.96 –77.13 –87.13
–10.00dBm/ 10.00MHz 3.840MHz –85.33 –95.33 –85.24 –95.25

3.840MHz 15.00MHz 2.888MHz –95.81 –95.81 –85.43 –95.43

OFFSET REF BW dBc dBm dBc dBm

VBW 30kHz ST OP 166.94MHz

SWEEP 143. 6ms (601 PTS)

Figure 34. One-Carrier W-CDMA ACLR Performance, IF = ~150 MHz

START 125.88MHz
#RES BW 30kHz

TOTAL CARRIER POWER –11.19dBm/15.3600MHz
RRC FILTER: OFF FILTER ALPHA 0.22
REF CARRIER POWER –16.89dBm/3.84000MHz

08281-131

1 –16.92dBm 5.000MHz 3.840MHz –65.88 –82.76 –67.52 –84.40
2 –16.89dBm 10.00MHz 3.840MHz –68.17 –85.05 –69.91 –86.79
3 –17.43dBm 15.00MHz 3.840MHz –70.42 –87.31 –71.40 –88.28
4 –17.64dBm

OFFSET FREQ INTEG BW dBc dBm dBc dBm

VBW 30kHz ST OP 174.42MHz

SWEEP 206.9ms (601 PTS)

LOWER UPPER

08281-132

Figure 35. Four-Carrier W-CDMA ACLR Performance, IF = ~150 MHz

Rev. B | Page 16 of 60

AD9122

TERMINOLOGY

Integral Nonlinearity (INL)

INL is the maximum deviation of the actual analog output from
the ideal output, determined by a straight line drawn from zero
scale to full scale.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.

Offset Error

Offset error is the deviation of the output current from the ideal
of 0 mA. For IOUT1P, 0 mA output is expected when all inputs
are set to 0. For IOUT1N, 0 mA output is expected when all
inputs are set to 1.

Gain Error

Gain error is the difference between the actual and ideal output
span. The actual span is determined by the difference between
the output when all inputs are set to 1 and the output when all
inputs are set to 0.

Output Compliance Range

The output compliance range is the range of allowable voltage
at the output of a current output DAC. Operation beyond the
maximum compliance limits can cause either output stage
saturation or breakdown, resulting in nonlinear performance.

Temp er at u re D ri ft

Temperature drift is specified as the maximum change from
the ambient (25°C) value to the value at either T

MIN

or T

MAX

.
For offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree Celsius. For reference voltage drift, the
drift is reported in ppm per degree Celsius.

Power Supply Rejection (PSR)

PSR is the maximum change in the full-scale output as the
supplies are varied from minimum to maximum specified
voltages.

Settling Time

Settling time is the time required for the output to reach and
remain within a specified error band around its final value,
measured from the start of the output transition.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels, between the peak amplitude
of the output signal and the peak spurious signal within the dc
to Nyquist frequency of the DAC. Typically, energy in this band
is rejected by the interpolation filters. This specification, there­fore, defines how well the interpolation filters work and the
effect of other parasitic coupling paths on the DAC output.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of
f

(interpolation rate), a digital filter can be constructed that

DATA

has a sharp transition band near f
appear around f

(output data rate) can be greatly suppressed.

DAC

/2. Images that typically

DATA

Adjacent Channel Leakage Ratio (ACLR)

ACLR is the ratio in decibels relative to the carrier (dBc) between
the measured power within a channel and that of its adjacent
channel.

Complex Image Rejection

In a traditional two-part upconversion, two images are created
around the second IF frequency. These images have the effect
of wasting transmitter power and system bandwidth. By placing
the real part of a second complex modulator in series with the
first complex modulator, either the upper or lower frequency
image near the second IF can be rejected.

Rev. B | Page 17 of 60

AD9122

DIFFERENCES BETWEEN AD9122R1 AND AD9122R2

The AD9122 underwent a die revision in early 2010, which
incremented the die revision from R1 to R2. The following list
explains the differences between the revisions.

• IOVDD supply voltage range.

For the AD9122R1, the valid operational voltage range
for IOVDD is 1.8 V to 2.5 V ± 10%. For the AD9122R2,
the valid operational voltage range for IOVDD is 1.8 V
to 3.3 V ± 10%.

• Reduction in spurs level variation.

The AD9122R1 has variation in the f

DATA

± f

spur level

OUT

between device startups. The AD9122R2 has a consistent
and lower f

DATA

± f

spur level. (The AD9122R2 still has

OUT

a spur level variation between power cycles of about 5 dB
if the PLL is enabled.)

• DCI delay feature added.

The AD9122R2 has a programmable delay associated with
the DCI signal. There are four programmable delay options.
The 00 setting gives the minimum delay and leaves the
timing unchanged from the AD9122R1. Additional delay
can be added to improve timing margins in some systems.
The resulting timing options are shown in Tab l e 13.

• Power-down mode power consumption increase.

The maximum power-down mode power consumption
of the R1 devices is 9.8 mW. This power consumption
increased to 18.8 mW in the R2 devices.

• Configuration register map changes.

Register 0x0B, Bit 5:

AD9122R1 Æ Enable VCO
AD9122R2 Æ Inactive bit. The VCO is now enabled
when the PLL is enabled.

Register 0x16, Bits[1:0]:

AD9122R1 Æ Unused
AD9122R2 Æ These bits control the delay of the DCI
signal (00 = minimum delay, 11 = maximum delay).

Register 0x7F:

AD9122R1 Æ Version ID = 0x04
AD9122R2 Æ Version ID = 0x0C

DEVICE MARKING OF AD9122R1 AND AD9122R2

Revision 1 devices are marked as shown in Figure 36. Revision 1
devices with TxDAC® as the top line have date codes earlier than
#1001. Revision 1 devices with AD80255 as the top line have date
codes of #1001 or later.

Revision 2 devices are marked as shown in Figure 37. Revision 2
devices have TxDAC® as the top line and date codes of #1001 or
later.

®

TxDAC

AD9122BCPZ

DATE CODE

Figure 36. Revision 1 Silicon, AD9122BCPZ Marking

Figure 37. Revision 2 Silicon, AD9122BCPZ Marking

#0935

1688587.1
KOREA

DATE CODE

TxDAC

AD9122BCPZ
#1021

1688782.1
KOREA

AD80255
AD9122BCPZ
#1001

1688586.1
KOREA

®

08281-136

08281-137

Rev. B | Page 18 of 60