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AD9059 a
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Analog Devices AD9059 a Datasheet

AD9059
FEATURES Dual 8-Bit ADCs on a Single Chip Low Power: 400 mW Typical On-Chip 2.5 V Reference and Track-and-Hold 1 V p-p Analog Input Range Single 5 V Supply Operation 5 V or 3 V Logic Interface 120 MHz Analog Bandwidth Power-Down Mode: <12 mW
APPLICATIONS Digital Communications (QAM Demodulators) RGB and YC/Composite Video Processing Digital Data Storage Read Channels Medical Imaging Digital Instrumentation

PRODUCT DESCRIPTION

The AD9059 is a dual 8-bit monolithic analog-to-digital converter optimized for low cost, low power, small size, and ease of use. With a 60 MSPS encode rate capability and full-power analog bandwidth of 120 MHz typical, the component is ideal for applications requiring multiple ADCs with excellent dynamic performance.
To minimize system cost and power dissipation, the AD9059 includes an internal 2.5 V reference and dual track-and-hold circuits. The ADC requires only a 5 V power supply and an encode clock. No external reference or driver components are required for many applications.
The AD9059’s single encode input is TTL/CMOS compatible and simultaneously controls both internal ADC channels. The parallel 8-bit digital outputs can be operated from 5 V or 3 V supplies. A power-down function may be exercised to bring total consumption to <12 mW when ADC data is not required for lengthy periods of time. In power-down mode, the digital outputs are driven to a high impedance state.
Fabricated on an advanced BiCMOS process, the AD9059 is available in a space-saving 28-lead shrink small outline package (28-lead SSOP) and is specified over the industrial temperature range (–40°C to +85°C).
Customers desiring single-channel digitization may consider the AD9057, a single 8-bit, 60 MSPS monolithic based on the AD9059 ADC core. The AD9057 is available in a 20-lead shrink small outline package (20-lead SSOP) and is specified over the industrial temperature range.

FUNCTIONAL BLOCK DIAGRAM

PWRDN
V
D
V
DD
AD9059
AINA
VREF
AINB
T/H
T/H
ADC
2.5V
ADC
GND
8
A
ENCODE
8
B

PIN CONFIGURATION

AINA
VREF
PWRDN
GND
V
D7A (MSB)
D6A
D5A
D4A
D3A
D2A
D1A
D0A (LSB)
V
D
DD
1
2
3
4
5
AD9059
6
TOP VIEW
(Not to Scale)
7
8
9
10
11
12
13
14
28
AINB
27
GND
26
ENCODE
25
V
24
GND
23
V
22
D7B (MSB)
21
D6B
D5B
20
19
D4B
18
D3B
17
D2B
16
D1B
15
D0B (LSB)
D
DD
D7A–D0A
D7B–D0B
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
AD9059–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter Temp Test Level Min Typ Max Unit
RESOLUTION 8 Bits
DC ACCURACY
Differential Nonlinearity 25°CI 0.75 2.0 LSB
Integral Nonlinearity 25°CI 0.75 2.0 LSB
No Missing Codes Full VI Guaranteed Gain Error
Gain Temperature Coefficient
ANALOG INPUT
Input Voltage Range (Centered at 2.5 V) 25°CV 1.0 V p-p Input Offset Voltage 25°CI –15 0 +15 mV
Input Resistance 25°CV 150 kΩ Input Capacitance 25°CV 2 pF Input Bias Current 25°CI 616µA Analog Bandwidth 25°CV 120 MHz
CHANNEL MATCHING (A to B)
Gain Delta 25°CV ± 1% FS Input Offset Voltage Delta 25°CV ± 4mV
BAND GAP REFERENCE
Output Voltage Full VI 2.4 2.5 2.6 V Temperature Coefficient Full V ±10 ppm/°C
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 60 MSPS Minimum Conversion Rate Full IV 5 MSPS Aperture Delay (t Aperture Uncertainty (Jitter) 25°CV 5 ps, rms Output Valid Time (t Output Propagation Delay (tPD)
DYNAMIC PERFORMANCE
Transient Response 25°CV 9 ns Overvoltage Recovery Time 25°CV 9 ns Signal-to-Noise Ratio (SINAD) (with Harmonics)
f
IN
f
IN
Effective Number of Bits (ENOB)
f
IN
f
IN
Signal-to-Noise Ratio (SNR) (Without Harmonics)
f
IN
f
IN
Second Harmonic Distortion
f
IN
f
IN
Third Harmonic Distortion
f
IN
f
IN
Two-Tone Intermodulation Distortion (IMD) 25°CV –52 dBc Channel Crosstalk Rejection 25°CV –50 dBc Differential Phase 25°CV 0.8 Degrees Differential Gain 25°CV 1.0 %
1
1
)25°CV 2.7 ns
A
2
)
V
2
3
= 10.3 MHz 25°CI 4044.5 dB = 76 MHz 25°CV 43.5 dB
= 10.3 MHz 25°CI 6.35 7.1 Bits = 76 MHz 25°CV 6.9 Bits
= 10.3 MHz 25°CI 4246 dB = 76 MHz 25°CV 45 dB
= 10.3 MHz 25°CI –50 –62 dBc = 76 MHz 25°CV –54 dBc
= 10.3 MHz 25°CI –46 –60 dBc = 76 MHz 25°CV –54 dBc
(VD = 5 V, VDD = 3 V, external reference, ENCODE = 60 MSPS, unless otherwise noted.)
AD9059BRS
Full VI 2.5 LSB
Full VI 2.5 LSB
25°CI –6 –2.5 +6 % FS Full VI –8 +8 % FS Full V ± 70 ppm/°C
Full VI –25 +25 mV
Full IV 4.0 6.6 ns Full IV 9.5 14.2 ns
REV. A–2–
AD9059
SPECIFICATIONS
(continued)
AD9059BRS
Parameter Temp Test Level Min Typ Max Unit
DIGITAL INPUTS
Logic 1 Voltage Full VI 2.0 V Logic 0 Voltage Full VI 0.8 V Logic 1 Current Full VI ±1 µA Logic 0 Current Full VI ±1 µA Input Capacitance 25°CV 4.5 pF Encode Pulsewidth High (t
)25°CIV 6.7 166 ns
EH
Encode Pulsewidth Low (tEL)25°CIV 6.7 166 ns
DIGITAL OUTPUTS
Logic 1 Voltage (VDD = 3 V) Full VI 2.95 V Logic 1 Voltage (V Logic 0 Voltage (V
= 5 V) Full IV 4.95 V
DD
= 3 V or 5 V) Full VI 0.05 V
DD
Output Coding Offset Binary Code
POWER SUPPLY
VD Supply Current (VD = 5 V) Full VI 72 92 mA
Supply Current (VDD = 3 V)
V
DD
Power Dissipation
5, 6
4
Full VI 13 15 mA
Full VI 400 505 mW Power-Down Dissipation Full VI 6 12 mW Power Supply Rejection Ratio (PSRR) 25°CI 3 mV/V
NOTES
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 2.5 V external reference).
2
tV and tPD are measured from the 1.5 V level of the ENCODE to the 10%/90% levels of the digital output swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of ± 40 µA.
3
SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 1.0 V full-scale input range.
4
Digital supply current based on VDD = 3 V output drive with <10 pF loading under dynamic test conditions.
5
Power dissipation is based on 60 MSPS encode and 10.3 MHz analog input dynamic test conditions (VD = 5 V ± 5%, VDD = 3 V ± 5%).
6
Typical thermal impedance for the RS style (SSOP) 28-lead package: θJC = 39°C/W, θCA = 70°C/W, and θJA = 109°C/W.
Specifications subject to change without notice.

EXPLANATION OF TEST LEVELS

Test Level
I–100% production tested.
II – 100% production tested at +25°C and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V– Parameter is a typical value only.
VI – 100% production tested at +25°C; guaranteed by design
and characterization testing for industrial temperature range.

ABSOLUTE MAXIMUM RATINGS*

VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

ORDERING GUIDE

Model Temperature Range Package Option
AD9059BRS –40°C to +85°C RS-28 AD9059/PCB 25°C Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9059 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
+ 0.5 V
D
+ 0.5 V
D
+ 0.5 V
D
REV. A
–3–
AD9059
NN + 3N + 5

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function
AIN
ENCODE
DIGITAL
OUTPUTS
N + 1
t
A
tEHt
EL
t
V
N – 3 N – 2 N – 1 N N + 1 N + 2
t
PD
N + 2
N + 4
MIN TYP
t
A
APERTURE DELAY
t
EH
PULSEWIDTH HIGH
t
PULSEWIDTH LOW
EL
t
OUTPUT VALID TIME
V
OUTPUT PROP DELAY
t
PD
6.7ns
6.7ns
4.0ns
2.7ns
6.6n
9.5ns
Figure 1. Timing Diagram

PIN CONFIGURATION

AINA
VREF
PWRDN
GND
V
D7A (MSB)
D6A
D5A
D4A
D3A
D2A
D1A
D0A (LSB)
V
D
DD
1
2
3
4
5
AD9059
6
TOP VIEW
(Not to Scale)
7
8
9
10
11
12
13
14
28
AINB
27
GND
26
ENCODE
25
V
24
GND
23
V
22
D7B (MSB)
21
D6B
D5B
20
19
D4B
18
D3B
17
D2B
16
D1B
15
D0B (LSB)
D
DD
MAX
166ns
166ns
14.2ns
1, 28 AINA, AINB Analog Inputs for ADC A and B.
2 VREF Internal Voltage Reference (2.5 V
Typical); Bypass with 0.1 µF to Ground or Overdrive with External Voltage Reference.
3 PWRDN Power-Down Function Select; Logic
HIGH for Power-Down Mode (Digital Outputs Go to High­Impedance State).
4, 25 V
D
Analog 5 V Power Supply.
5, 24, 27 GND Ground.
6, 23 V
DD
Digital Output Power Supply. Nominally 3 V to 5 V.
7–14 D7A–D0A Digital Outputs of ADC A.
22–15 D7B–D0B Digital Outputs of ADC B.
26 ENCODE Encode Clock for ADCs A and B
(ADCs Sample Simultaneously on the Rising Edge of ENCODE).
Table I. Digital Coding (VREF = 2.5 V)
Analog Input (V) Voltage Level Digital Output
3.0 Positive Full Scale 1111 1111
2.502 Midscale + 1/2 LSB 1000 0000
2.498 Midscale – 1/2 LSB 0111 1111
2.0 Negative Full Scale 0000 0000
REV. A–4–
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