ANALOG DEVICES AD 8625 ARZ Datasheet

Precision Low Power

Data Sheet

FEATURES

SC70 package
Very low I
Single-supply operation: 5 V to 26 V
Dual-supply operation: ±2.5 V to ±13 V
Rail-to-rail output
Low supply current: 630 μA/amp typ
Low offset voltage: 500 μV max
Unity gain stable
No phase reversal

APPLICATIONS

Photodiode amplifiers
AT Es
Line-powered/battery-powered instrumentation
Industrial controls
Automotive sensors
Precision filters
Audio

GENERAL DESCRIPTION

The AD862x is a precision JFET input amplifier. It features
true single-supply operation, low power consumption, and
rail-to-rail output. The outputs remain stable with capacitive
loads of over 500 pF; the supply current is less than 630 μA/amp.
Applications for the AD862x include photodiode transimpedance
amplification, ATE reference level drivers, battery management,
both line powered and portable instrumentation, and remote
sensor signal conditioning, which includes automotive sensors.

The AD862x’s ability to swing nearly rail-to-rail at the input
and rail-to-rail at the output enables it to be used to buffer
CMOS DACs, ASICs, and other wide output swing devices in
single-supply systems.

: 1 pA max

B

Single-Supply JFET Amplifiers

AD8625/AD8626/AD8627

PIN CONFIGURATIONS

8-Lead SOIC

(R-8 Suffix)

NC

1
2

–IN V+

AD8627

3

+IN OUT

4

V– NC

NC = NO CONNECT

8-Lead SOIC

(R-8 Suffix)

OUT A

1
2

–IN A OUT B

+IN A –IN B

OUT A OUT D

–IN A –IN D
+IN A +IN D

+IN B +IN C
–IN B –IN C

OUT B OUT C

AD8626

3

4

V– +IN B

14-Lead SOIC

(R-Suffix)

114
213
312

AD8625

V+ V–

411
510
69
78

NC

8
7

6

5

V+

8
7

6

5

Figure 1.

The 5 MHz bandwidth and low offset are ideal for precision filters.

The AD862x is fully specified over the industrial temperature
range. (−40°C to +85°C). e AD8627 is available in both
5-lead SC70 and 8-lead SOIC surface-mount packages (SC70
packaged parts are available in tape and reel only). The AD8626
is available in MSOP and SOIC packages, while the AD8625 is
available in TSSOP and SOIC packages.

5-Lead SC70

1
2

V–

+IN

3

8-Lead MSOP

1

4

14-Lead TSSOP

1

7

(KS Suffix)

AD8627

(RM-Suffix)

AD8626

(RU-Suffix)

AD8625

5OUT A

V+

–IN

4

8

V+OUT A
OUT B–IN A
–IN B+IN A
+IN BV–

5

14

OUT DOUT A
–IN D–IN A
+IN D+IN A
V–V+
+IN C+IN B
–IN C–IN B
OUT COUT B

8

03023-001

Rev. F Document Feedback

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Tel: [phone] ©2003–2013 Analog Devices, Inc. All rights reserved.

Technical Support www.analog.com

AD8625/AD8626/AD8627 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Pin Configurations ........................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics ............................................................. 3

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

REVISION HISTORY

5/13—Rev. E to Rev. F

Changes to Applications Information Section ............................ 13

Changes to Ordering Guide .......................................................... 20

12/10—Rev. D to Rev. E

Removed Table Summary Conditions Above Table 3 ................. 5

Updated Outline Dimensions ....................................................... 18

3/09—Rev. C to Rev. D

Updated Outline Dimensions ....................................................... 18

Changes to Ordering Guide .......................................................... 19

11/04—Rev. B to Rev. C

Updated Figure Codes ....................................................... Universal

Changes to Figure 17 and 18 ........................................................... 8

Changes to Figure 33 and Figure 37 ............................................. 11

Changes to Figure 38 ...................................................................... 12

Changes to Figure 39 and Figure 40 ............................................. 13

Changes to Figure 41 to Figure 44 ................................................ 14

Typical Performance Characteristics ..............................................6

Applications Information .............................................................. 13

Minimizing Input Current ........................................................ 15

Photodiode Preamplifier Application...................................... 15

Output Amplifier for DACs ...................................................... 16

Eight-Pole Sallen Key Low-Pass Filter ..................................... 17

Outline Dimensions ....................................................................... 18

Ordering Guide .......................................................................... 20

1/04—Rev. A to Rev. B

Change to General Description ....................................................... 1

Change to Figure 10 .......................................................................... 7

Change to Figure13 ........................................................................... 7

Change to Figure 37 ....................................................................... 11

Changes to Figure 38 ...................................................................... 12

Change to Output Amplifier for DACs Section ......................... 15

Updated Outline Dimensions ....................................................... 19

10/03—Rev. 0 to Rev. A

Addition of Two New Parts ............................................... Universal

Change to General Description ....................................................... 1

Changes to Pin Configurations ....................................................... 1

Change to Specifications Table ........................................................ 3

Changes to Figure 31 ...................................................................... 10

Changes to Figure 32 ...................................................................... 11

Changes to Figure 38 ...................................................................... 12

Changes to Figure 46 ...................................................................... 16

Changes to Figure 47 ...................................................................... 16

Changes to Figure 49 ...................................................................... 17

Updated Outline Dimensions ....................................................... 18

Changes to Ordering Guide .......................................................... 19

Rev. F | Page 2 of 20

Data Sheet AD8625/AD8626/AD8627

OUTPUT CHARACTERISTICS

Slew Rate

SR

5 V/µs

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

@VS = 5 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS 0.05 0.5 mV

−40°C < TA < +85°C 1.2 mV
Input Bias Current IB 0.25 1 pA
–40°C < TA < +85°C 60 pA
Input Offset Current IOS 0.5 pA
–40°C < TA < +85°C 25 pA
Input Voltage Range 0 3 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.5 V 66 87 dB
Large Signal Voltage Gain AVO RL = 10 kΩ, VO = 0.5 V to 4.5 V 100 230 V/mV
Offset Voltage Drift ∆VOS/∆T –40°C < TA < +85°C 2.5 µV/°C

Output Voltage High VOH 4.92 V
IL = 2 mA, –40°C < TA < +85°C 4.90 V
Output Voltage Low VOL 0.075 V
IL = 2 mA, –40°C < TA < +85°C 0.08 V
Output Current I

POWER SUPPLY

Power-Supply Rejection Ratio PSRR VS = 5 V to 26 V 80 104 dB

Supply Current/Amplifier ISY 630 785 µA
–40°C < TA < +85°C 800 µA
DYNAMIC PERFORMANCE

±10 mA

OUT

Gain Bandwidth Product GBP 5 MHz

Phase Margin ØM 60 Degrees
NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 1.9 µV p-p

Voltage Noise Density en f = 1 kHz 17.5 nV/√Hz

Current Noise Density in f = 1 kHz 0.4 fA/√Hz

Channel Separation Cs f = 1 kHz 104 dB

Rev. F | Page 3 of 20

AD8625/AD8626/AD8627 Data Sheet

Input Bias Current

IB

0.25 1 pA

Common-Mode Rejection Ratio

CMRR

V

= –13 V to +10 V

76

105 dB

NOISE PERFORMANCE

@VS = ±13 V; VCM = 0 V; TA = 25°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS 0.35 0.75 mV
–40°C < TA < +85°C 1.35 mV

–40°C < TA < +85°C 60 pA
Input Offset Current IOS 0.5 pA
–40°C < TA < +85°C 25 pA
Input Voltage Range –13 +11 V

CM

Large Signal Voltage Gain AVO RL = 10 kΩ, VO = –11 V to +11 V 150 310 V/mV
Offset Voltage Drift ∆VOS/∆T –40°C < TA < +85°C 2.5 µV/°C

OUTPUT CHARACTERISTICS

Output Voltage High VOH +12.92 V
VOH IL = 2 mA, –40°C < TA < +85°C +12.91 V
Output Voltage Low VOL –12.92 V
VOL IL = 2 mA, –40°C < TA < +85°C –12.91 V
Output Current I

POWER SUPPLY

Power-Supply Rejection Ratio PSRR VS = ±2.5 V to ±13 V 80 104 dB

Supply Current/Amplifier ISY 710 850 µA
–40°C < TA < +85°C 900 µA
DYNAMIC PERFORMANCE

Slew Rate SR 5 V/µs

Gain Bandwidth Product GBP 5 MHz

Phase Margin ØM 60 Degrees

±15 mA

OUT

Voltage Noise en p-p 0.1 Hz to 10 Hz 2.5 µV p-p

Voltage Noise Density en f = 1 kHz 16 nV/√Hz

Current Noise Density in f = 1 kHz 0.5 fA/√Hz

Channel Separation Cs f = 1 kHz 105 dB

Rev. F | Page 4 of 20

Data Sheet AD8625/AD8626/AD8627

−

Lead Temperature Range (Soldering, 60 sec)

300°C

ABSOLUTE MAXIMUM RATINGS

θ

is specified for worst-case conditions when devices are

Table 3.

Parameter Ratings

Supply Voltage 27 V
Input Voltage VS– to VS+
Differential Input Voltage ± Supply Voltage
Output Short-Circuit Duration Indefinite
Storage Temperature Range, R Package

Operating Temperature Range
Junction Temperature Range, R Package

−65°C to +125°C

40°C to +85°C

−65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

JA

soldered in circuit boards for surface-mount packages.

Table 4.

Package Type θJA θJC Unit

5-Lead SC70 (KS) 376 126 °C/W
8-Lead MSOP (RM) 210 45 °C/W
8-Lead SOIC (R) 158 43 °C/W
14-Lead SOIC (R) 120 36 °C/W
14-Lead TSSOP (RU) 180 35 °C/W

ESD CAUTION

Rev. F | Page 5 of 20

AD8625/AD8626/AD8627 Data Sheet

03023-002

VOLTAGE (

µ

V)

25

20

0

–600 –400

NUMBER OF AMPLIFIERS

–200

0

200 400

600

15

10

5

V

SY

=±12V

T

A

= 25

°

C

OFFSET VOLTAGE (µV/°C)

12

0

0 1 2 3 4 5 6 7 8 9 10

03023-003

NUMBER OF AMPLIFIERS

6

4

2

8

10

V

SY

=±13V

VOLTAGE (

µ

V)

18

16

14

12

10

8

6

4

2

0

–

400 –300 –200 –100 0 100 200 300

03023-004

NUMBER OF AMPLIFIERS

V

SY

= +3.5V/–1.5V

OFFSET VOLTAGE (µV/°C)

16

14

12

10

8

6

4

2

0

0

1

2 3 4 5 6 7 8 9 10

03023-005

NUMBER OF AMPLIFIERS

VSY = +3.5V/–1.5V

V

CM

(V)

50

–50

–40

–30

–

20

–10

0

10

20

30

40

–

15.0–12.5

–10.0 –

7.5 –5.0 –2.5 0 2.5 5.0 7.5 10.0 12.5 15.0

03023-006

INPUT BIAS CURRENT (pA)

V

SY

=±13V

T

A

= 25°C

VCM (V)

–0.9

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

–15.0–12.5–10.0 –7.5 –

5.0 –2.5 0 2.5 5.0 7.5 10.0 12.5 15.0

03023-007

INPUT BIAS CURRENT (pA)

VSY =±13V
TA = 25

°

C

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 2. Input Offset Voltage

Figure 3. Offset Voltage Drift

Figure 5. Offset Voltage Drift

Figure 6. Input Bias Current vs. V

CM

Figure 4. Input Offset Voltage

Figure 7. Input Bias Current vs. VCM

Rev. F | Page 6 of 20

Data Sheet AD8625/AD8626/AD8627

TEMPERATURE (°C)

0.1

100

10

1

–

50 –

25

0 25

50 75

100

125 150

03023-008

INPUT BIAS CURRENT (pA)

V

SY

=±13V

V

CM

= 0V

V

CM

(V)

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

–

5 –4

–3 –

2 –

1 0

1

2

3 4

5

03023-009

INPUT BIAS CURRENT (pA)

V

SY

= +5V OR

±

5V

VCM (V)

–100

0

100

200

300

400

500

600

700

800

900

1000

–15 –12 –9 –6 –3 0 3 6 9 12 15

03023-010

INPUT OFFSET VOLTAGE (

µ

V)

V

SY

=±13V

V

CM

(V)

–500

–400

–300

–200

–100

0

100

200

300

400

500

–1 0 1 2

3

4

03023-011

INPUT OFFSET VOLTAGE (

µ

V)

V

SY

= 5V

LOAD RESI STANCE (kΩ)

10k

100k

1M

10M

0.1 1 10 100

03023-012

OPEN-LOOP GAIN (V/V)

VSY = +5V

V

SY

=±13V

TEMPERATURE (°C)

1

10

100

1000

–40 25 95 125

03023-013

OPEN-LOOP GAIN (V/mV)

e

c

b

d

a

a. VSY =±13V, VO =±11V, RL = 10kΩ
b. VSY =±13V, VO =±11V, RL = 2kΩ
c. VSY = +5V, VO = +0.5V/+4.5V, RL = 2kΩ
d. VSY = +5V, VO = +0.5V/+4.5V, R

L

= 10kΩ

e. VSY = +5V, VO = +0.5V/+4.5V, RL = 600Ω

Figure 8. Input Bias Current vs. Temperature

Figure 9. Input Bias Current vs. V

CM

Figure 11. Input Offset Voltage vs. V

CM

Figure 12. Open-Loop Gain vs. Load Resistance

Figure 10. Input Offset Voltage vs. V

CM

Figure 13. Open-Loop Gain vs. Temperature

Rev. F | Page 7 of 20

AD8625/AD8626/AD8627 Data Sheet

OUTPUT VOLTAGE (V)

–400

–300

–200

–100

0

100

200

300

400

500

600

–15 –10 –5 0 5 10 15

03023-014

OFFSET VOLTAGE (

µ

V)

VSY = ±13V

R

L

= 100kΩ

RL = 10kΩ

RL = 600Ω

OUTPUT VOLTAGE FROM SUPPLY RAILS (mV)

–250

–200

–150

–100

–50

0

50

100

150

200

250

0 50 100 150 200 250 300

03023-015

INPUT VOLTAGE (

µ

V)

NEG RAIL

POS RAIL

V

SY

= ±5V

R

L

= 1kΩ

RL = 100kΩ

RL = 10kΩ

RL = 10kΩ

RL = 1kΩ

TOTAL SUPPLY VOLTAGE (V)

0

100

200

300

400

500

600

700

800

0 4 8 12

16 20 24 28

03023-016

QUIESCENT CURRENT (

µ

A)

+125

°

C

+25°C

–55

°C

LOAD CURRENT ( mA)

1

10

100

1k

10k

0.001 0.01

0.1 1

10 100

03023-017

V

SY

–

OUTPUT VOLTAGE (mV)

V

OH

V

OL

VSY =

±

13V

LOAD CURRENT ( mA)

1

10

100

1k

10k

0.001 0.01

0.1 1 10 100

03023-018

V

SY

– OUTPUT VOLTAGE (mV)

V

SY

= 5V

V

OL

V

OH

FREQUENCY ( Hz)

–30 –135

–90

–45

–0

45

90

135

180

225

270

315

–20

–10

0

10

20

30

40

50

60

70

10k 100k 1M 10M 50M

03023-019

GAIN (dB)

PHASE (Degrees)

GAIN

PHASE

VSY =±13V
R

L

= 2k

Ω

CL = 40pF

Figure 14. Input Error Voltage vs. Output Voltage for Resistive Loads

Figure 15. Input Error Voltage vs. Output Voltage within 300 mV of

Supply Rails

Figure 17. Output Saturation Voltage vs. Load Current

Figure 18. Output Saturation Voltage vs. Load Current

Figure 16. Quiescent Current vs. Supply Voltage at Different Temperatures

Figure 19. Open-Loop Gain and Phase Margin vs. Frequency

Rev. F | Page 8 of 20

Data Sheet AD8625/AD8626/AD8627

FREQUENCY ( Hz)

–

30 –

135

–

90

–45

–

0

45

90

135

180

225

270

315

–20

–10

0

10

20

30

40

50

60

70

10k 100k

1M 10M

50M

03023-020

GAIN (dB)

PHASE (Degrees)

V

SY

= 5V

R

L

= 2k

Ω

C

L

= 40pF

GAIN

PHASE

FREQUENCY ( Hz)

–30

–20

–10

0

10

20

30

40

50

60

70

1k 10k 100k 1M 10M 50M

03023-021

GAIN (dB)

G = +100

G = +1

G = +10

V

SY

=

±

13V

R

L

= 2k

Ω

C

L

= 40pF

FREQUENCY ( Hz)

–30

–20

–10

0

10

20

30

40

50

60

70

1k 10k 100k 1M 10M 50M

03023-022

GAIN (dB)

G = +100

G = +1

G = +10

V

SY

= 5V

R

L

= 2k

Ω

C

L

= 40pF

FREQUENCY ( Hz)

–60

–40

–20

0

20

40

60

80

100

120

140

1k 10k 100k 1M 10M

03023-023

CMRR (dB)

V

SY

=

±

13V

FREQUENCY ( Hz)

–60

–40

–20

0

20

40

60

80

100

120

140

1k 10k 100k 1M 10M

03023-024

CMRR (dB)

V

SY

= 5V

FREQUENCY ( Hz)

–60

–40

–20

0

20

40

60

80

100

120

140

1k 10k 100k 1M 10M

03023-025

PSRR (dB)

+PSRR

–PSRR

V

SY

=

±

13V

Figure 20. Open-Loop Gain and Phase Margin vs. Frequency

Figure 21. Closed-Loop Gain vs. Frequency

Figure 23. CMRR vs. Frequency

Figure 24. CMRR vs. Frequency

Figure 22. Closed-Loop Gain vs. Frequency

Figure 25. PSRR vs. Frequency

Rev. F | Page 9 of 20

AD8625/AD8626/AD8627 Data Sheet

FREQUENCY ( Hz)

–60

–40

–20

0

20

40

60

80

100

120

140

1k 10k 100k 1M 10M

03023-026

PSRR (dB)

+PSRR

–PSRR

V

SY

= 5V

FREQUENCY ( Hz)

0

30

60

90

120

150

180

210

240

270

300

1k 10k 100k 1M 100M10M

03023-027

Z

OUT

(Ω)

G = +100

G = +1

G = +10

V

SY

= ±

13V

FREQUENCY ( Hz)

0

30

60

90

120

150

180

210

240

270

300

1k 10k 100k 1M 100M10M

03023-028

Z

OUT

(Ω)

G = +100

G = +1

G = +10

V

SY

= 5V

TIME (400

µ

s/DIV)

03023-029

VOLTAGE (10V/DIV)

INPUT

OUTPUT

V

SY

=

±

13V

SETTLING TIME (

µ

s)

–15

–

10

–5

0

5

10

15

0

0.5 1.0

1.5

2.52.0

03023-030

OUTPUT SWING (V)

TS + (1%)

TS + (0.1%)

TS

–

(1%)

TS –

(0.1%)

CAPACITANCE (p F)

0

10

60

50

40

30

20

70

10 100 1k

03023-031

OVERSHOOT (%)

OS–

OS+

V

S

=

±

13V

R

L

= 10k

Ω

V

IN

= 100mV p-p

A

V

= +1

Figure 26. PSRR vs. Frequency

Figure 27. Output Impedance vs. Frequency

Figure 30. Output Swing and Error vs. Settling Time

Figure 29. No Phase Reversal

Figure 28. Output Impedance vs. Frequency

Figure 31. Small-Signal Overshoot vs. Load Capacitance

Rev. F | Page 10 of 20

Data Sheet AD8625/AD8626/AD8627

CAPACITANCE (p F)

0

10

50

40

30

20

70

60

10 100 1k

03023-032

OVERSHOOT (%)

OS–

OS+

V

S

= ±2.5V

R

L

= 10k

Ω

V

IN

= 100mV p-p

A

V

= +1

TIME (1s/DIV)

03023-033

VOLTAGE (50mV/DIV)

VSY =±13V
AVO = 100,000V/V

0

TIME (1s/DIV)

03023-034

VOLTAGE (50mV/DIV)

0

VSY =±2.5V
AVO = 100,000V/V

FREQUENCY ( kHz)

0 1 2 3 4 5 6 7 8 9 10

03023-035

VOLTAGE (nV)

28

35

42

49

56

21

14

7

0

V

SY

=

±

13V

19.7nV/ Hz

FREQUENCY ( kHz)

0

1 2 3 4

5 6 7 8 9

10

03023-036

VOLTAGE (nV)

28

35

42

49

56

21

14

7

0

V

SY

= 5V

16.7nV/ Hz

FREQUENCY ( Hz)

10 100 1k 10k 100k

03023-037

THD + NOISE (dB)

–40

–110

–100

–90

–80

–70

–60

–50

VSY =±5V, V

IN

= 9V p-p

V

SY

=

±

13V, VIN = 18V p-p

V

SY

=±2.5V, VIN = 4.5V p-p

Figure 32. Small-Signal Overshoot vs. Load Capacitance

Figure 35. Voltage Noise Density

Figure 33. 0.1 Hz to 10 Hz Noise

Figure 36. Voltage Noise Density

Figure 34. 0.1 Hz to 10 Hz Noise

Figure 37. Total Harmonic Distortion + Noise vs. Frequency

Rev. F | Page 11 of 20

AD8625/AD8626/AD8627 Data Sheet

FREQUENCY ( Hz)

–160

–150

–140

–130

–120

–

110

–

100

–90

–

80

10

100 1k 10k

100k

03023-049

CHANNEL SEPARATION (dB)

V

IN

2k

Ω

2kΩ

2k

Ω

20k

Ω

V

IN

= 9V p-p

V

IN

= 4.5V p-p

VIN = 18V p-p

Figure 38. Channel Separation

Rev. F | Page 12 of 20

Data Sheet AD8625/AD8626/AD8627

TIME (2µs/DIV)

03023-038

VOLTAGE (2V/DIV)

INPUT

OUTPUT

V

SY

= 5V

4V

4V

0V

0V

TIME (2µs/DIV)

03023-039

VOLTAGE (2V/DIV)

INPUT

OUTPUT

V

SY

= 5V

4V

0V

5V

0V

APPLICATIONS INFORMATION

The AD862x is one of the smallest and most economical
JFETs offered. It has true single-supply capability and has
an input voltage range that extends below the negative rail,
allowing the part to accommodate input signals below ground.
The rail-to-rail output of the AD862x provides the maximum
dynamic range in many applications. To provide a low offset,
low noise, high impedance input stage, the AD862x uses
n-channel JFETs. The input common-mode voltage extends
from 0.2 V below –V
the amplifier, configured in the unity gain buffer, closer than
2 V to the positive rail causes an increase in common-mode
voltage error, as illustrated in Figure 15, and a loss of amplifier
bandwidth. This loss of bandwidth causes the rounding of the
output waveforms shown in Figure 39 and Figure 40, which
have inputs that are 1 V and 0 V from +V

The AD862x does not experience phase reversal with input
signals close to the positive rail, as shown in Figure 29. For
input voltages greater than +V
AD862x’s noninverting input prevents phase reversal at the
expense of greater input voltage noise. This current-limiting
resistor should also be used if there is a possibility of the input
voltage exceeding the positive supply by more than 300 mV, or
if an input voltage is applied to the AD862x when ±V
Either of these conditions damages the amplifier if the
condition exists for more than 10 seconds. A 10 kΩ resistor
allows the amplifier to withstand up to 10 V of continuous
overvoltage, while increasing the input voltage noise by a
negligible amount.

to 2 V below +VS. Driving the input of

S

, respectively.

S

, a resistor in series with the

SY

= 0.

SY

Figure 39. Unity Gain Follower Response to 0 V to 4 V Step

Figure 40. Unity Gain Follower Response to 0 V to 5 V Step

Rev. F | Page 13 of 20

AD8625/AD8626/AD8627 Data Sheet

TIME (2µs/DIV)

03023-040

VOLTAGE (1V/DIV)

+5V

20k

Ω

10k

Ω

0V

–2.5V

V

SY

= 5V, 0V

5V

0V

TIME (2µs/DIV)

03023-041

VOLTAGE (10mV/DIV)

5V

60mV

20mV

600

Ω

0V

VSY = 5V
RL = 600Ω

0V

TIME (2

µ

s/DIV)

03023-042

VOLTAGE (10mV/DIV)

+5V

20k

Ω

10k

Ω

–10mV

–30mV

0V

VSY = 5V

0V

TIME (5µs/DIV)

03023-043

VOLTAGE (5V/DIV)

VSY =

±

13V

R

L

= 600

Ω

0V

The AD862x can safely withstand input voltages 15 V below
V

if the total voltage between the positive supply and the input

SY

terminal is less than 26 V. Figure 41 through Figure 43 show the
AD862x in different configurations accommodating signals
close to the negative rail. The amplifier input stage typically
maintains picoamp-level input currents across that input
voltage range.

Figure 41. Gain-of-Two Inverter Response to 2.5 V Step,

Centered 1.25 V below Ground

Figure 43. Gain-of-Two Inverter Response to 20 mV Step,

Centered 20 mV below Ground

The AD862x is designed for 16 nV/√Hz wideband input voltage
noise and maintains low noise performance to low frequencies,
as shown in Figure 35. This noise performance, along with the
AD862x’s low input current and current noise, means that the
AD862x contributes negligible noise for applications with large
source resistances.

The AD862x has a unique bipolar rail-to-rail output stage that
swings within 5 mV of the rail when up to 2 mA of current is
drawn. At larger loads, the drop-out voltage increases, as shown
in Figure 17 and Figure 18. The AD862x’s wide bandwidth and
fast slew rate allows it to be used with faster signals than older
single-supply JFETs. Figure 44 shows the response of the
AD862x, configured in unity gain, to a V

of 20 V p-p at

IN

50 kHz. The full-power bandwidth (FPBW) of the part is close
to 100 kHz.

Figure 42. Unity Gain Follower Response to 40 mV Step,

Centered 40 mV above Ground

Figure 44. Unity Gain Follower Response to 20 V, 50 kHz Input Signal

Rev. F | Page 14 of 20

Data Sheet AD8625/AD8626/AD8627

f

p

f

OUT

(P)RR)ID(RV −=−=

)(IR

V

R

R

V

B

f

OS

D

f

E

+















+

=

1

03023-044

R

D

100MΩ

C4
15pF

I

B

I

B

V

OS

C

F

5pF

R

F

1.5M

Ω

OUTPUT

AD8627

PHOTODIODE

MINIMIZING INPUT CURRENT

The AD862x is guaranteed to 1 pA maximum input current
with a ±13 V supply voltage at room temperature. Careful
attention to how the amplifier is used maintains or possibly
betters this performance. The amplifier’s operating temperature
should be kept as low as possible. Like other JFET input ampli­fiers, the AD862x’s input current doubles for every 10°C rise in
junction temperature, as illustrated in Figure 8. On-chip power
dissipation raises the device operating temperature, causing an
increase in input current. Reducing supply voltage to cut power
dissipation reduces the AD862x’s input current. Heavy output
loads can also increase chip temperature; maintaining a
minimum load resistance of 1 kΩ is recommended.

The AD862x is designed for mounting on PC boards. Main­taining picoampere resolution in those environments requires
a lot of care. Both the board and the amplifier’s package have
finite resistance. Voltage differences between the input pins and
other pins, as well as PC board metal traces may cause parasitic
currents larger than the AD862x’s input current, unless special
precautions are taken. To ensure the best result, refer to the ADI
website for proper board layout seminar materials. Two
common methods of minimizing parasitic leakages that should
be used are guarding of the input lines and maintaining
adequate insulation resistance.

Contaminants, such as solder flux on the board’s surface and
the amplifier’s package, can greatly reduce the insulation
resistance between the input pin and traces with supply or
signal voltages. Both the package and the board must be kept
clean and dry.

PHOTODIODE PREAMPLIFIER APPLICATION

The low input current and offset voltage levels of the AD862x,
together with its low voltage noise, make this amplifier an
excellent choice for preamplifiers used in sensitive photodiode
applications. In a typical photovoltaic preamp circuit, shown in
Figure 45, the output of the amplifier is equal to

where:

ID = photodiode signal current (A).
R

= photodiode sensitivity (A/W).

p

R

= value of the feedback resistor, in Ω.

f

P = light power incident to photodiode surface, in W.

The amplifier’s input current, I
error proportional to the value of the feedback resistor. The
offset voltage error, V

, causes a small current error due to the

OS

photodiode’s finite shunt resistance, R
The resulting output voltage error, VE, is equal to

A shunt resistance on the order of 100 MΩ is typical for a small
photodiode. Resistance RD is a junction resistance that typically
drops by a factor of two for every 10°C rise in temperature. In
the AD862x, both the offset voltage and drift are low, which
helps minimize these errors. With I
50 mV, V

for Figure 45 is very negligible. Also, the circuit in

E

Figure 45 results in an SNR value of 95 dB for a signal bandwidth
of 30 kHz.

Figure 45. A Photodiode Model Showing DC Error

, contributes an output voltage

B

D.

values of 1 pA and VOS of

B

Rev. F | Page 15 of 20

AD8625/AD8626/AD8627 Data Sheet

03023-045

AD5551/AD5552

AD8627

DGND

*AD5552 ONLY

V

DD

V

REFF

* V

REFS

*

OUT

SCLK

DIN

CS

AGND

5V

2.5V

UNIPOLAR

OUTPUT

LDAC*

0.1µF

10

µ

F

0.1

µ

F

SERIAL

INTERFACE

5V

03023-046

ONE CHANNEL

AD5544

1/2

AD8626

DIGITAL INTERFACE CONNECTIONS
OMITTED FOR CLARITY

VSSA

GND

F A

GND

X

V

DD

V

REF

X

RFBX

ADR01

VREF

10V

1/2

AD8626

–13V

+13V

–10V < V

OUT

< +10V

10k

Ω

5k

Ω

10k

Ω

V

OUT

OUTPUT AMPLIFIER FOR DACs

Many system designers use amplifiers as buffers on the output
of amplifiers to increase the DAC’s output driving capability.
The high resolution current output DACs need high precision
amplifiers on their output as current-to-voltage converters

(I/V). Additionally, many DACs operate with a single supply of
5 V. In a single-supply application, selection of a suitable op
amp may be more difficult because the output swing of the
amplifier does not usually include the negative rail, in this case
AGND. This can result in some degradation of the DAC’s
specified performance, unless the application does not use
codes near zero. The selected op amp needs to have very low
offset voltage—for a 14-bit DAC, the DAC LSB is 300 µV with a
5 V reference—to eliminate the need for output offset trims.
Input bias current should also be very low because the bias
current multiplied by the DAC output impedance (about 10 kΩ
in some cases) adds to the zero-code error. Rail-to-rail input and
output performance is desired. For fast settling, the slew rate of
the op amp should not impede the settling time of the DAC.
Output impedance of the DAC is constant and code
independent, but in order to minimize gain errors, the input
impedance of the output amplifier should be as high as possible.
The AD862x, with a very high input impedance, I

and a fast slew rate, is an ideal amplifier for these types of
applications. A typical configuration with a popular DAC is
shown in Figure 46. In these situations, the amplifier adds
another time constant to the system, increasing the settling time
of the output. The AD862x, with 5 MHz of BW, helps in
achieving a faster effective settling time of the combined DAC
and amplifier.

In applications with full 4-quadrant multiplying capability or a
bipolar output swing, the circuit in Figure 47 can be used. In
this circuit, the first and second amplifiers provide a total gain
of 2, which increases the output voltage span to 20 V. Biasing
the external amplifier with a 10 V offset from the reference
voltage results in a full 4-quadrant multiplying circuit.

Figure 46. Unipolar Output

of 1 pA,

B

Figure 47. 4-Quadrant Multiplying Application Circuit

Rev. F | Page 16 of 20

Data Sheet AD8625/AD8626/AD8627

03023-047

V2

V4

V3

V1

FREQUENCY (Hz)

VOLTAGE (V)

0.1

0

0.4

0.8

1.2

1 10 100 1k

03023-048

V

IN

V

DD

V

EE

R1

162.3k

Ω

R2

162.3k

Ω

3

2

11

1

4

U1

R3

25k

Ω

C2

96.19µF
D

D

V3

R10

191.4k

Ω

R5

191.4k

Ω

U2

R4

25k

Ω

C4

69.14µF
D

R11

286.5k

Ω

R7

286.5k

Ω

U3

R6

25k

Ω

C6

30.86µF
D

R12

815.8k

Ω

R9

815.8k

Ω

U4

R8

25k

Ω

C8

3.805µF
D

C1

100µF

C3

1/4

AD8625

1/4

AD8625

1/4

AD8625

1/4

AD8625

100

µ

F

C5

100µF

C7

100µF

V1

V2

V3

V4

EIGHT-POLE SALLEN KEY LOW-PASS FILTER

The AD862x’s high input impedance and dc precision make it a
great selection for active filters. Due to the very low bias current
of the AD862x, high value resistors can be used to construct low
frequency filters. The AD862x’s picoamp-level input currents
contribute minimal dc errors. Figure 49 shows an example of a
10 Hz, 8-pole Sallen Key filter constructed using the AD862x.
Different numbers of the AD862x can be used depending on
the desired response, which is shown in Figure 48. The high
value used for R1 minimizes interaction with signal source
resistance. Pole placement in this version of the filter minimizes
the Q associated with the lower pole section of the filter. This
eliminates any peaking of the noise contribution of resistors in
the preceding sections, minimizing the inherent output voltage
noise of the filter.

Figure 48. Frequency Response Output at Different Stages

of the Low-Pass Filter

Figure 49. 10 Hz, 8-Pole Sallen Key Low-Pass Filter

Rev. F | Page 17 of 20

AD8625/AD8626/AD8627 Data Sheet

CO

MP

L

IA

NT TO JEDEC STANDARDS MO-203-AA

1.00

0.

90

0

.

70

0.

4

6

0.36

0.

2

6

2.

20

2

.0

0

1.80

2

.

40

2.10
1

.

80

1

.3

5

1

.2

5

1.15

0

72

80

9

-A

0.10 MAX

1

.1

0

0

.8

0

0.40
0

.1

0

0.22

0.08

3

1 2

45

0.65BSC

CO

PL

A

NA

RI

T

Y

0.10

SEATING
P

LA

NE

0.

3

0

0.15

CONTROLLING DIMENSION

S AR

E IN MIL

LIM

ETER

S; I

NCH

DIMENSIONS

(

IN P

ARE

NTH

ESES

) ARE ROUNDED-OFF MI

LLIM

ETE

R EQU

IVA

LENT

S FO

R

REF

ERE

NCE ONL

Y AN

D AR

E NO

T APP

ROPRIATE FOR USE IN

DESI

GN.

CO

MPLIAN

T TO J

EDEC

STANDARDS MS-012-AA

012407-A

0.25 (0.0098)

0.17 (0.0067)

1.27 (0.0500)

0.40 (0.0157)

0.50 (0.0196)

0.25 (0.0099)

45°

8°
0°

1.75 (0.0688)

1.35 (0.0532)

SEATING

PLANE

0.25 (0.0098)

0.10 (0.0040)

4

1

8 5

5.00(0.1968)

4.80(0.1890)

4.00 (0.1574)

3.80 (0.1497)

1.27 (0.0500)
BSC

6.20 (0.2441)

5.80 (0.2284)

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

OUTLINE DIMENSIONS

Figure 50. 5-Lead Plastic Surface-Mount Package [SC70]

(KS-5)

Dimensions shown in millimeters

Figure 51. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

Rev. F | Page 18 of 20

Data Sheet AD8625/AD8626/AD8627

CO

MP

L

IA

NT

T

O J

E

DE

C S

T

AN

DA

R

DS

MO

-

18

7

-A

A

6°
0

°

0.80
0

.5

5

0.40

4

8

1

5

0.65 BSC

0.40
0

.2

5

1.10 MAX

3

.2

0

3.

00

2.

8

0

CO

P

LA

NA

R

IT

Y

0

.

10

0.

23

0

.0

9

3.

20

3

.0

0

2

.8

0

5

.

15

4.

90

4

.6

5

PI

N

1

I

D

EN

TI

F

IE

R

1

5°

M

AX

0

.

95

0.

8

5

0.

7

5

0.

1

5

0

.

05

10-07-2009

-B

CONTROLLING DIMENSIONSARE IN MI LLIMETERS; INCH DI M E NS IONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE O NLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AB

060606-A

14

8

7

1

6.20 (0.2441)

5.80 (0.2283)

4.00 (0.1575)

3.80 (0.1496)

8.75 (0.3445)

8.55 (0.3366)

1.27 (0.0500)
BSC

SEATING
PLANE

0.25 (0.0098)

0.10 (0.0039)

0.51 (0.0201)

0.31 (0.0122)

1.75 (0.0689)

1.35 (0.0531)

0.50 (0.0197)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

0.25 (0.0098)

0.17 (0.0067)

COPLANARITY

0.10

8°
0°

45°

COMPLI ANT TO JEDEC STANDARDS MO-153-AB- 1

061908-A

8°
0°

4.50

4.40

4.30

14

8

7

1

6.40

BSC

PIN 1

5.10

5.00

4.90

0.65 BSC

0.15

0.05

0.30

0.19

1.20
MAX

1.05

1.00

0.80

0.20

0.09

0.75

0.60

0.45

COPLANARITY

0.10

SEATING
PLANE

Figure 52. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

Figure 53. 14-Lead Standard Small Outline Package [SOIC_N]

(R-14)

Dimensions shown in millimeters and (inches)

Figure 54. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

Rev. F | Page 19 of 20

AD8625/AD8626/AD8627 Data Sheet

Model

Temperature Range

Package Description

Package Option

Branding

AD8626ARZ-REEL7

–40°C to +85°C

8-Lead SOIC_N

R-8

AD8627AKSZ-REEL7

–40°C to +85°C

5-Lead SC70

KS-5

B9B

AD8627AKSZ-R2

–40°C to +85°C

5-Lead SC70

KS-5

B9B

©2003–2013 Analog Devices, Inc. All rights reserved. Trademarks and

ORDERING GUIDE

1, 2

AD8625ARUZ –40°C to +85°C 14-Lead TSSOP RU-14
AD8625ARUZ-REEL –40°C to +85°C 14-Lead TSSOP RU-14
AD8625ARZ –40°C to +85°C 14-Lead SOIC_N R-14
AD8625ARZ-REEL –40°C to +85°C 14-Lead SOIC_N R-14
AD8625ARZ-REEL7 –40°C to +85°C 14-Lead SOIC_N R-14
AD8626ARMZ-REEL –40°C to +85°C 8-Lead MSOP RM-8 BJA
AD8626ARMZ –40°C to +85°C 8-Lead MSOP RM-8 BJA
AD8626ARZ –40°C to +85°C 8-Lead SOIC_N R-8
AD8626ARZ-REEL –40°C to +85°C 8-Lead SOIC_N R-8

AD8627AKSZ-REEL –40°C to +85°C 5-Lead SC70 KS-5 B9B

AD8627ARZ –40°C to +85°C 8-Lead SOIC_N R-8
AD8627ARZ-REEL –40°C to +85°C 8-Lead SOIC_N R-8
AD8627ARZ-REEL7 –40°C to +85°C 8-Lead SOIC_N R-8

1

Z = RoHS Compliant Part; # denotes product may be top or bottom marked.

2

For the AD8627AKS models, pre-0542 parts were branded with B9A without #.

registered trademarks are the property of their respective owners.
D03023-0-5/13(F)

Rev. F | Page 20 of 20