ANALOG DEVICES AD8564 Service Manual
Quad 7 ns
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FEATURES
5 V single-supply operation
7 ns propagation delay
Low power
Separate input and output sections
TTL/CMOS logic-compatible outputs
Wide output swing
TSSOP, SOIC, and PDIP packages
APPLICATIONS
High speed timing
Line receivers
Data communications
High speed V-to-F converters
Battery operated instrumentation
High speed sampling systems
Window comparators
PCMCIA cards
Upgrade for MAX901 designs
Single Supply Comparator
AD8564
PIN CONFIGURATIONS
–IN A
+IN A
GND
OUT A
OUT B
V
–ANA
+IN B
–IN B
116
AD8564
89
Figure 1. 16-Lead TSSOP
U-16)
(R
–IN A
+IN A
GND
OUT A
OUT B
V
–ANA
+IN B
–IN B
AD8564
Figure 2. 16-Lead Narrow Body SOIC
(R
-16)
1
–IN A
2
+IN A
GND
OUT A
V
–ANA
+IN B
–IN B
3
4
5
6
7
8
–
+
AD8564
–
+
Figure 3. 16-Lead PDIP
(N-16)
–IN D
+IN D
V
+ANA
OUT D
OUT C
V
+DIG
+IN C
–IN C
1103-003
–IN D
+IN D
V
+ANA
OUT D
OUT C
V
+DIG
+IN C
–IN C
01103-001
16
–IN D
15
+IN D
–
+
V
14
+ANA
13
OUT D
12
OUT COUT B
V
11
+DIG
–
+
+IN C
10
–IN C
9
01103-002
GENERAL DESCRIPTION
The AD8564 is a quad 7 ns comparator with separate input and
output supplies, thus enabling the input stage to be operated
from ±5 V dual supplies or a 5 V single supply while maintaining a
CMOS-/TTL-compatible output.
Fast 7 ns propagation delay makes the AD8564 a good choice
for
timing circuits and line receivers. Independent analog and
digital supplies provide excellent protection from supply pin
interaction. The AD8564 is pin compatible with the MAX901
and has lower supply currents.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
All four comparators have similar propagation delays. The
ropagation delay for rising and falling signals is similar, and
p
tracks over temperature and voltage. These characteristics make
the AD8564 a good choice for high speed timing and data
communications circuits. For a similar single comparator with
latch function, refer to the
The AD8564 is specified over the industrial temperature range
°C to +125°C). The quad AD8564 is available in the 16-lead
(−40
TSSOP, 16-lead narrow body SOIC, and 16-lead plastic DIP
packages.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1999–2007 Analog Devices, Inc. All rights reserved.
AD8561 data sheet.
AD8564
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features.............................................................................................. 1
ESD Caution...................................................................................5
Applications....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
REVISION HISTORY
8/07—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Applications .................................................................. 1
Changes to General Description .................................................... 1
Changes to Specifications................................................................ 3
Changes to the Absolute Maximum Ratings Section .................. 5
Changes to the Applications Information Section....................... 9
Deleted Spice Model Section......................................................... 11
Updated Outline Dimensions....................................................... 12
Changes to Ordering Guide.......................................................... 13
Typical Performance Characteristics..............................................6
Applications Information.................................................................9
Optimizing High Speed Performance........................................9
Output Loading Considerations..................................................9
Input Stage and Bias Currents .....................................................9
Using Hysteresis ......................................................................... 10
Outline Dimensions....................................................................... 11
Ordering Guide .......................................................................... 12
6/99—Rev. 0 to Rev. A
Rev. B | Page 2 of 12
AD8564
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SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
V
= V
+ANA
= 5.0 V, V
+DIG
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 2.3 7 mV
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift ΔVOS/ΔT 4 μV/°C
Input Bias Current IB VCM = 0 V ±4 μA
−40°C ≤ TA ≤ +125°C
Input Offset Current IOS VCM = 0 V ±3 μA
Input Common-Mode Voltage Range VCM 0 2.75 V
Common-Mode Rejection Ratio CMRR 0 V ≤ VCM ≤ 3.0 V 65 85 dB
Large Signal Voltage Gain A
Input Capacitance CIN 3.0 pF
DIGITAL OUTPUTS
Logic 1 Voltage VOH IOH = −3.2 mA, ΔVIN > 250 mV 2.4 3.5 V
Logic 0 Voltage VOL IOL = 3.2 mA, VIN > 250 mV 0.3 0.4 V
DYNAMIC PERFORMANCE2
Propagation Delay tP 200 mV step with 100 mV overdrive 6.75 9.8 ns
−40°C ≤ TA ≤ +125°C1 13 ns
100 mV step with 5 mV overdrive 8 ns
Differential Propagation Delay (Rising Propagation Delay vs.
Falling Propagation Delay)
Rise Time 20% to 80% 3.8 ns
Fall Time 20% to 80% 1.5 ns
POWER SUPPLY
Power Supply Rejection Ratio PSRR 4.5 V ≤ V
Analog Supply Current I
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C1 17 mA
Digital Supply Current I
−40°C ≤ TA ≤ +125°C1 8.0 mA
Analog Supply Current I
−40°C ≤ TA ≤ +85°C1 15.6 mA
−40°C ≤ TA ≤ +125°C1 17 mA
1
Full electrical specifications to −55°C, but these package types are guaranteed for operation from −40°C to +125°C only. Package reliability below −40°C is not guaranteed.
2
Guaranteed by design.
= 0 V, TA = 25°C, unless otherwise noted.
−ANA
1
1
R
VO
Δt
100 mV step with 20 mV overdrive 0.5 2.0 ns
P
10.5 14.0 mA
+ANA
VO = 0 V, RL = ∞ 6.0 7.0 mA
DIG
–7.0 +14.0 mA
−ANA
= 10 kΩ 3000 V/V
L
+ANA
and V
≤ 5.5 V 80 dB
+DIG
1
8 mV
±9 μA
15.6 mA
Rev. B | Page 3 of 12
AD8564
www.BDTIC.com/ADI
V
= V
+ANA
= 5.0 V, V
+DIG
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 2.3 7 mV
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift ΔVOS/ΔT 4 μV/°C
Input Bias Current IB VCM = 0 V ±4 μA
−40°C ≤ TA ≤ +125°C
Input Offset Current IOS VCM = 0 V ±3 μA
Input Common-Mode Voltage Range VCM −4.9 +3.5 V
Common-Mode Rejection Ratio CMRR 0 V ≤ VCM ≤ 3.0 V 65 85 dB
Large Signal Voltage Gain AVO RL = 10 kΩ 3000 V/V
Input Capacitance CIN 3.0 pF
DIGITAL OUTPUTS
Logic 1 Voltage VOH IOH = –3.2 mA, ΔVIN > +250 mV 2.6 3.6 V
Logic 0 Voltage VOL IOL = 3.2 mA, ΔVIN > 250 mV 0.2 0.3 V
DYNAMIC PERFORMANCE2
Propagation Delay tP 200 mV step with 100 mV overdrive 6.75 9.8 ns
−40°C ≤ TA ≤ +85°C1 8 13 ns
100 mV step with 5 mV overdrive 8 ns
Differential Propagation Delay (Rising Propagation Delay
vs. Falling Propagation Delay)
Rise Time 20% to 80% 3 ns
Fall Time 20% to 80% 3 ns
POWER SUPPLY
Power Supply Rejection Ratio PSRR 4.5 V ≤ V
Analog Supply Current I
−40°C ≤ TA ≤ +85°C1 15.6 mA
−40°C ≤ TA ≤ +125°C
Digital Supply Current I
−40°C ≤ TA ≤ +125°C1 5.6 mA
Analog Supply Current I
−40°C ≤ TA ≤ +85°C1 15.6 mA
−40°C ≤ TA ≤ +125°C1 17 mA
1
Full electrical specifications to −55°C, but these package types are guaranteed for operation from −40°C to +125°C only. Package reliability below −40°C is not guaranteed.
2
Guaranteed by design.
= −5 V, TA = 25°C, unless otherwise noted.
−ANA
Δt
+ANA
DIG
−ANA
1
1
100 mV step with 20 mV overdrive 0.5 2.0 ns
P
+ANA
and V
≤ 5.5 V 50 70 dB
+DIG
10 mV
±9 μA
10.8 14.0 mA
1
17 mA
VO = 0 V, RL = ∞ 3.6 4.4 mA
−8.2 +14.0 mA
Rev. B | Page 4 of 12
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