ANALOG DEVICES AD 8532 ARZ Datasheet

Low Cost, 250 mA Output,

O

O

FEATURES

Single-supply operation: 2.7 V to 6 V
High output current: ±250 mA
Low supply current: 750 μA/amplifier
Wide bandwidth: 3 MHz
Slew rate: 5 V/μs
No phase reversal
Low input currents
Unity gain stable
Rail-to-rail input and output

APPLICATIONS

Multimedia audio
LCD drivers
ASIC input or output amplifiers
Headphone drivers

GENERAL DESCRIPTION

The AD8531, AD8532, and AD8534 are single, dual, and quad
rail-to-rail input/output single-supply amplifiers featuring
250 mA output drive current. This high output current makes
these amplifiers excellent for driving either resistive or capacitive
loads. AC performance is very good with 3 MHz bandwidth,
5 V/μs slew rate, and low distortion. All are guaranteed to operate
from a 3 V single supply as well as a 5 V supply.

The very low input bias currents enable the AD853x to be used for
integrators, diode amplification, and other applications requiring
low input bias current. Supply current is only 750 μA per
amplifier at 5 V, allowing low current applications to control
high current loads.

Applications include audio amplification for computers, sound
ports, sound cards, and set-top boxes. The AD853x family is
very stable, and it is capable of driving heavy capacitive loads
such as those found in LCDs.

The ability to swing rail-to-rail at the inputs and outputs enables
designers to buffer CMOS DACs, ASICs, or other wide output
swing devices in single-supply systems.

The AD8531/AD8532/AD8534 are specified over the extended
industrial temperature range (−40°C to +85°C). The AD8531 is
available in 8-lead SOIC, 5-lead SC70, and 5-lead SOT-23 packages.
The AD8532 is available in 8-lead SOIC, 8-lead MSOP, and 8-lead
TSSOP surface-mount packages. The AD8534 is available in
narrow 14-lead SOIC and 14-lead TSSOP surface-mount
packages.

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

Single-Supply Amplifiers

AD8531/AD8532/AD8534

PIN CONFIGURATIONS

AD8531

1

OUT A

V–

2

3

+IN A

Figure 1. 5-Lead SC70 and 5-Lead SOT-23

(KS and RJ Suffixes)

NC 1

–IN A 2

+IN A

AD8531

3

V– 4

NC = NO CONNECT

Figure 2. 8-Lead SOIC

(R Suffix)

1

OUT A

2

–IN A

3

+IN A

4

V–

AD8532

Figure 3. 8-Lead SOIC, 8-Lead TSSOP, and 8-Lead MSOP

(R, RU, and RM Suffixes)

1

UT A

2

–IN A

3

+IN A

4

V+

+IN B

–IN B

UT B

AD8534

5

6

7

Figure 4. 14-Lead SOIC and 14-Lead TSSOP

(R and RU Suffixes)

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©1996–2008 Analog Devices, Inc. All rights reserved.

6

5

4

NC8

V+7

OUT A

NC5

8

7

6

5

14

13

12

11

10

9

8

V+

–IN A

V+

OUT B

–IN B

+IN B

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

01099-001

01099-002

01099-003

01099-004

AD8531/AD8532/AD8534

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Pin Configurations ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Typical Performance Characteristics ............................................. 6

Theory of Operation ...................................................................... 11

Short-Circuit Protection............................................................ 11

Power Dissipation....................................................................... 11

Power Calculations for Varying or Unknown Loads............. 12

Calculating Power by Measuring Ambient and Case

Te mp e r at u re ................................................................................ 12

Calculating Power by Measuring Supply Current ................. 12

Input Overvoltage Protection................................................... 12

Output Phase Reversal............................................................... 13

Capacitive Load Drive ............................................................... 13

Applications Information.............................................................. 14

High Output Current, Buffered Reference/Regulator........... 14

Single-Supply, Balanced Line Driver ....................................... 14

Single-Supply Headphone Amplifier....................................... 15

Single-Supply, 2-Way Loudspeaker Crossover Network....... 15

Direct Access Arrangement for Telephone Line Interface ... 16

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 20

REVISION HISTORY

1/08—Rev. E to Rev. F

Changes to Layout............................................................................ 5

Changes to Figure 12 and Figure 13............................................... 7

Changes to Figure 38...................................................................... 11

Changes to Input Overvoltage Protection Section..................... 12

Changes to Figure 43...................................................................... 14

Updated Outline Dimensions....................................................... 17

Changes to Ordering Guide.......................................................... 20

4/05—Rev. D to Rev. E

Updated Format..................................................................Universal

Changes to Pin Configurations....................................................... 1

Changes to Table 4............................................................................ 5

Updated Outline Dimensions....................................................... 18

Changes to Ordering Guide.......................................................... 19

10/02—Rev. C to Rev. D

Deleted 8-Lead PDIP (N-8) .............................................. Universal

Deleted 14-Lead PDIP (N-14) ..........................................Universal

Edits to Figure 34...............................................................................9

Updated Outline Dimensions........................................................15

8/96—Revision 0: Initial Version

Rev. F | Page 2 of 20

AD8531/AD8532/AD8534

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VS = 3.0 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V

OS

−40°C ≤ TA ≤ +85°C 30 mV
Input Bias Current I

B

−40°C ≤ TA ≤ +85°C 60 pA
Input Offset Current I

OS

−40°C ≤ TA ≤ +85°C 30 pA
Input Voltage Range 0 3 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 3 V 38 45 dB
Large Signal Voltage Gain A

VO

Offset Voltage Drift ΔVOS/ΔT 20 μV/°C
Bias Current Drift ΔIB/ΔT 50 fA/°C
Offset Current Drift ΔIOS/ΔT 20 fA/°C

OUTPUT CHARACTERISTICS

Output Voltage High V

OH

−40°C ≤ TA ≤ +85°C 2.8 V
Output Voltage Low V

OL

−40°C ≤ TA ≤ +85°C 125 mV
Output Current I
Closed-Loop Output Impedance Z

OUT

OUT

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 3 V to 6 V 45 55 dB
Supply Current/Amplifier I

SY

−40°C ≤ TA ≤ +85°C 1.25 mA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 2 kΩ 3.5 V/μs
Settling Time t

S

Gain Bandwidth Product GBP 2.2 MHz
Phase Margin фo 70 Degrees
Channel Separation CS f = 1 kHz, RL = 2 kΩ 65 dB

NOISE PERFORMANCE

Voltage Noise Density e

n

f = 10 kHz 30 nV/√Hz
Current Noise Density i

n

25 mV

5 50 pA

1 25 pA

RL = 2 kΩ, VO = 0.5 V to 2.5 V 25 V/mV

IL = 10 mA 2.85 2.92 V

IL = 10 mA 60 100 mV

±250 mA
f = 1 MHz, AV = 1 60 Ω

VO = 0 V 0.70 1 mA

To 0.01% 1.6 μs

f = 1 kHz 45 nV/√Hz

f = 1 kHz 0.05 pA/√Hz

Rev. F | Page 3 of 20

AD8531/AD8532/AD8534

VS = 5.0 V, VCM = 2.5 V, TA = 25°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V

OS

−40°C ≤ TA ≤ +85°C 30 mV

Input Bias Current I

B

−40°C ≤ TA ≤ +85°C 60 pA

Input Offset Current I

OS

−40°C ≤ TA ≤ +85°C 30 pA

Input Voltage Range 0 5 V

Common-Mode Rejection Ratio CMRR VCM = 0 V to 5 V 38 47 dB

Large Signal Voltage Gain A

VO

Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +85°C 20 μV/°C

Bias Current Drift ΔIB/ΔT 50 fA/°C

Offset Current Drift ΔIOS/ΔT 20 fA/°C
OUTPUT CHARACTERISTICS

Output Voltage High V

OH

−40°C ≤ TA ≤ +85°C 4.85 V

Output Voltage Low V

OL

−40°C ≤ TA ≤ +85°C 125 mV

Output Current I

Closed-Loop Output Impedance Z

OUT

OUT

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 3 V to 6 V 45 55 dB

Supply Current/Amplifier I

SY

−40°C ≤ TA ≤ +85°C 1.75 mA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 2 kΩ 5 V/μs

Full-Power Bandwidth BW

Settling Time t

p

S

Gain Bandwidth Product GBP 3 MHz

Phase Margin фo 70 Degrees

Channel Separation CS f = 1 kHz, RL = 2 kΩ 65 dB
NOISE PERFORMANCE

Voltage Noise Density e

n

f = 10 kHz 30 nV/√Hz

Current Noise Density i

n

25 mV

5 50 pA

1 25 pA

RL = 2 kΩ, VO = 0.5 V to 4.5 V 15 80 V/mV

IL = 10 mA 4.9 4.94 V

IL = 10 mA 50 100 mV

±250 mA
f = 1 MHz, AV = 1 40 Ω

VO = 0 V 0.75 1.25 mA

1% distortion 350 kHz
To 0.01% 1.4 μs

f = 1 kHz 45 nV/√Hz

f = 1 kHz 0.05 pA/√Hz

Rev. F | Page 4 of 20

AD8531/AD8532/AD8534

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage (VS) 7 V
Input Voltage GND to V
Differential Input Voltage

1

±6 V

S

Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C

1

For supplies less than 6 V, the differential input voltage is equal to ±VS.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; the functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

2.5
–V

OL

2.0

1.5

OUT

±V

1.0

0.5

0

0 20 40 60 80 100 120 140 160 180 200

Figure 5. Output Voltage vs. Load, V

ESD CAUTION

+V

OH

R

LOAD

R

Is Connected to GND (0 V)

LOAD

(Ω)

= ±2.5 V,

S

01099-005

Table 4.

Package Type θ

JA

θ

JC

Unit

5-Lead SC70 (KS) 376 126 °C/W
5-Lead SOT-23 (RJ) 230 146 °C/W
8-Lead SOIC (R) 158 43 °C/W
8-Lead MSOP (RM) 210 45 °C/W
8-Lead TSSOP (RU) 240 43 °C/W
14-Lead SOIC (R) 120 36 °C/W
14-Lead TSSOP (RU) 240 43 °C/W

Rev. F | Page 5 of 20

AD8531/AD8532/AD8534

TYPICAL PERFORMANCE CHARACTERISTICS

VS= 2.7V

= 1.35V

V

CM

= 25°C

T

500

400

300

200

QUANTITY ( Amplifi ers)

100

–12 –10 –8 –6 –4 –2 0 2 4

INPUT OFFSET VOLTAGE (mV)

A

INPUT BIAS CURRENT (pA)

01099-006

Figure 6. Input Offset Voltage Distribution

VS= 5V

= 2.5V

V

CM

= 25°C

T

500

400

300

200

QUANTITY ( Amplifi ers)

100

A

INPUT BIAS CURRENT (pA)

VS= 5V, 3V
V

= VS/2

CM

8

7

6

5

4

3

2

–35 –15 5 25 45 65 85

TEMPERATURE (°C)

Figure 9. Input Bias Current vs. Temperature

VS= 5V

T

= 25°C

A

8

7

6

5

4

3

2

01099-009

–12 –10 –8 –6 –4 –2 0 2 4

INPUT OFFSET VOLTAGE (mV)

Figure 7. Input Offset Voltage Distribution

–2

–3

–4

–5

–6

–7

INPUT OFFSET VOLTAGE (mV)

–8

–35 –15 5 25 45 65 85

TEMPERATURE (°C)

Figure 8. Input Offset Voltage vs. Temperature

VS= 5V
V

= 2.5V

CM

01099-007

01 2 34 5

COMMON-MODE VOLTAGE (V)

01099-010

Figure 10. Input Bias Current vs. Common-Mode Voltage

6

VS= 5V, 3V

= VS/2

V

CM

5

4

3

2

1

0

INPUT OFFSET CURRENT (pA)

–1

01099-008

–2

–35 –15 5 25 45 65 85

TEMPERATURE (°C)

01099-011

Figure 11. Input Offset Current vs. Temperature

Rev. F | Page 6 of 20

AD8531/AD8532/AD8534

1000

VS= 2.7V

= 25°C

T

A

VS= 5V

= NO LOAD

R

L

= 25°C

T

A

100

10

1

ΔOUTPUT VOLTAGE (mV)

0.1

0.01

0.001 0.01 0.1 1 10 100
LOAD CURRENT (mA)

SOURCE

SINK

Figure 12. Output Voltage to Supply Rail vs. Load Current

1000

VS= 5V

= 25°C

T

A

100

10

1

ΔOUTPUT VOLTAGE (mV)

0.1

SOURCE

SINK

80

60

40

GAIN (dB)

20

0

01099-012

1k 10k 100k 1M 10M 100M

FREQUENCY ( Hz)

45

90

135

180

PHASE SHIFT (Degrees)

01099-015

Figure 15. Open-Loop Gain and Phase Shift vs. Frequency

5

VS= 2.7V

= 25°C

T

A

= 2kΩ

R

L

= 2.5V p-p

V

4

IN

3

2

OUTPUT SWING (V p-p)

1

0.01

0.001 0.01 0.1 1 10 100
LOAD CURRENT (mA)

Figure 13. Output Voltage to Supply Rail vs. Load Current

VS= 2.7V

= NO LOAD

R

L

= 25°C

T

A

80

60

40

GAIN (dB)

20

0

1k 10k 100k 1M 10M 100M

FREQUENCY ( Hz)

Figure 14. Open-Loop Gain and Phase Shift vs. Frequency

45

90

135

180

01099-013

0

1k 10k 100k 1M 10M

FREQUENCY ( Hz)

01099-016

Figure 16. Closed-Loop Output Swing vs. Frequency

5

4

3

2

PHASE SHIFT (Degrees)

01099-014

OUTPUT SWING (V p-p)

1

0

1k 10k 100k 1M 10M

FREQUENCY ( Hz)

VS= 5V

= 25°C

T

A

= 2kΩ

R

L

= 4.9V p-p

V

IN

01099-017

Figure 17. Closed-Loop Output Swing vs. Frequency

Rev. F | Page 7 of 20

AD8531/AD8532/AD8534

(

200

VS= 5V

= 25°C

T

180

A

160

140

Ω)

120

100

80

IMPEDANCE

60

40

20

0

1k 10k 100k 1M 10M 100M

AV= 10

AV= 1

LOAD CURRENT (mA)

Figure 18. Closed-Loop Output Impedance vs. Frequency

VS = 5V

= 1000

A

100

90

V

T

= 25°C

A

FREQUENCY = 1kHz

01099-018

1

VS= 5V

= 25°C

T

A

0.1

CURRENT NOISE DENSITY ( pA/√Hz)

0.01
10 100 1k 10k 100k

FREQUENCY ( Hz)

Figure 21. Current Noise Density vs. Frequency

110

VS= 5V
T

= 25°C

A

100

90

80

01099-021

100µV/DIV

10

0%

MARKER 41µV/√Hz

Figure 19. Voltage Noise Density vs. Frequency (1 kHz)

VS = 5V

= 1000

A

100

90

200µV/DIV

10

0%

MARKER 25.9µV/√Hz

V

T

= 25°C

A

FREQUENCY = 10kHz

Figure 20. Voltage Noise Density vs. Frequency (10 kHz)

70

60

COMMON-MO DE REJECTI ON (dB)

50

01099-019

40

1k 10k 100k 1M 10M

FREQUENCY ( Hz)

01099-022

Figure 22. Common-Mode Rejection vs. Frequency

140

V

= 2.7V

S

T

= 25°C

120

A

100

80

60

40

20

0

–20

POWER SUPPLY REJECTION (dB)

–40

01099-020

–60

100 1k 10k 100k 1M 10M

PSSR–

PSSR+

FREQUENCY ( Hz)

01099-023

Figure 23. Power Supply Rejection vs. Frequency

Rev. F | Page 8 of 20

AD8531/AD8532/AD8534

A

A

A

A

140

VS= 5V
T

= 25°C

120

A

100

80

60

40

20

0

–20

POWER SUPPLY REJECTION (dB)

–40

–60

100 1k 10k 100k 1M 10M

PSSR–

PSSR+

FREQUENCY ( Hz)

Figure 24. Power Supply Rejection vs. Frequency

50

VS= 2.7V

= 25°C

T

A

= 2kΩ

R

L

40

01099-024

50

VS= 5V

= 25°C

T

A

= 600Ω

R

L

40

30

L OVERSHOOT (%)

20

10

SMALL SIGN

0

10 100 1000 10000

–OS

CAPACITANCE (pF)

+OS

Figure 27. Small Signal Overshoot vs. Load Capacitance

50

VS= 2.7V

= 25°C

T

A

= 600Ω

R

L

40

01099-027

30

L OVERSHOOT (%)

20

10

SMALL SIGN

0

10 100 1000 10000

–OS

+OS

CAPACITANCE (pF)

Figure 25. Small Signal Overshoot vs. Load Capacitance

60

VS= 5V

= 25°C

T

A

= 2kΩ

R

L

50

40

–OS

30

L OVERSHOOT (%)

20

SMALL SIGN

10

0

10 100 1000 10000

CAPACITANCE (pF)

+OS

Figure 26. Small Signal Overshoot vs. Load Capacitance

30

L OVERSHOOT (%)

20

–OS

10

SMALL SIGN

+OS

01099-025

0

10 100 1000 10000

CAPACITANCE (pF)

01099-028

Figure 28. Small Signal Overshoot vs. Load Capacitance

0.90

0.85

0.80

0.75

0.70

0.65

0.60

SUPPLY CURRENT/AMPLI FIER (mA)

0.55

01099-026

0.50
–20–40 0 20 40 60 80

TEMPERATURE (°C)

VS= 5V

VS= 3V

01099-029

Figure 29. Supply Current per Amplifier vs. Temperature

Rev. F | Page 9 of 20

AD8531/AD8532/AD8534

V

V

0.8
TA= 25°C

0.7

0.6

0.5

0.4

0.3

0.2

SUPPLY CURRENT/AMPLIFI ER (mA)

0.1

0

0.75 1.501.00 2.00 2.50 3.00
SUPPLY VOLTAGE (±V)

Figure 30. Supply Current per Amplifier vs. Supply Voltage

VS= 1.35V
V
A
R
C
T

0V

20mV/DI

= 50mV

IN

= 1Ω

V

= 2kΩ

L

= 300pF

L

= 25°C

A

100

90

10

0%

01099-030

Figure 33. Large Signal Transient Response

100

90

VS = ±2.5V

= 1

A

V

= 2kΩ

R

L

= 25°C

T

A

500ns500mV

VS = ±1.35V

= 1

A

V

= 2kΩ

R

L

= 25°C

T

A

01099-033

10

0%

500 ns/DIV

Figure 31. Small Signal Transient Response

0V

20mV/DI

VS= 2.5V
V

IN

= 1Ω

A

V

= 2kΩ

R

L

= 300pF

C

L

= 25°C

T

A

500ns/DIV

Figure 32. Small Signal Transient Response

= 50mV

01099-031

500ns500mV

Figure 34. Large Signal Transient Response

1V

100

90

10

0%

1V

01099-032

10µs

Figure 35. No Phase Reversal

01099-034

01099-035

Rev. F | Page 10 of 20

AD8531/AD8532/AD8534

V

V

V

THEORY OF OPERATION

The AD8531/AD8532/AD8534 are all CMOS, high output
current drive, rail-to-rail input/output operational amplifiers.
Their high output current drive and stability with heavy capacitive
loads make the AD8531/AD8532/AD8534 excellent choices as
drive amplifiers for LCD panels.

Figure 36 illustrates a simplified equivalent circuit for the
AD8531/AD8532/AD8534. Like many rail-to-rail input amplifier
configurations, it comprises two differential pairs, one N-channel
(M1 to M2) and one P-channel (M3 to M4). These differential
pairs are biased by 50 μA current sources, each with a compliance
limit of approximately 0.5 V from either supply voltage rail. The
differential input voltage is then converted into a pair of
differential output currents. These differential output currents
are then combined in a compound folded-cascade second gain
stage (M5 to M9). The outputs of the second gain stage at M8
and M9 provide the gate voltage drive to the rail-to-rail output
stage. Additional signal current recombination for the output
stage is achieved using M11 to M14.

To achieve rail-to-rail output swings, the AD8531/AD8532/
AD8534 design employs a complementary, common source
output stage (M15 to M16). However, the output voltage swing
is directly dependent on the load current because the difference
between the output voltage and the supply is determined by
the AD8531/AD8532/AD8534’s output transistors on channel
resistance (see

Figure 12 and Figure 13). The output stage also
exhibits voltage gain by virtue of the use of common source
amplifiers; as a result, the voltage gain of the output stage (thus,
the open-loop gain of the device) exhibits a strong dependence
on the total load resistance at the output of the AD8531/
AD8532/AD8534.

+

IN–

IN+

M1

50µA

M3

50µA

100µA 100µA

V

B2

M4

M2

V

B3

M5

M8

M6

M9

M7 M10

V–

M12

20µA

20µA

M11

M15

OUT

M16

M14

M13

Figure 36. Simplified Equivalent Circuit

01099-036

SHORT-CIRCUIT PROTECTION

As a result of the design of the output stage for the maximum
load current capability, the AD8531/AD8532/AD8534 do not
have any internal short-circuit protection circuitry. Direct
connection of the output of the AD8531/AD8532/AD8534 to
the positive supply in single-supply applications destroys the
device. In applications where some protection is needed, but not
at the expense of reduced output voltage headroom, a low value
resistor in series with the output, as shown in

Figure 37, can be
used. The resistor, connected within the feedback loop of the
amplifier, has very little effect on the performance of the amplifier
other than limiting the maximum available output voltage
swing. For single 5 V supply applications, resistors less than
20 Ω are not recommended.

5

R

IN

AD8532

Figure 37. Output Short-Circuit Protection

20Ω

X

V

OUT

01099-037

POWER DISSIPATION

Although the AD8531/AD8532/AD8534 are capable of
providing load currents to 250 mA, the usable output load
current drive capability is limited to the maximum power
dissipation allowed by the device package used. In any
application, the absolute maximum junction temperature
for the AD8531/AD8532/AD8534 is 150°C. The maximum
junction temperature should never be exceeded because the
device could suffer premature failure. Accurately measuring
power dissipation of an integrated circuit is not always a
straightforward exercise; therefore,
as a design aid for either setting a safe output current drive
level or selecting a heat sink for the package options available
on the AD8531/AD8532/AD8534.

1.5

SOIC

θ

= 158°C/W

JA

1.0

MSOP

θ

= 210°C/W

JA

SC70

0.5

θ

= 376°C/W

JA

POWER DISSIPATI ON (W)

TSSOP

θ

= 240°C/W

JA

0

0 25 50 75 85 100

TEMPERATURE (°C)

Figure 38. Maximum Power Dissipation vs. Ambient Temperature

Figure 38 is provided

SOT-23

θ

= 230°C/W

JA

TJMAX = 150°C

FREE AIR

NO HEAT SINK

01099-038

Rev. F | Page 11 of 20

AD8531/AD8532/AD8534

The thermal resistance curves were determined using the
AD8531/AD8532/AD8534 thermal resistance data for each
package and a maximum junction temperature of 150°C. The
following formula can be used to calculate the internal junction
temperature of the AD8531/AD8532/AD8534 for any application:

= P

J

× θJA + T

DISS

A

T

where:

T

is the junction temperature.

J

P

is the power dissipation.

DISS

is the package thermal resistance, junction-to-case.

θ

JA

T

is the ambient temperature of the circuit.

A

To calculate the power dissipated by the AD8531/AD8532/
AD8534, the following equation can be used:

= I

P

DISS

× (VS − V

LOAD

OUT

)

where:

I

is the output load current.

LOAD

V

is the supply voltage.

S

is the output voltage.

V

OUT

The quantity within the parentheses is the maximum voltage
developed across either output transistor. As an additional
design aid in calculating available load current from the
AD8531/AD8532/AD8534,

Figure 5 illustrates the output
voltage of the AD8531/AD8532/AD8534 as a function of
load resistance.

POWER CALCULATIONS FOR VARYING OR UNKNOWN LOADS

Often, calculating power dissipated by an integrated circuit to
determine if the device is being operated in a safe range is not
as simple as it may seem. In many cases, power cannot be directly
measured, which may be the result of irregular output waveforms
or varying loads; indirect methods of measuring power are
required.

There are two methods to calculate power dissipated by an
integrated circuit. The first can be done by measuring the
package temperature and the board temperature, and the
other is to directly measure the supply current of the circuit.

CALCULATING POWER BY MEASURING AMBIENT AND CASE TEMPERATURE

Given the two equations for calculating junction temperature

T

= TA + P

J

where:

T

is the junction temperature.

J

T

is the ambient temperature.

A

is the junction to ambient thermal resistance.

θ

JA

DISS θJA

TJ = TC + P

DISS θJA

where:

T

is the case temperature.

C

and θJC are given in the data sheet.

θ

JA

The two equations can be solved for P (power)

T

+ P

A

P

= (TA − TC)/(θJC − θJA)

DISS

DISS θJA

= TC + Pθ

JC

Once power is determined, it is necessary to go back and calculate
the junction temperature to ensure that it has not been exceeded.

The temperature measurements should be directly on the package
and on a spot on the board that is near the package but not
touching it. Measuring the package could be difficult. A very
small bimetallic junction glued to the package can be used, or
measurement can be done using an infrared sensing device if
the spot size is small enough.

CALCULATING POWER BY MEASURING SUPPLY CURRENT

Power can be calculated directly, knowing the supply voltage
and current. However, supply current may have a dc component
with a pulse into a capacitive load, which can make rms current
very difficult to calculate. It can be overcome by lifting the supply
pin and inserting an rms current meter into the circuit. For this
to work, be sure the current is being delivered by the supply pin
being measured. This is usually a good method in a single-supply
system; however, if the system uses dual supplies, both supplies
may need to be monitored.

INPUT OVERVOLTAGE PROTECTION

As with any semiconductor device, whenever the condition
exists for the input to exceed either supply voltage, the input
overvoltage characteristic of the device must be considered.
When an overvoltage occurs, the amplifier can be damaged,
depending on the magnitude of the applied voltage and the
magnitude of the fault current. Although not shown here, when
the input voltage exceeds either supply by more than 0.6 V, pn
junctions internal to the AD8531/AD8532/AD8534 energize,
allowing current to flow from the input to the supplies. As
illustrated in the simplified equivalent input circuit (see
the AD8531/AD8532/AD8534 do not have any internal current
limiting resistors; therefore, fault currents can quickly rise to
damaging levels.

This input current is not inherently damaging to the device, as
long as it is limited to 5 mA or less. For the AD8531/AD8532/
AD8534, once the input voltage exceeds the supply by more than

0.6 V, the input current quickly exceeds 5 mA. If this condition
continues to exist, an external series resistor should be added.
The size of the resistor is calculated by dividing the maximum
overvoltage by 5 mA. For example, if the input voltage could
reach 10 V, the external resistor should be (10 V/5 mA) = 2 kΩ.

This resistance should be placed in series with either or both
inputs if they are exposed to an overvoltage condition.

Figure 36),

Rev. F | Page 12 of 20

AD8531/AD8532/AD8534

50mV

5V

AD8532

V

C

L

47nF

OUT

01099-040

R

S

5Ω

C

S

1µF

is determined; 10 μF is a

S

Figure 41. The top trace was

Tabl e 5

OUTPUT PHASE REVERSAL

Some operational amplifiers designed for single-supply operation
exhibit an output voltage phase reversal when their inputs are
driven beyond their useful common-mode range. The AD8531/
AD8532/AD8534 are free from reasonable input voltage range
restrictions, provided that input voltages no greater than the
supply voltage rails are applied. Although the output of the
device does not change phase, large currents can flow through
internal junctions to the supply rails, which was described in the
Input Overvoltage Protection section. Without limit, these fault
currents can easily destroy the amplifier. The technique
recommended in the

Input Overvoltage Protection section
should therefore be applied in those applications where the
possibility of input voltages exceeding the supply voltages exists.

CAPACITIVE LOAD DRIVE

The AD8531/AD8532/AD8534 exhibit excellent capacitive load
driving capabilities. They can drive up to 10 nF directly, as
shown in
the device is stable, a capacitive load does not come without a
penalty in bandwidth. As shown in
reduced to less than 1 MHz for loads greater than 10 nF. A snubber
network on the output does not increase the bandwidth, but it
does significantly reduce the amount of overshoot for a given
capacitive load. A snubber consists of a series RC network (R
C

S

device to ground. This network operates in parallel with the
load capacitor, C
actual value of the resistor and capacitor is best determined
empirically.

Figure 25 through Figure 28. However, even though

Figure 39, the bandwidth is

), as shown in Figure 40, connected from the output of the

, to provide phase lag compensation. The

L

4.0

3.5

3.0

VS= ±2.5V

= 1kΩ

R

L

= 25°C

T

A

,

S

V

IN

100mV p-p

Figure 40. Snubber Network Compensates for Capacitive Loads

The first step is to determine the value of the resistor, RS. A good
starting value is 100 Ω. This value is reduced until the small signal
transient response is optimized. Next, C
good starting point. This value is reduced to the smallest value
for acceptable performance (typically, 1 μF). For the case of a
47 nF load capacitor on the AD8531/AD8532/AD8534, the
optimal snubber network is 5 Ω in series with 1 μF. The benefit
is immediately apparent, as seen in
taken with a 47 nF load, and the bottom trace was taken with
the 5 Ω in series with a 1 μF snubber network in place. The
amount of overshoot and ringing is dramatically reduced.
illustrates a few sample snubber networks for large load
capacitors.

Table 5. Snubber Networks for Large Capacitive Loads

Load Capacitance (CL) Snubber Network (RS, CS)

0.47 nF 300 Ω, 0.1 μF

4.7 nF 30 Ω, 1 μF
47 nF 5 Ω, 1 μF

ONLY

100

90

47nF LO AD

2.5

2.0

1.5

BANDWIDITH ( MHz)

1.0

0.5

0

0.01 0.1 1 10 100
CAPACITIVE LOAD ( nF)

SNUBBER

IN CIRCUIT

01099-039

10

0%

10µs50mV

Figure 41. Overshoot and Ringing Are Reduced by Adding a Snubber

Network in Parallel with the 47 nF Load

01099-041

Figure 39. Unity-Gain Bandwidth vs. Capacitive Load

Rev. F | Page 13 of 20

AD8531/AD8532/AD8534

V

V

APPLICATIONS INFORMATION

HIGH OUTPUT CURRENT, BUFFERED REFERENCE/REGULATOR

Many applications require stable voltage outputs relatively close
in potential to an unregulated input source. This low dropout
type of reference/regulator is readily implemented with a rail­to-rail output op amp and is particularly useful when using a
higher current device, such as the AD8531/AD8532/AD8534.
A typical example is the 3.3 V or 4.5 V reference voltage developed
from a 5 V system source. Generating these voltages requires a
three terminal reference, such as the

REF194 (4.5 V), both of which feature low power, with sourcing

outputs of 30 mA or less.

Figure 42 shows how such a reference
can be outfitted with an AD8531/AD8532/AD8534 buffer for
higher currents and/or voltage levels, plus sink and source load
capability.

S

5V

C1

0.1µF

C3

0.1µF

V

C

ON/OFF
CONTROL
INPUT CMOS HI
(OR OPEN) = ON

LO = OFF

V

S

COMMON

3

2

U1

REF196

4

6

V

OUT2

3.3V

=

Figure 42. High Output Current Reference/Regulator

The low dropout performance of this circuit is provided by
stage U2, an AD8531 connected as a follower/buffer for the
basic reference voltage produced by U1. The low voltage
saturation characteristic of the AD8531/AD8532/AD8534
allows up to 100 mA of load current in the illustrated use,
as a 5 V to 3.3 V converter with good dc accuracy. In fact,
the dc output voltage change for a 100 mA load current delta
measures less than 1 mV. This corresponds to an equivalent
output impedance of < 0.01 Ω. In this application, the stable

3.3 V from U1 is applied to U2 through a noise filter, R1 to C1.
U2 replicates the U1 voltage within a few millivolts, but at a
higher current output at V

OUT1

source output current(s), unlike most IC references. R2 and C2
in the feedback path of U2 provide additional noise filtering.

Transient performance of the reference/regulator for a 100 mA
step change in load current is also quite good and is largely
determined by the R5 to C5 output network. With values as
shown, the transient is about 20 mV peak and settles to within
2 mV in less than 10 μs for either polarity. Although room exists

REF196 (3.3 V) or the

U2

R1
10kΩ
1%

(See Text)

C4
1µF

R3

R4

3.3kΩ

AD8531

R2

10kΩ 1%

C2

0.1µF

V

=

OUT1

3.3V @ 100mA

C5
100µF/ 16V
TAN TALU M

R5

0.2Ω

V

OUT

COMMON

, with the ability to both sink and

01099-042

for optimizing the transient response, any changes to the R5 to
C5 network should be verified by experiment to preclude the
possibility of excessive ringing with some capacitor types.

To s c al e V
resistor R3 (shown dotted in
new V

to another (higher) output level, the optional

OUT2

Figure 42) is added, causing the

to become

OUT1

R2

VV

⎛
⎜

OUT2OUT1

⎝

⎞

+×=

1

⎟

R3

⎠

The circuit can either be used as shown, as a 5 V to 3.3 V
reference/regulator, or with on/off control. By driving Pin 3 of
U1 with a logic control signal as noted, the output is switched
on/off. Note that when on/off control is used, R4 must be used
with U1 to speed on/off switching.

SINGLE-SUPPLY, BALANCED LINE DRIVER

The circuit in Figure 43 is a unique line driver circuit topology
used in professional audio applications. It was modified for
automotive and multimedia audio applications. On a single 5 V
supply, the line driver exhibits less than 0.7% distortion into a
600 Ω load from 20 Hz to 15 kHz (not shown) with an input
signal level of 4 V p-p. In fact, the output drive capability of the
AD8531/AD8532/AD8534 maintains this level for loads as
small as 32 Ω. For input signals less than 1 V p-p, the THD is
less than 0.1%, regardless of load. The design is a transformer­less, balanced transmission system where output common­mode rejection of noise is of paramount importance. As with
the transformer-based system, either output can be shorted
to ground for unbalanced line driver applications without changing
the circuit gain of 1. Other circuit gains can be set according to the
equation in the diagram. This allows the design to be easily
configured for inverting, noninverting, or differential operation.

R3

5V

2

C1

22µF

IN

A1, A2 = 1/2 AD8532

GAIN =

SET: R7, R10, R11 = R2

SET: R6, R12, R13 = R3

A1

3

R3
R2

10kΩ

R1

10kΩ

10kΩ

1

R10

10kΩ

2

1

A2

3

R2

R7
10kΩ

12V

7

A1

R11

R12

10kΩ

10kΩ

6

7

A2

5

R13

10kΩ

R6

10kΩ

6

5

100kΩ

R5

50Ω

5V

R8
100kΩ

C2

R9

1µF

R14
50Ω

Figure 43. Single-Supply, Balanced Line Driver for Multimedia and

Automotive Applications

C3

47µF

600Ω

C4

47µF

V

OUT1

R

L

V

OUT2

01099-043

Rev. F | Page 14 of 20

AD8531/AD8532/AD8534

V

SINGLE-SUPPLY HEADPHONE AMPLIFIER

Because of its speed and large output drive, the AD8531/
AD8532/AD8534 make an excellent headphone driver, as
illustrated in

Figure 44. Its low supply operation and rail-to-rail
inputs and outputs give a maximum signal swing on a single
5 V supply. To ensure maximum signal swing available to drive
the headphone, the amplifier inputs are biased to V+/2, which
in this case is 2.5 V. The 100 kΩ resistor to the positive supply
is equally split into two 50 kΩ resistors, with their common
point bypassed by 10 μF to prevent power supply noise from
contaminating the audio signal.

The audio signal is then ac-coupled to each input through a
10 μF capacitor. A large value is needed to ensure that the 20 Hz
audio information is not blocked. If the input already has the
proper dc bias, the ac coupling and biasing resistors are not
required. A 270 μF capacitor is used at the output to couple the
amplifier to the headphone. This value is much larger than that
used for the input because of the low impedance of the head­phones, which can range from 32 Ω to 600 Ω. An additional 16 Ω
resistor is used in series with the output capacitor to protect the
output stage of the op amp by limiting the capacitor discharge
current. When driving a 48 Ω load, the circuit exhibits less
than 0.3% THD+N at output drive levels of 4 V p-p.

5V

V5V

1µF/0.1µF

16Ω

16Ω

270µF

270µF

50kΩ

50kΩ

LEFT
HEADPHONE

RIGHT
HEADPHONE

01099-044

LEFT

INPUT

RIGHT

INPUT

50kΩ

50kΩ

10µF

50kΩ

10µF

10µF

100kΩ

V

50kΩ

10µF

100kΩ

1/2

AD8532

1/2

AD8532

Figure 44. Single-Supply, Stereo Headphone Driver

SINGLE-SUPPLY, 2-WAY LOUDSPEAKER CROSSOVER NETWORK

Active filters are useful in loudspeaker crossover networks
because of small size, relative freedom from parasitic effects, the
ease of controlling low/high channel drive, and the controlled
driver damping provided by a dedicated amplifier. Both Sallen­Key (SK) and multiple-feedback (MFB) filter architectures are
useful in implementing active crossover networks. The circuit
shown in
that combines the advantages of both filter topologies.

Figure 45 is a single-supply, 2-way active crossover

This active crossover exhibits less than 0.4% THD+N at output
levels of 1.4 V rms using general-purpose, unity-gain HP/LP stages.

In this 2-way example, the LO signal is a dc-to-500 Hz LP woofer
output, and the HI signal is the HP (>500 Hz) tweeter output.
U1B forms an LP section at 500 Hz, while U1A provides an HP
section, covering frequencies ≥500 Hz.

+

270µF

+

500Hz

AND UP

100kΩ

DC –
500Hz

100kΩ

HI

LO

V

IN

TO U1

R

100kΩ

V

S

C1

0.01µF

IN

C

10µF

0.1µ F

IN

100kΩ

100kΩ

R2

31.6kΩ

R5

31.6kΩ

V

S

100µF/25V

C2

0.01µF

15.8kΩ

C4

0.02µF

10µF

31.6kΩ

31.6kΩ

R7

5V

COM

R1

V

S

U1A

AD8532

3

1

2

4

R6

C3

0.01µF

6

7

5

U1B

AD8532

Figure 45. A Single-Supply, 2-Way Active Crossover

R3

49.9Ω

R4

49.9Ω

270µF

The crossover example frequency of 500 Hz can be shifted
lower or higher by frequency scaling of either resistors or
capacitors. In configuring the circuit for other frequencies,
complementary LP/HP action must be maintained between
sections, and component values within the sections must be in
the same ratio.

Tabl e 6 provides a design aid to adaptation, with

suggested standard component values for other frequencies.

For additional information on the active filters and active crossover
networks, refer to the data sheet for the

OP279, a dual rail-to-

rail, high output current, operational amplifier.

Table 6. RC Component Selection for Various Crossover
Frequencies

Crossover Frequency (Hz) R1/C1 (U1A)2, R5/C3 (U1B)

1

3

100 160 kΩ/0.01 μF
200 80.6 kΩ/0.01 μF
319 49.9 kΩ/0.01 μF
500 31.6 kΩ/0.01 μF
1 k 16 kΩ/0.01 μF
2 k 8.06 kΩ/0.01 μF
5 k 3.16 kΩ/0.01 μF
10 k 1.6 kΩ/0.01 μF

1

Applicable for Filter A = 2.

2

For Sallen-Key stage U1A: R1 = R2, and C1 = C2, and so on.

3

For multiple feedback stage U1B: R6 = R5, R7 = R5/2, and C4 = 2C3.

01099-045

Rev. F | Page 15 of 20

AD8531/AD8532/AD8534

T

DIRECT ACCESS ARRANGEMENT FOR TELEPHONE LINE INTERFACE

Figure 46 illustrates a 5 V only transmit/receive telephone line
interface for 600 Ω transmission systems. It allows full duplex
transmission of signals on a transformer-coupled 600 Ω line in
a differential manner. A1 provides gain that can be adjusted to
meet the modem output drive requirements. Both A1 and A2
are configured to apply the largest possible signal on a single
supply to the transformer. Because of the high output current
drive and low dropout voltage of the AD8531/AD8532/AD8534,
the largest signal available on a single 5 V supply is approximately

4.5 V p-p into a 600 Ω transmission system. A3 is configured as
a difference amplifier for two reasons: it prevents the transmit
signal from interfering with the receive signal, and it extracts
the receive signal from the transmission line for amplification
by A4. The gain of A4 can be adjusted in the same manner as
that of A1 to meet the input signal requirements of the modem.
Standard resistor values permit the use of single in-line package
(SIP) format resistor arrays.

P1
Tx GAIN
ADJUST

OTELEPHONE

LINE

1:1

Z

O

600Ω

T1
MIDCOM
671-8005

A1, A2 = 1/2 AD8532
A3, A4 = 1/2 AD8532

6.2V

6.2V

R11

10kΩ

360Ω

R9

10kΩ

R12

10kΩ

R3

R5

10kΩ

R6

10kΩ

R10

10kΩ

2

A3

3

Figure 46. Single-Supply Direct Access Arrangement for Modems

2kΩ

1

7

1

9.09kΩ

A1

A2

R13

10kΩ

R2

2

3

6

5

R14

14.3kΩ

6

5

R1

10kΩ

A4

C1

0.1µF

10µF

P2
Rx GAIN
ADJUST

2kΩ

7

5V DC

0.1µF

TRANSMIT

R7
10kΩ

R8
10kΩ

RECEIVE

C2

TxA

RxA

01099-046

Rev. F | Page 16 of 20

AD8531/AD8532/AD8534

OUTLINE DIMENSIONS

2.20

2.00

1.80

1.35

1.25

1.15

PIN 1

1.00

0.90

0.70

0

.

1

0

M

X

A

0.10 COPLANARITY

123

0.30

0.15

COMPLIANT TO JEDEC STANDARDS MO-203-AA

45

0.65 BSC

2.40

2.10

1.80

1.10

0.80

SEATING
PLANE

0.40

0.10

0.22

0.08

Figure 47. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]

(KS-5)

Dimensions shown in millimeters

2.90 BSC

1.60 BSC

1.30

1.15

0.90

0.15 MAX

5

123

PIN 1

COMPLIANT TO JEDEC STANDARDS MO-178-A A

1.90

BSC

0.50

0.30

4

0.95 BSC

2.80 BSC

1.45 MAX

SEATING
PLANE

0.22

0.08

10°

5°
0°

Figure 48. 5-Lead Small Outline Transistor Package [SOT-23]

(RJ-5)

Dimensions shown in millimeters

5.00 (0.1968)

4.80 (0.1890)

0.46

0.36

0.26

0.60

0.45

0.30

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLL ING DIMENSI ONS ARE IN MILLIMETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DES IGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-A A

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

Figure 49. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

Rev. F | Page 17 of 20

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

AD8531/AD8532/AD8534

0.95

0.85

0.75

0.15

0.00

COPLANARITY

3.20

3.00

2.80

8

5

3.20

3.00

1

2.80

PIN 1

0.65 BSC

0.38

0.22

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

5.15

4.90

4.65

4

SEATING
PLANE

1.10 MAX

0.23

0.08

8°
0°

0.80

0.60

0.40

Figure 50. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

3.10

3.00

2.90

8

5

4.50

6.40 BSC

4.40

4.30

41

PIN 1

0.65 BSC

0.15

0.05

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AA

0.30

0.19

1.20
MAX

SEATING
PLANE

0.20

0.09

8°
0°

0.75

0.60

0.45

Figure 51. 8-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-8)

Dimensions shown in millimeters

5.10

5.00

4.90

1.05

1.00

0.80

4.50

4.40

4.30

PIN 1

14

0.65
BSC

0.15

0.05

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

0.30

0.19

8

6.40
BSC

71

1.20
MAX

SEATING
PLANE

0.20

0.09

COPLANARITY

0.10

8°
0°

0.75

0.60

0.45

Figure 52. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

Rev. F | Page 18 of 20

AD8531/AD8532/AD8534

8.75 (0.3445)

8.55 (0.3366)

BSC

8

7

6.20 (0.2441)

5.80 (0.2283)

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0197)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

45°

060606-A

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARIT Y

0.10

CONTROLL ING DIMENSIONS ARE IN MILLI METERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-O FF MIL LIMETE R EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

14

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-012-AB

Figure 53. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-14)

Dimensions shown in millimeters and (inches)

Rev. F | Page 19 of 20

AD8531/AD8532/AD8534

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8531AKS-R2 −40°C to +85°C 5-Lead SC70 KS-5 A7B
AD8531AKS-REEL7 −40°C to +85°C 5-Lead SC70 KS-5 A7B
AD8531AKSZ-R2
AD8531AKSZ-REEL7
AD8531ART-REEL −40°C to +85°C 5-Lead SOT-23 RJ-5 A7A
AD8531ART-REEL7 −40°C to +85°C 5-Lead SOT-23 RJ-5 A7A
AD8531ARTZ-REEL
AD8531ARTZ-REEL7
AD8531AR −40°C to +85°C 8-Lead SOIC_N R-8
AD8531AR-REEL −40°C to +85°C 8-Lead SOIC_N R-8
AD8531ARZ
AD8531ARZ-REEL
AD8532AR −40°C to +85°C 8-Lead SOIC_N R-8
AD8532AR-REEL −40°C to +85°C 8-Lead SOIC_N R-8
AD8532AR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
AD8532ARZ
AD8532ARZ-REEL
AD8532ARZ-REEL7
AD8532ARM-R2 −40°C to +85°C 8-Lead MSOP RM-8 ARA
AD8532ARM-REEL −40°C to +85°C 8-Lead MSOP RM-8 ARA
AD8532ARMZ-R2
AD8532ARMZ-REEL
AD8532ARU −40°C to +85°C 8-Lead TSSOP RU-8
AD8532ARU-REEL −40°C to +85°C 8-Lead TSSOP RU-8
AD8532ARUZ
AD8532ARUZ-REEL
AD8534AR −40°C to +85°C 14-Lead SOIC_N R-14
AD8534AR-REEL −40°C to +85°C 14-Lead SOIC_N R-14
AD8534ARZ
AD8534ARZ-REEL
AD8534ARU −40°C to +85°C 14-Lead TSSOP RU-14
AD8534ARU-REEL −40°C to +85°C 14-Lead TSSOP RU-14
AD8534ARUZ
AD8534ARUZ-REEL

1

Z = RoHS Compliant Part.

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

−40°C to +85°C 5-Lead SC70 KS-5 A0Q

−40°C to +85°C 5-Lead SC70 KS-5 A0Q

−40°C to +85°C 5-Lead SOT-23 RJ-5 A0P

−40°C to +85°C 5-Lead SOT-23 RJ-5 A0P

−40°C to +85°C 8-Lead SOIC_N R-8

−40°C to +85°C 8-Lead SOIC_N R-8

−40°C to +85°C 8-Lead SOIC_N R-8

−40°C to +85°C 8-Lead SOIC_N R-8

−40°C to +85°C 8-Lead SOIC_N R-8

−40°C to +85°C 8-Lead MSOP RM-8 A0R

−40°C to +85°C 8-Lead MSOP RM-8 A0R

−40°C to +85°C 8-Lead TSSOP RU-8

−40°C to +85°C 8-Lead TSSOP RU-8

−40°C to +85°C 14-Lead SOIC_N R-14

−40°C to +85°C 14-Lead SOIC_N R-14

−40°C to +85°C 14-Lead TSSOP RU-14

−40°C to +85°C 14-Lead TSSOP RU-14

©1996–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01099-0-1/08(F)

Rev. F | Page 20 of 20

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Analog Devices Inc.:
AD8531AKSZ-R2 AD8534ARZ AD8531ARTZ-REEL7 AD8532ARZ-REEL7 AD8531ARZ-REEL AD8531ARTZ-

REEL AD8534ARUZ-REEL AD8531ARZ AD8534ARZ-REEL AD8532ARMZ-R2 AD8532ARZ-REEL AD8532ARUZ
AD8532ARZ AD8531AKSZ-REEL7 AD8534ARUZ AD8532ARMZ-REEL AD8532ARUZ-REEL AD8532AR-REEL
AD8532AR