ANALOG DEVICES AD 8510 ARMZ Datasheet

Precision, Very Low Noise, Low Input Bias Current,

FEATURES

Fast settling time: 500 ns to 0.1%
Low offset voltage: 400 μV maximum
Low T
Low input bias current: 25 pA typical at V
Dual-supply operation: ±5 V to ±15 V
Low noise: 8 nV/√Hz typical at f = 1 kHz
Low distortion: 0.0005%
No phase reversal
Unity gain stable

APPLICATIONS

Instrumentation
Multipole filters
Precision current measurement
Photodiode amplifiers
Sensors
Audio

: 1 μV/°C typical

CVOS

= ±15 V

S

Wide Bandwidth JFET Operational Amplifiers

AD8510/AD8512/AD8513

PIN CONFIGURATIONS

NULL

1

AD8510

–IN

2

TOP VIEW

+IN

3

(Not to Scale)

V–

45

NC = NO CONNECT

Figure 1. 8-Lead MSOP (RM Suffix) Figure 2. 8-Lead SOIC_N (R Suffix)

OUT A

1

–IN A

+IN A

AD8512

2

TOP VIEW

3

(Not to Scale)

V–

45

Figure 3. 8-Lead MSOP (RM Suffix) Figure 4. 8-Lead SOIC_N (R Suffix)

OUT A

1

–IN A

2

3

+IN A

+IN B

–IN B

OUT B

V+

AD8513

4

TOP VIEW

(Not to Scale)

5

6

7

Figure 5. 14-Lead SOIC_N (R Suffix) Figure 6. 14-Lead TSSOP (RU Suffix)

14

13

12

11

10

8

7

6

8

7

6

9

8

NC

V+

OUT

NULL

V+

OUT B

–IN B

+IN B

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

NULL

1

AD8510

–IN

2

TOP VIEW

+IN

3

(Not to Scale)

V–

45

02729-003

02729-001

02729-005

NC = NO CONNECT

OUT A

1

–IN A

+IN A

OUT A

–IN A

+IN A

+IN B

–IN B

OUT B

AD8512

2

TOP VIEW

3

(Not to Scale)

V–

45

1

2

3

AD8513

4

V+

TOP VIEW

(Not to Scale)

5

6

7

8

7

6

14

13

12

11

10

9

8

8

7

6

NC

V+

OUT

NULL

V+

OUT B

–IN B

+IN B

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

02729-004

02729-002

2729-006

GENERAL DESCRIPTION

The AD8510/AD8512/AD8513 are single-, dual-, and quad­precision JFET amplifiers that feature low offset voltage, input
bias current, input voltage noise, and input current noise.

The combination of low offsets, low noise, and very low input
bias currents makes these amplifiers especially suitable for high
impedance sensor amplification and precise current measurements
using shunts. The combination of dc precision, low noise, and
fast settling time results in superior accuracy in medical
instruments, electronic measurement, and automated test
equipment. Unlike many competitive amplifiers, the AD8510/
AD8512/AD8513 maintain their fast settling performance even
with substantial capacitive loads. Unlike many older JFET
amplifiers, the AD8510/AD8512/AD8513 do not suffer from
output phase reversal when input voltages exceed the maximum
common-mode voltage range.

Fast slew rate and great stability with capacitive loads make the
AD8510/AD8512/AD8513 a perfect fit for high performance
filters. Low input bias currents, low offset, and low noise result
in a wide dynamic range of photodiode amplifier circuits. Low
noise and distortion, high output current, and excellent speed
make the AD8510/AD8512/AD8513 great choices for audio
applications.

The AD8510/AD8512 are both available in 8-lead narrow SOIC_N
and 8-lead MSOP packages. MSOP-packaged parts are only
available in tape and reel. The AD8513 is available in 14-lead
SOIC_N and TSSOP packages.

The AD8510/AD8512/AD8513 are specified over the −40°C to
+125°C extended industrial temperature range.

Rev. I

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2002–2009 Analog Devices, Inc. All rights reserved.

AD8510/AD8512/AD8513

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Pin Configurations ........................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics ............................................................. 4

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Typical Performance Characteristics ............................................. 7

General Application Information ................................................. 13

Input Overvoltage Protection ................................................... 13

REVISION HISTORY

2/09—Rev. H to Rev. I

Changes to Figure 25 ...................................................................... 10

Changes to Ordering Guide .......................................................... 20

10/07—Rev. G to Rev. H

Changes to Crosstalk Section ........................................................ 18

Added Figure 58 .............................................................................. 18

6/07—Rev. F to Rev. G

Changes to Figure 1 and Figure 2 ................................................... 1

Changes to Table 1 and Table 2 ....................................................... 3

Updated Outline Dimensions ....................................................... 19

Changes to Ordering Guide .......................................................... 20

6/06—Rev. E to Rev. F

Changes to Figure 23 ........................................................................ 9

Updated Outline Dimensions ....................................................... 19

Changes to Ordering Guide .......................................................... 20

6/04—Rev. D to Rev. E

Changes to Format ............................................................. Universal

Changes to Specifications ................................................................ 3

Updated Outline Dimensions ....................................................... 19

10/03—Rev. C to Rev. D

Added AD8513 Model ....................................................... Universal

Changes to Specifications ................................................................ 3

Added Figure 36 through Figure 40 ............................................. 10

Added Figure 55 and Figure 57..................................................... 17

Changes to Ordering Guide .......................................................... 20

Output Phase Reversal ............................................................... 13

Total Harmonic Distortion (THD) + Noise .............................. 13

Total Noise Including Source Resistors ................................... 13

Settling Time ............................................................................... 14

Overload Recovery Time .......................................................... 14

Capacitive Load Drive ............................................................... 14

Open-Loop Gain and Phase Response .................................... 15

Precision Rectifiers ..................................................................... 16

I-V Conversion Applications .................................................... 17

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 20

9/03—Rev. B to Rev. C

Changes to Ordering Guide ............................................................ 4

Updated Figure 2 ............................................................................ 10

Changes to Input Overvoltage Protection Section .................... 10

Changes to Figure 10 and Figure 11............................................. 12

Changes to Photodiode Circuits Section .................................... 13

Changes to Figure 13 and Figure 14............................................. 13

Deleted Precision Current Monitoring Section ......................... 14

Updated Outline Dimensions ....................................................... 15

3/03—Rev. A to Rev. B

Updated Figure 5 ............................................................................ 11

Updated Outline Dimensions ....................................................... 15

8/02—Rev. 0 to Rev. A

Added AD8510 Model ....................................................... Universal

Added Pin Configurations ............................................................... 1

Changes to Specifications ................................................................. 2

Changes to Ordering Guide ............................................................. 4

Changes to TPC 2 and TPC 3 .......................................................... 5

Added TPC 10 and TPC 12 .............................................................. 6

Replaced TPC 20 ............................................................................... 8

Replaced TPC 27 ............................................................................... 9

Changes to General Application Information Section .............. 10

Changes to Figure 5 ........................................................................ 11

Changes to I-V Conversion Applications Section ..................... 13

Changes to Figure 13 and Figure 14............................................. 13

Changes to Figure 17 ...................................................................... 14

Rev. I | Page 2 of 20

AD8510/AD8512/AD8513

SPECIFICATIONS

@ VS = ±5 V, VCM = 0 V, TA = 25°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage (B Grade)

−40°C < TA < +125°C 0.8 mV
Offset Voltage (A Grade) VOS 0.1 0.9 mV

−40°C < TA < +125°C 1.8 mV
Input Bias Current IB 21 75 pA

−40°C < TA < +85°C 0.7 nA

−40°C < TA < +125°C 7.5 nA
Input Offset Current IOS 5 50 pA

−40°C < TA < +85°C 0.3 nA

−40°C < TA < +125°C 0.5 nA
Input Capacitance

Differential 12.5 pF

Common Mode 11.5 pF
Input Voltage Range −2.0 +2.5 V
Common-Mode Rejection Ratio CMRR VCM = −2.0 V to +2.5 V 86 100 dB
Large-Signal Voltage Gain AVO R
Offset Voltage Drift (B Grade)1 ΔVOS/ΔT 0.9 5 μV/°C
Offset Voltage Drift (A Grade) ΔVOS/ΔT 1.7 12 μV/°C

OUTPUT CHARACTERISTICS

Output Voltage High VOH RL = 10 kΩ 4.1 4.3 V
Output Voltage Low VOL RL = 10 kΩ, −40°C < TA < +125°C −4.9 −4.7 V
Output Voltage High VOH RL = 2 kΩ 3.9 4.2 V
Output Voltage Low VOL RL = 2 kΩ, −40°C < TA < +125°C −4.9 −4.5 V
Output Voltage High VOH RL = 600 Ω 3.7 4.1 V
Output Voltage Low VOL RL = 600 Ω, −40°C < TA < +125°C −4.8 −4.2 V
Output Current I

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V 86 130 dB
Supply Current/Amplifier I

AD8510/AD8512/AD8513 VO = 0 V 2.0 2.3 mA

AD8510/AD8512 −40°C < TA < +125°C 2.5 mA

AD8513 −40°C < TA < +125°C 2.75 mA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 2 kΩ 20 V/μs
Gain Bandwidth Product GBP 8 MHz
Settling Time tS To 0.1%, 0 V to 4 V step, G = +1 0.4 μs
Total Harmonic Distortion (THD) + Noise THD + N 1 kHz, G = +1, RL = 2 kΩ 0.0005 %
Phase Margin φ

NOISE PERFORMANCE

Voltage Noise Density en f = 10 Hz 34 nV/√Hz

f = 100 Hz 12 nV/√Hz
f = 1 kHz 8.0 10 nV/√Hz
f = 10 kHz 7.6 nV/√Hz

Peak-to-Peak Voltage Noise en p-p 0.1 Hz to 10 Hz bandwidth 2.4 5.2 μV p-p

1

AD8510/AD8512 only.

1

V

0.08 0.4 mV

OS

= 2 kΩ, VO = −3 V to +3 V 65 107 V/mV

L

±40 ±54 mA

OUT

SY

M

44.5 Degrees

Rev. I | Page 3 of 20

AD8510/AD8512/AD8513

ELECTRICAL CHARACTERISTICS

@ VS = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage (B Grade)1 VOS 0.08 0.4 mV

−40°C < TA < +125°C 0.8 mV

Offset Voltage (A Grade) VOS 0.1 1.0 mV

−40°C < TA < +125°C 1.8 mV
Input Bias Current IB 25 80 pA

−40°C < TA < +85°C 0.7 nA

−40°C < TA < +125°C 10 nA
Input Offset Current I

−40°C < TA < +85°C 0.3 nA

−40°C < TA < +125°C 0.5 nA
Input Capacitance

Differential 12.5 pF

Common Mode 11.5 pF
Input Voltage Range −13.5 +13.0 V
Common-Mode Rejection Ratio CMRR VCM = −12.5 V to +12.5 V 86 108 dB
Large-Signal Voltage Gain AVO

Offset Voltage Drift (B Grade)1 ΔVOS/ΔT 1.0 5 μV/°C
Offset Voltage Drift (A Grade) ΔVOS/ΔT 1.7 12 μV/°C

OUTPUT CHARACTERISTICS

Output Voltage High VOH RL = 10 kΩ +14.0 +14.2 V
Output Voltage Low VOL RL = 10 kΩ, −40°C < TA < +125°C −14.9 −14.6 V
Output Voltage High VOH RL = 2 kΩ +13.8 +14.1 V
Output Voltage Low VOL RL = 2 kΩ, −40°C < TA < +125°C –14.8 −14.5 V
Output Voltage High VOH RL = 600 Ω +13.5 +13.9 V

R

Output Voltage Low VOL RL = 600 Ω −14.3 −13.8 V

R

Output Current I

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V 86 dB
Supply Current/Amplifier ISY

AD8510/AD8512/AD8513 VO = 0 V 2.2 2.5 mA

AD8510/AD8512 −40°C < TA < +125°C 2.6 mA

AD8513 −40°C < TA < +125°C 3.0 mA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 2 kΩ 20 V/μs
Gain Bandwidth Product GBP 8 MHz
Settling Time tS To 0.1%, 0 V to 10 V step, G = +1 0.5 μs

To 0.01%, 0 V to 10 V step, G = +1 0.9 μs

Total Harmonic Distortion (THD) + Noise THD + N 1 kHz, G = +1, RL = 2 kΩ 0.0005 %
Phase Margin φM 52 Degrees

6 75 pA

OS

= 2 kΩ, VCM = 0 V,

R

L

V

= −13.5 V to +13.5 V

O

= 600 Ω, −40°C < TA < +125°C +11.4 V

L

= 600 Ω, −40°C < TA < +125°C −12.1 V

L

±70 mA

OUT

115 196 V/mV

Rev. I | Page 4 of 20

AD8510/AD8512/AD8513

Parameter Symbol Conditions Min Typ Max Unit

NOISE PERFORMANCE

Voltage Noise Density en f = 10 Hz 34 nV/√Hz
f = 100 Hz 12 nV/√Hz
f = 1 kHz 8.0 10 nV/√Hz
f = 10 kHz 7.6 nV/√Hz

Peak-to-Peak Voltage Noise en p-p 0.1 Hz to 10 Hz bandwidth 2.4 5.2 μV p-p

1

AD8510/AD8512 only.

Rev. I | Page 5 of 20

AD8510/AD8512/AD8513

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage ±18 V
Input Voltage ±VS
Output Short-Circuit Duration to GND Observe derating curves
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Electrostatic Discharge

(Human Body Model)

2000 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Table 4. Thermal Resistance

Package Type θ

8-Lead MSOP (RM) 210 45 °C/W
8-Lead SOIC_N (R) 158 43 °C/W
14-Lead SOIC_N (R) 120 36 °C/W
14-Lead TSSOP (RU) 180 35 °C/W

1

θJA is specified for worst-case conditions, that is, θJA is specified for device

soldered in circuit board for surface-mount packages.

1

θ

JA

Unit

JC

ESD CAUTION

Rev. I | Page 6 of 20

AD8510/AD8512/AD8513

TYPICAL PERFORMANCE CHARACTERISTICS

120

100

80

60

VSY = ±15V
T

= 25°C

A

100k

10k

VSY = ±5V, ±15V

1k

40

NUMBER OF AMPLIF IERS

20

0

–0.5

–0.4 –0.3

–0.2 –0.1 0 0.1 0.2 0.3 0. 4 0.5

INPUT OFFSET VOLTAGE (mV)

Figure 7. Input Offset Voltage Distribution

30

25

20

15

10

NUMBER OF AMPLIF IERS

5

0

0

1

23456

TCVOS (µV/°C)

Figure 8. AD8510/AD8512 TCVOS Distribution

VSY = ±15V
B GRADE

100

INPUT BIAS CURRENT (pA)

10

02729-007

1

–40

–25

–10 5 20 35 50

TEMPERATURE (°C)

80 95 110 125

65

02729-010

Figure 10. Input Bias Current vs. Temperature

1000

100

±15V

10

±5V

1

INPUT OFFSET CURRENT ( pA)

02729-008

0.1
–40

–10 5 20 35 50

–25

TEMPERATURE (°C)

65 80 95 110 125

02729-011

Figure 11. Input Offset Current vs. Temperature

30

25

20

15

10

NUMBER OF AMPLIF IERS

5

0

0

1

2345 6

TCVOS (µV/°C)

Figure 9. AD8510/AD8512 TCVOS Distribution

VSY = ±15V
A GRADE

02729-009

Rev. I | Page 7 of 20

40

TA = 25°C

35

30

25

20

15

10

INPUT BIAS CURRENT (pA)

5

0

8

13

18 23

SUPPLY VOLTAGE (V+ – V– )

28 30

02729-012

Figure 12. Input Bias Current vs. Supply Voltage

AD8510/AD8512/AD8513

R

2.0
TA = 25°C

1.9

1.8

1.7

1.6

AMPLIFI ER (mA)

1.5

1.4

1.3

1.2

SUPPLY CURRENT PE

1.1

1.0
8

13

18 23

SUPPLY VOLTAGE (V+ – V–)

28 30

Figure 13. AD8512 Supply Current per Amplifier vs. Supply Voltage

02729-013

2.8

TA = 25°C

2.6

2.4

2.2

2.0

1.8

1.6

SUPPLY CURRENT (mA)

1.4

1.2

1.0
8

13

18 23 28 33

SUPPLY VOLTAGE (V+ – V–)

Figure 16. AD8510 Supply Current vs. Supply Voltage

02729-016

16

14

12

10

8

6

OUTPUT VOLTAGE (V)

4

2

0

0

10

V

OL

V

OH

V

OL

V

OH

20 30 40 50

= ±5V

V

SY

LOAD CURRENT (mA)

VSY = ±15V

60 70 80

Figure 14. AD8510/AD8512 Output Voltage vs. Load Current

2.50

2.25

2.00

1.75

1.50

1.25

SUPPLY CURRENT PER AMPLIFI ER (mA)

1.00
–40

–25 35 50 95 125

520 6580 110

–10

±15V

±5V

TEMPERATURE (° C)

Figure 15. AD8512 Supply Current per Amplifier vs. Temperature

70

60

50

40

30

20

GAIN (dB)

10

0

–10

02729-014

–20

–30

10k

100k

1M 10M

FREQUENCY (Hz)

VSY = ±15V
R

= 2.5kΩ

L

C

SCOPE

Φ

= 52°

M

= 20pF

50M

315

270

225

180

135

90

45

0

–45

–90

–135

PHASE (Degrees)

02729-017

Figure 17. Open-Loop Gain and Phase vs. Frequency

2.50

2.25

2.00

1.75

1.50

SUPPLY CURRENT (mA)

1.25

02729-015

1.00
–40

–25 35 50 95 125

520 6580 110

–10

±15V

±5V

02729-018

TEMPERATURE (°C)

Figure 18. AD8510 Supply Current vs. Temperature

Rev. I | Page 8 of 20

AD8510/AD8512/AD8513

OUTPUT IMPEDANCE (Ω)

300

VSY = ±15V

270

V

= 50mV

IN

240

210

180

150

120

90

60

30

0

100

1k

AV = 100

AV = 10

10k 10M

100k

FREQUENCY ( Hz)

Figure 22. Output Impedance vs. Frequency

1M

AV = 1

100M

02729-022

70

60

50

40

AV = 100

30

20

AV = 10

10

0

CLOSED-LOOP GAIN (dB)

AV = 1

–10

–20

–30

1k

10k

100k

FREQUENCY ( Hz)

VSY = ±15V, ±5V

1M 10M

02729-019

50M

Figure 19. Closed-Loop Gain vs. Frequency

120

100

80

60

CMRR (dB)

40

20

0

100 1k

120

100

80

60

10k 10M 100M

100k 1M

FREQUENCY ( Hz)

Figure 20. CMRR vs. Frequency

VSY = ±5V, ±15V

–PSRR

VSY = ±15V

1k

100

10

VOLTAGE NOISE DENSI TY (nV/ Hz)

02729-020

1

1 10 100 1k

FREQUENCY (Hz)

VSY = ±5V TO ±15V

10k

02729-023

Figure 23. Voltage Noise Density vs. Frequency

VSY = ±15V

40

PSRR (dB)

20

0

–20

100

1k

Figure 21. PSRR vs. Frequency

+PSRR

100k 1M

10k 10M

FREQUENCY ( Hz)

100M

VOLTAGE (1µV/DIV)

02729-021

TIME (1s/DIV)

02729-024

Figure 24. 0.1 Hz to 10 Hz Input Voltage Noise

Rev. I | Page 9 of 20

AD8510/AD8512/AD8513

T

A

280

245

210

175

140

105

AGE NOISE DENSITY (nV Hz)

70

VOL

35

0

1

0

27

46

3

5

FREQUENCY ( Hz)

Figure 25. Voltage Noise Density vs. Frequency

VSY = ±5V TO ±15V

9

8

02729-025

10

90

VSY = ±15V

80

R

= 2kΩ

L

70

60

50

L OVERSHOO T (%)

40

30

20

SMALL-SIGN

10

0

1

10

LOAD CAPACITANCE (pF)

+OS

–OS

100 1k

Figure 28. Small-Signal Overshoot vs. Load Capacitance

02729-028

10k

VSY = ±15V
R

= 2kΩ

L

C

= 100pF

L

A

= 1

V

VOLTAGE (5V/DIV)

TIME (1µs/DIV)

Figure 26. Large-Signal Transient Response

VSY = ±15V
R

= 2kΩ

L

C

= 100pF

L

A

= 1

V

VOLTAG E (50mV/DIV)

70

60

50

40

30

20

10

0

OPEN-LOOP GAIN (dB)

–10

–20

02729-026

–30

10k

100k

1M 10M 50M

FREQUENCY (Hz)

VSY = ±5V
R

= 2.5kΩ

L

C

SCOPE

Φ

= 44.5°

M

= 20pF

315

270

225

180

135

90

45

0

–45

–90

–135

PHASE (Degrees)

02729-029

Figure 29. Open-Loop Gain and Phase vs. Frequency

120

VSY = ±5V

100

80

60

CMRR (dB)

40

20

0

02729-027

TIME (100ns/DIV)

100

Figure 27. Small-Signal Transient Response

Rev. I | Page 10 of 20

1k

Figure 30. CMRR vs. Frequency

100k

10k 10M

FREQUENCY ( Hz)

1M

100M

02729-030

AD8510/AD8512/AD8513

A

300

VSY = ±5V

270

= 50mV

V

IN

240

210

1M

AV= 1

02729-031

10M 100M

180

150

120

90

OUTPUT IM PEDANCE (Ω)

60

30

0

100

1k

AV= 100

AV= 10

100k

10k

FREQUENCY (Hz)

Figure 31. Output Impedance vs. Frequency

VSY = ±5V
R

= 2kΩ

L

C

= 100pF

L

A

= 1

V

VOLTAGE (50mV/DIV)

TIME (100ns/DIV)

Figure 34. Small-Signal Transient Response

02729-034

VSY = ±5V

VOLTAGE (1µV/DIV)

TIME (1s/ DIV)

Figure 32. 0.1 Hz to 10 Hz Input Voltage Noise

VSY = ±5V
R

= 2kΩ

L

C

= 100pF

L

A

= 1

V

VOLTAGE (2V/DIV)

TIME (1µs/DIV)

Figure 33. Large-Signal Transient Response

100

90

80

70

60

50

L OVERSHOO T (%)

40

30

20

SMALL-SIGN

10

02729-032

0

1

10

LOAD CAPACITANCE (pF)

+OS

–OS

100 1k 10k

VSY = ±5V
R

= 2kΩ

L

02729-035

Figure 35. Small-Signal Overshoot vs. Load Capacitance

100

90

80

70

60

50

40

30

NUMBER OF AMPLI FIERS

20

10

0

0

1

25

02729-033

34

TCVOS (µV/°C)

VS = ±15V

02729-036

6

Figure 36. AD8513 TCVOS Distribution

Rev. I | Page 11 of 20

AD8510/AD8512/AD8513

R

R

120

VS = ±5V

100

80

60

16

14

12

10

8

V

V

OL

OH

VSY = ±15V

40

NUMBER OF AMPLIFIERS

20

0

0

1

25

34

TCVOS (µV/°C)

6

Figure 37. AD8513 TCVOS Distribution

2.5
TA= 25°C

2.4

2.3

2.2

2.1

AMPLIFI ER (mA)

2.0

1.9

1.8

1.7

SUPPLY CURRENT PE

1.6

1.5

8

13

18 33

SUPPLY VOLTAGE (V+ – V–)

23 28

Figure 38. AD8513 Supply Current per Amplifier vs. Supply Voltage

6

OUTPUT VOLTAGE (V)

4

2

02729-037

0

0

10

V

OL

V

OH

30 40

20 50

LOAD CURRENT (mA)

VSY = ±5V

60 70 80

02729-039

Figure 39. AD8513 Output Voltage vs. Load Current

3.0

2.5

2.0

AMPLIFIER (mA)

1.5

1.0

0.5

SUPPLY CURRENT PE

02729-038

0

–40 –25 –10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

±15V

±5V

02729-040

Figure 40. AD8513 Supply Current per Amplifier vs. Temperature

Rev. I | Page 12 of 20

AD8510/AD8512/AD8513

(

GENERAL APPLICATION INFORMATION

INPUT OVERVOLTAGE PROTECTION

The AD8510/AD8512/AD8513 have internal protective
circuitry that allows voltages as high as 0.7 V beyond the
supplies to be applied at the input of either terminal without
causing damage. For higher input voltages, a series resistor is
necessary to limit the input current. The resistor value can be
determined from the formula

VV

−

IN

S

R

S

With a very low offset current of <0.5 nA up to 125°C, higher
resistor values can be used in series with the inputs. A 5 kΩ
resistor protects the inputs from voltages as high as 25 V
beyond the supplies and adds less than 10 µV to the offset.

OUTPUT PHASE REVERSAL

Phase reversal is a change of polarity in the transfer function of
the amplifier. This can occur when the voltage applied at the
input of an amplifier exceeds the maximum common-mode
voltage.

Phase reversal can cause permanent damage to the device and
can result in system lockups. The AD8510/AD8512/AD8513 do
not exhibit phase reversal when input voltages are beyond the
supplies.

VOLTAGE (2V/DIV)

TOTAL HARMONIC DISTORTION (THD) + NOISE

The AD8510/AD8512/AD8513 have low THD and excellent gain
linearity, making these amplifiers great choices for precision
circuits with high closed-loop gain and for audio application
circuits. Figure 42 shows that the AD8510/AD8512/AD8513 have
approximately 0.0005% of total distortion when configured in
positive unity gain (the worst case) and driving a 100 kΩ load.

mA5≤

V

IN

TIME (20µs/DIV)

Figure 41. No Phase Reversal

VSY = ±5V
A

= 1

V

R

= 10kΩ

L

V

OUT

02729-057

0.01

VSY = ±5V
R

= 100kΩ

L

BW = 22kHz

0.001

DISTORTION (%)

0.0001
20 100 1k 10k 20k

Figure 42. THD + N vs. Frequency

FREQUENCY ( Hz)

02729-056

TOTAL NOISE INCLUDING SOURCE RESISTORS

The low input current noise and input bias current of the
AD8510/AD8512/AD8513 make them the ideal amplifiers for
circuits with substantial input source resistance. Input offset
voltage increases by less than 15 nV per 500 Ω of source
resistance at room temperature. The total noise density of the
circuit is

nn

BWee

2

)

kTRRiee 4

++=

SS

–23

J/K).

nTO TAL

≈ e

. The current noise

n

is greater than

S

nTOTAL

2

where:

e

is the input voltage noise density of the parts.

n

i

is the input current noise density of the parts.

n

R

is the source resistance at the noninverting terminal.

S

k is Boltzmann’s constant (1.38 × 10
T is the ambient temperature in Kelvin (T = 273 + °C).

< 3.9 kΩ, en dominates and e

For R

S

of the AD8510/AD8512/AD8513 is so low that its total density
does not become a significant term unless R
165 MΩ, an impractical value for most applications.

The total equivalent rms noise over a specific bandwidth is
expressed as

=

nTOTALnTOTAL

where

BW is the bandwidth in hertz.

Note that the previous analysis is valid for frequencies larger
than 150 Hz and assumes flat noise above 10 kHz. For lower
frequencies, flicker noise (1/f) must be considered.

Rev. I | Page 13 of 20

AD8510/AD8512/AD8513

T

2

V

SETTLING TIME

Settling time is the time it takes the output of the amplifier to
reach and remain within a percentage of its final value after a
pulse is applied at the input. The AD8510/AD8512/AD8513
settle to within 0.01% in less than 900 ns with a step of 0 V to
10 V in unity gain. This makes each of these parts an excellent
choice as a buffer at the output of DACs whose settling time is
typically less than 1 µs.

In addition to the fast settling time and fast slew rate, low offset
voltage drift and input offset current maintain the full accuracy
of 12-bit converters over the entire operating temperature range.

OVERLOAD RECOVERY TIME

Overload recovery, also known as overdrive recovery, is the
time it takes the output of an amplifier to recover to its linear
region from a saturated condition. This recovery time is par­ticularly important in applications where the amplifier must
amplify small signals in the presence of large transient voltages.

Figure 43 shows the positive overload recovery of the AD8510/
AD8512/AD8513. The output recovers in approximately 200 ns
from a saturated condition.

V

= ±15V

SY

V

= 200mV

IN

A

= –100

0V

V

R

= 10kΩ

L

OUTPUTINPUT

–15V

AGE

VOL

200mV

+15V

0V

VOLTAGE

0V

INPUT OUTPUT

–200mV

TIME (2µs/DIV)

Figure 44. Negative Overload Recovery

CAPACITIVE LOAD DRIVE

The AD8510/AD8512/AD8513 are unconditionally stable at all
gains in inverting and noninverting configurations. Each device
is capable of driving a capacitive load of up to 1000 pF without
oscillation in unity gain using the worst-case configuration.

However, as with most amplifiers, driving larger capacitive
loads in a unity gain configuration may cause excessive
overshoot and ringing, or even oscillation. A simple snubber
network significantly reduces the amount of overshoot and
ringing. The advantage of this configuration is that the output
swing of the amplifier is not reduced, because R
feedback loop.

V+

VSY = ±15V

= –100

A

V

= 10kΩ

R

L

is outside the

S

02729-054

0V

02729-053

TIME (2µs/DIV)

Figure 43. Positive Overload Recovery

The negative overdrive recovery time shown in Figure 44 is less
than 200 ns.

In addition to the fast recovery time, the AD8510/AD8512/
AD8513 show excellent symmetry of the positive and negative
recovery times. This is an important feature for transient signal
rectification because the output signal is kept equally undistorted
throughout any given period.

2

00m

3

AD8510

7

6

4

V–

R

S

C

S

V

OUT

C

L

02729-055

Figure 45. Snubber Network Configuration

Rev. I | Page 14 of 20

AD8510/AD8512/AD8513

T

Figure 46 shows a scope plot of the output of the AD8510/AD8512/
AD8513 in response to a 400 mV pulse. The circuit is configured in
positive unity gain (worst case) with a load experience of 500 pF.

VSY = ±15V

= 500pF

C

L

=10kΩ

R

L

VOLTAGE (200mV/DIV)

TIME (1µs/DIV)

02729-041

Figure 46. Capacitive Load Drive Without Snubber

When the snubber circuit is used, the overshoot is reduced from
55% to less than 3% with the same load capacitance. Ringing is
virtually eliminated, as shown in Figure 47.

VSY = ±15V
R

= 10kΩ

L

C

= 500pF

L

R

= 100Ω

S

C

= 1nF

S

AGE (200mV/DI V)

VOL

02729-042

TIME (1µs/DIV)

Figure 47. Capacitive Load with Snubber Network

Optimum values for RS and CS depend on the load capacitance
and input stray capacitance and are determined empirically.
Tabl e 5 shows a few values that can be used as starting points.

Table 5. Optimum Values for Capacitive Loads

C

RS (Ω) CS

LOAD

500 pF 100 1 nF
2 nF 70 100 pF
5 nF 60 300 pF

OPEN-LOOP GAIN AND PHASE RESPONSE

In addition to their impressive low noise, low offset voltage, and
offset current, the AD8510/AD8512/AD8513 have excellent
loop gain and phase response even when driving large resistive
and capacitive loads.

Compared with Competitor A (see Figure 49) under the same
conditions, with a 2.5 kΩ load at the output, the AD8510/AD8512/
AD8513 have more than 8 MHz of bandwidth and a phase margin
of more than 52°.

Competitor A, on the other hand, has only 4.5 MHz of band­width and 28° of phase margin under the same test conditions.
Even with a 1 nF capacitive load in parallel with the 2 kΩ load
at the output, the AD8510/AD8512/AD8513 show much better
response than Competitor A, whose phase margin is degraded
to less than 0, indicating oscillation.

GAIN (dB)

–10

–20

–30

70

60

50

40

30

20

10

0

10k

100k

1M 10M

FREQUENCY (Hz)

VSY = ±15V

= 2.5kΩ

R

L

= 0pF

C

L

Figure 48. Frequency Response of the AD8510/AD8512/AD8513

GAIN (dB)

–10

–20

–30

70

60

50

40

30

20

10

0

10k

100k

1M 10M

FREQUENCY ( Hz)

VSY = ±15V
R

= 2.5kΩ

L

C

= 0pF

L

Figure 49. Frequency Response of Competitor A

50M

50M

315

270

225

180

135

90

45

0

–45

–90

–135

315

270

225

180

135

90

45

0

–45

–90

–135

PHASE (Degrees)

02729-043

PHASE (Degrees)

02729-044

Rev. I | Page 15 of 20

AD8510/AD8512/AD8513

PRECISION RECTIFIERS

Rectifying circuits are used in a multitude of applications. One
of the most popular uses is in the design of regulated power
supplies, where a rectifier circuit is used to convert an input
sinusoid to a unipolar output voltage.

However, there are some potential problems with amplifiers
used in this manner. When the input voltage (V
the output is zero, and the magnitude of V
inputs of the op amp. If this voltage exceeds the power supply
voltage, it may permanently damage some amplifiers. In addition,
the op amp must come out of saturation when V
This delays the output signal because the amplifier requires
time to enter its linear region.

Although the AD8510/AD8512/AD8513 have a very fast
overdrive recovery time, which makes them great choices for the
rectification of transient signals, the symmetry of the positive
and negative recovery times is also important to keep the output
signal undistorted.

Figure 50 shows the test circuit of the rectifier. The first stage of
the circuit is a half-wave rectifier. When the sine wave applied at
the input is positive, the output follows the input response.
During the negative cycle of the input, the output tries to swing
negative to follow the input, but the power supply restrains it to
zero. In a similar fashion, the second stage is a follower during
the positive cycle of the sine wave and an inverter during the
negative cycle.

R2

10kΩ

10V

V

IN

3V p-p

R1

1kΩ

3

AD8512

2

8

1/2

1

4

6

5

) is negative,

IN

is doubled at the

IN

is negative.

IN

R3

10kΩ

4

2/2

AD8512

8

7

OUT B
(FULL WAVE)

VOLTAGE (1V/DIV)

TIME (1ms/DIV)

02729-046

Figure 51. Half-Wave Rectifier Signal (OUT A in Figure 50)

VOLTAGE (1V/DIV)

02729-047

TIME (1ms/DIV)

Figure 52. Full-Wave Rectifier Signal (OUT B in Figure 50)

10V

OUT A
(HALF WAVE)

02729-045

Figure 50. Half-Wave and Full-Wave Rectifiers

Rev. I | Page 16 of 20

AD8510/AD8512/AD8513

V

I-V CONVERSION APPLICATIONS

Photodiode Circuits

Common applications for I-V conversion include photodiode
circuits where the amplifier is used to convert a current emitted
by a diode placed at the positive input terminal into an output
voltage.

The AD8510/AD8512/AD8513’s low input bias current, wide
bandwidth, and low noise make them each an excellent choice
for various photodiode applications, including fax machines,
fiber optic controls, motion sensors, and bar code readers.

The circuit shown in Figure 53 uses a silicon diode with zero
bias voltage. This is known as a photovoltaic mode; this
configuration limits the overall noise and is suitable for
instrumentation applications.

Cf

R2

V

EE

4

2

AD8510

Rd Ct

Figure 53. Equivalent Preamplifier Photodiode Circuit

3

A larger signal bandwidth can be attained at the expense of
additional output noise. The total input capacitance (Ct)
consists of the sum of the diode capacitance (typically 3 pF to
4 pF) and the amplifier’s input capacitance (12 pF), which
includes external parasitic capacitance. Ct creates a pole in the
frequency response that can lead to an unstable system. To
ensure stability and optimize the bandwidth of the signal, a
capacitor is placed in the feedback loop of the circuit shown in
Figure 53. It creates a zero and yields a bandwidth whose corner
frequency is 1/(2π(R2Cf)).

The value of R2 can be determined by the ratio

V/I

D

where:

V is the desired output voltage of the op amp.
I

is the diode current.

D

For example, if I

is 100 µA and a 10 V output voltage is desired,

D

R2 should be 100 kΩ. Rd (see Figure 53) is a junction resistance
that drops typically by a factor of 2 for every 10°C increase in
temperature.

6

7

V

CC

02729-048

A typical value for Rd is 1000 MΩ. Because Rd >> R2, the
circuit behavior is not impacted by the effect of the junction
resistance. The maximum signal bandwidth is

f

MAX

where

ft is the unity gain frequency of the amplifier.

ft

=

CtR

22π

Cf can be calculated by

Cf

Ct

=

ftR

22π

where ft is the unity gain frequency of the op amp, and it achieves
a phase margin, φ

, of approximately 45°.

M

A higher phase margin can be obtained by increasing the value
of Cf. Setting Cf to twice the previous value yields approximately

= 65° and a maximal flat frequency response, but it reduces the

φ

M

maximum signal bandwidth by 50%.

Using the previous parameters with a Cf ≈ 1 pF, the signal
bandwidth is approximately 2.6 MHz.

Signal Transmission Applications

One popular signal transmission method uses pulse-width
modulation. High data rates may require a fast comparator
rather than an op amp. However, the need for sharp, undistorted
signals may favor using a linear amplifier.

The AD8510/AD8512/AD8513 make excellent voltage
comparators. In addition to a high slew rate, the AD8510/
AD8512/AD8513 have a very fast saturation recovery time. In
the absence of feedback, the amplifiers are in open-loop mode
(very high gain). In this mode of operation, they spend much of
their time in saturation.

The circuit shown in Figure 54 was used to compare two signals
of different frequencies, namely a 100 Hz sine wave and a 1 kHz
triangular wave. Figure 55 shows a scope plot of the resulting
output waveforms. A pull-up resistor (typically 5 kΩ) can be
connected from the output to V

if the output voltage needs to

CC

reach the positive rail. The trade-off is that power consumption
is higher.

+15

3

7

6

2

4

V1

–15V

V2

Figure 54. Pulse-Width Modulator

V

OUT

02729-049

Rev. I | Page 17 of 20

AD8510/AD8512/AD8513

V

R
A

The AD8510 single has two additional active terminals that are
not present on the AD8512 dual or AD8513 quad parts. These
pins are labeled “null” and are used for fine adjustment of the
input offset voltage. Although the guaranteed maximum offset
voltage at room temperature is 400 µV and over the −40°C to
+125°C range is 800 mV maximum, this offset voltage can be
reduced by adding a potentiometer to the null pins as shown in

VOLTAGE (5V/DIV)

02729-050

TIME (2ms/DIV)

Figure 55. Pulse-Width Modulation

Crosstalk

Crosstalk, also known as channel separation, is a measure of
signal feedthrough from one channel to another on the same
IC. The AD8512/AD8513 have a channel separation of better
than −90 dB for frequencies up to 10 kHz and of better than

−50 dB for frequencies up to 10 MHz. Figure 57 shows the
typical channel separation behavior between Amplifier A
(driving amplifier) and each of the following: Amplifier B,
Amplifier C, and Amplifier D.

OUT

2.2kΩ

6

5

02729-052

2

18V p-p

3

V

IN

CROSSTALK = 20 log

Figure 56. Crosstalk Test Circuit

0

–20

20kΩ

+V

S

8

1

7

4

5kΩ5kΩ

–V

V

10V

OUT

IN

S

Figure 58. With the 20 k potentiometer shown, the adjustment
range is approximately ±3.5 mV. The potentiometer parallels
low value resistors in the drain circuit of the JFET differential
input pair and allows unbalancing of the drain currents to
change the offset voltage. If offset adjustment is not required,
these pins should be left unconnected.

Caution should be used when adding adjusting potentiometers to
any op amp with this capability for several reasons. First, there is
gain from these nodes to the output; therefore, capacitive coupling
from noisy traces to these nodes will inject noise into the signal
path. Second, the temperature coefficient of the potentiometer
will not match the temperature coefficient of the internal resistors,
so the offset voltage drift with temperature will be slightly affected.
Third, this provision is for adjusting the offset voltage of the
op amp, not for adjusting the offset of the overall system. Although
it is tempting to decrease the value of the potentiometer to attain
more range, this will adversely affect the dc and ac parameters.
Instead, increase the potentiometer to 50 kΩ to decrease the
range if needed.

20kΩ

1

5

2

–

INPUT OUTPUT

AD8510

3

+

7

4

V–

Figure 58. Optional Offset Nulling Circuit

V+

6

V

TRIM RANGE I S

OS

TYPICALLY ±3.5mV

2729-058

–40

TION (dB)

CHANNEL SEPA

–60

–80

–100

–120

–140

–160

100

1k

10k

FREQUENCY ( Hz)

CH B

100k

CH D

CH C

1M 10M

02729-051

Figure 57. Channel Separation

Rev. I | Page 18 of 20

AD8510/AD8512/AD8513

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

5.10

5.00

4.90

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARI TY

0.10

CONTROL LING DIMENSI ONS ARE IN MILL IMET ERS; INCH DI MENSIO NS
(IN PARENTHESES ) ARE ROUNDED- OFF MI LLI METER EQ UIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE I N DESIG N.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLI ANT TO JEDE C STANDARDS MS-012-A A

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

Figure 59. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

3.20

3.00

2.80

8

5

3.20

3.00

2.80

1

5.15

4.90

4.65

4

PIN 1

0.65 BSC

0.95

0.85

0.75

0.15

0.00

COPLANARITY

0.10

0.38

0.22

1.10 MAX

SEATING
PLANE

0.23

0.08

8°
0°

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 60. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

0.80

0.60

0.40

45°

4.50

4.40

4.30

14

8

6.40

BSC

71

PIN 1

1.05

1.00

0.80

012407-A

0.65

0.15

0.05

BSC

0.30

0.19

SEATING
PLANE

1.20
MAX

COPLANARITY

0.20

0.09

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

8°
0°

0.75

0.60

0.45

Figure 61. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

8.75 (0.3445)

8.55 (0.3366)

BSC

8

7

6.20 (0.2441)

5.80 (0.2283)

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0197)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

45°

060606-A

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARIT Y

0.10

14

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

CONTROLL ING DIMENS IONS ARE IN MILLIM ETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED- OFF MIL LIMET ER EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DES IGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AB

Figure 62. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-14)

Dimensions shown in millimeters and (inches)

Rev. I | Page 19 of 20

AD8510/AD8512/AD8513

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8510ARMZ-REEL
AD8510ARMZ
AD8510AR −40°C to +125°C 8-Lead SOIC_N R-8
AD8510ARZ
AD8510ARZ-REEL
AD8510ARZ-REEL7
AD8510BR −40°C to +125°C 8-Lead SOIC_N R-8
AD8510BR-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8510BRZ
AD8510BRZ-REEL
AD8510BRZ-REEL7
AD8512ARMZ-REEL
AD8512ARMZ
AD8512AR −40°C to +125°C 8-Lead SOIC_N R-8
AD8512AR-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8512AR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8512ARZ
AD8512ARZ-REEL
AD8512ARZ-REEL7
AD8512BR −40°C to +125°C 8-Lead SOIC_N R-8
AD8512BR-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8512BR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8512BRZ
AD8512BRZ-REEL
AD8512BRZ-REEL7
AD8513AR −40°C to +125°C 14-Lead SOIC_N R-14
AD8513AR-REEL −40°C to +125°C 14-Lead SOIC_N R-14
AD8513AR-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14
AD8513ARZ
AD8513ARZ-REEL
AD8513ARZ-REEL7
AD8513ARU −40°C to +125°C 14-Lead TSSOP RU-14
AD8513ARU-REEL −40°C to +125°C 14-Lead TSSOP RU-14
AD8513ARUZ
AD8513ARUZ-REEL

1

Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.

1

−40°C to +125°C 8-Lead MSOP RM-8 B7A#

1

−40°C to +125°C 8-Lead MSOP RM-8 B7A#

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead MSOP RM-8 B8A#

1

−40°C to +125°C 8-Lead MSOP RM-8 B8A#

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 14-Lead SOIC_N R-14

1

−40°C to +125°C 14-Lead SOIC_N R-14

1

−40°C to +125°C 14-Lead SOIC_N R-14

1

−40°C to +125°C 14-Lead TSSOP RU-14

1

−40°C to +125°C 14-Lead TSSOP RU-14

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