Analog Devices AD8400, AD8403, AD8402 Datasheet

1-/2-/4-Channel

RDAC1

SHDN

8

8-BIT

LATCH

CK

RS

RDAC2

SHDN

8

8-BIT

LATCH

CK

RS

RDAC3

SHDN

8

8-BIT

LATCH

CK

RS

RDAC4

SHDN

8

8-BIT

LATCH

CK

RS

SHDN

DAC

SELECT

A1, A0

1
2
3
4

10-BIT

SERIAL

LATCH

CK Q RS

D

RS

SDO

A1
W1
B1
AGND1

A2
W2
B2
AGND2

A3
W3

B3
AGND3

A4
W4

B4
AGND4

AD8403

V

DD

DGND

SDI

CLK

CS

8

2

a

Digital Potentiometers

AD8400/AD8402/AD8403

FEATURES
256 Position
Replaces 1, 2 or 4 Potentiometers
1 kV, 10 kV, 50 kV, 100 kV
Power Shut Down—Less than 5 mA
3-Wire SPI Compatible Serial Data Input
10 MHz Update Data Loading Rate
+2.7 V to +5.5 V Single-Supply Operation
Midscale Preset

APPLICATIONS
Mechanical Potentiometer Replacement
Programmable Filters, Delays, Time Constants
Volume Control, Panning
Line Impedance Matching
Power Supply Adjustment

GENERAL DESCRIPTION

The AD8400/AD8402/AD8403 provide a single, dual or quad
channel, 256 position digitally controlled variable resistor (VR)
device. These devices perform the same electronic adjustment
function as a potentiometer or variable resistor. The AD8400
contains a single variable resistor in the compact SO-8 package.
The AD8402 contains two independent variable resistors in
space saving SO-14 surface mount package. The AD8403 con­tains four independent variable resistors in 24-lead PDIP, SOIC
and TSSOP packages. Each part contains a fixed resistor with a
wiper contact that taps the fixed resistor value at a point deter­mined by a digital code loaded into the controlling serial input
register. The resistance between the wiper and either endpoint
of the fixed resistor varies linearly with respect to the digital
code transferred into the VR latch. Each variable resistor offers
a completely programmable value of resistance, between the A
terminal and the wiper or the B terminal and the wiper. The
fixed A to B terminal resistance of 1 kΩ, 10 kΩ, 50 kΩ or 100 kΩ
has a ±1% channel-to-channel matching tolerance with a nominal
temperature coefficient of 500 ppm/°C. A unique switching cir­cuit minimizes the high glitch inherent in traditional switched
resistor designs avoiding any make-before-break or break-before­make operation.

Each VR has its own VR latch that holds its programmed

The reset (
loading 80
tor to an end-to-end open circuit condition on the A terminal
and shorts the wiper to the B terminal, achieving a microwatt
power shutdown state. When
the previous latch settings put the wiper in the same resistance
setting prior to shutdown. The digital interface is still active in
shutdown so that code changes can be made which will produce
new wiper positions when the device is taken out of shutdown.

The AD8400 is available in both the SO-8 surface mount and
the 8-lead plastic DIP package.

The AD8402 is available in both surface mount (SO-14) and
the 14-lead plastic DIP package, while the AD8403 is available
in a narrow body 24-lead plastic DIP and the 24-lead surface
mount package. The AD8402/AD8403 are also offered in the

1.1 mm thin TSSOP-14/TSSOP-24 package for PCMCIA ap­plications. All parts are guaranteed to operate over the extended
industrial temperature range of –40°C to +85°C.

resistance value. These VR latches are updated from an SPI
compatible serial-to-parallel shift register that is loaded from a
standard 3-wire serial-input digital interface. Ten data bits make
up the data word clocked into the serial input register. The data
word is decoded where the first two bits determine the address
of the VR latch to be loaded, the last eight bits are data. A serial
data output pin at the opposite end of the serial register allows
simple daisy-chaining in multiple VR applications without addi­tional external decoding logic.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

FUNCTIONAL BLOCK DIAGRAM

RS) pin forces the wiper to the midscale position by

into the VR latch. The SHDN pin forces the resis-

H

SHDN is returned to logic high,

AD8400/AD8402/AD8403–SPECIFICATIONS

10 kV VERSION
ELECTRICAL CHARACTERISTICS

(VDD = +3 V 6 10% or + 5 V 6 10%, VA = +VDD, VB = 0 V, –408C ≤ TA ≤ +858C unless
otherwise noted)

Parameter Symbol Conditions Min Typ1Max Units

DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs

Resistor Differential NL
Resistor Nonlinearity
Nominal Resistance
Resistance Tempco ∆R
Wiper Resistance R
Nominal Resistance Match ∆R/R

2

2

3

R-DNL RWB, VA = NC –1 ±1/4 +1 LSB
R-INL RWB, VA = NC –2 ±1/2 +2 LSB
RT

/∆TV

AB

W

O

= +25°C, Model: AD840XYY10 8 10 12 kΩ

A

= VDD, Wiper = No Connect 500 ppm/°C

AB

IW = 1 V/R 50 100 Ω
CH 1 to 2, 3, or 4, VAB = VDD, TA = +25°C 0.2 1 %

DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs

Resolution N 8 Bits
Integral Nonlinearity
Differential Nonlinearity

Voltage Divider Tempco ∆V
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance
Capacitance

6
6

Shutdown Current
Shutdown Wiper Resistance R

4

4

5

Ax, Bx C
Wx C

7

INL –2 ±1/2 +2 LSB
DNL V
DNL V
DNL V

/∆T Code = 80

W
WFSE
WZSE

V

A, B, W
A, B
W

I

A_SD

W_SD

= +5 V –1 ±1/4 +1 LSB

DD

= +3 V TA = +25°C–1±1/4 +1 LSB

DD

= +3 V TA = –40°C, +85°C –1.5 ±1/2 +1.5 LSB

DD

Code = FF
Code = 00

f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80

H

H

H

H
H

–4 –2.8 0 LSB
0 +1.3 +2 LSB

0V

15 ppm/°C

V

DD

75 pF

120 pF
VA = VDD, VB = 0 V, SHDN = 0 0.01 5 µA
VA = VDD, VB = 0 V, SHDN = 0, V

= +5 V 100 200 Ω

DD

DIGITAL INPUTS & OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
Input Capacitance

6

IH
IL
IH
IL
OH
OL

IL

C

IL

VDD = +5 V 2.4 V
VDD = +5 V 0.8 V
VDD = +3 V 2.1 V
VDD = +3 V 0.6 V
RL = 1 kΩ to V

DD

VDD–0.1 V
IOL = 1.6 mA, VDD = +5 V 0.4 V
VIN = 0 V or +5 V, VDD = +5 V ±1 µA

5pF

POWER SUPPLIES

Power Supply Range V
Supply Current (CMOS) I
Supply Current (TTL)
Power Dissipation (CMOS)

8

9

Power Supply Sensitivity PSS V

Range 2.7 5.5 V

I
P

DD
DD
DD

DISS

VIH = VDD or VIL = 0 V 0.01 5 µA
VIH = 2.4 V or 0.8 V, VDD = +5.5 V 0.9 4 mA
VIH = VDD or VIL = 0 V, VDD = +5.5 V 27.5 µW

= +5 V ± 10% 0.0002 0.001 %/%

DD

PSS VDD = +3 V ± 10% 0.006 0.03 %/%

DYNAMIC CHARACTERISTICS

6, 10

Bandwidth –3 dB BW_10K R = 10 kΩ 600 kHz
Total Harmonic Distortion THD
V

Settling Time t

W

Resistor Noise Voltage e
Crosstalk

NOTES FOR 10 kΩ VERSION

1

Typicals represent average readings at +25°C and VDD = +5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 30 test circuit.
IW = 50 µA for VDD = +3 V and IW = 400 µA for VDD = +5 V for the 10 kΩ versions.

3

V

AB

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL Specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.

5

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.

7

Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.

8

Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I

9

P

DISS

10

All Dynamic Characteristics use VDD = +5 V.

11

Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.

Specifications subject to change without notice.

11

= VDD, Wiper (VW) = No Connect.

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

S

C

W

NWB

T

VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 %
VA = VDD, VB = 0 V, ±1% Error Band 2 µs
RWB = 5 kΩ, f = 1 kHz, RS = 0 9 nV/√Hz
VA = VDD, VB = 0 V –65 dB

versus logic voltage.

DD

–2–

REV. B

SPECIFICATIONS

50 kV & 100 kV VERSION
ELECTRICAL CHARACTERISTICS

(VDD = +3 V 6 10% or + 5 V 6 10%, VA = +VDD, VB = 0 V, –408C ≤ TA ≤ +858C unless
otherwise noted)

AD8400/AD8402/AD8403

Parameter Symbol Conditions Min Typ1Max Units

DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs

Resistor Differential NL
Resistor Nonlinearity
Nominal Resistance

Resistance Tempco ∆R
Wiper Resistance R
Nominal Resistance Match ∆R/R

2

2

3

R-DNL RWB, VA = NC –1 ±1/4 +1 LSB
R-INL RWB, VA = NC –2 ±1/2 +2 LSB
RT
RT

/∆TV

AB

W

O

= +25°C, Model: AD840XYY50 35 50 65 kΩ

A

= +25°C, Model: AD840XYY100 70 100 130 kΩ

A

= VDD, Wiper = No Connect 500 ppm/°C

AB

IW = 1 V/R 53 100 Ω
CH 1 to 2, 3, or 4, VAB = VDD, TA = +25°C 0.2 1 %

DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs

Resolution N 8 Bits
Integral Nonlinearity
Differential Nonlinearity

Voltage Divider Tempco ∆V
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance
Capacitance

6
6

Shutdown Current
Shutdown Wiper Resistance R

4

4

5

Ax, Bx C
Wx C

7

INL –4 ±1 +4 LSB
DNL V
DNL V
DNL V

/∆T Code = 80

W
WFSE
WZSE

V

A, B, W

A, B
W

I

A_SD

W_SD

= +5 V –1 ±1/4 +1 LSB

DD

= +3 V TA = +25°C–1±1/4 +1 LSB

DD

= +3 V TA = –40°C, +85°C –1.5 ±1/2 +1.5 LSB

DD

Code = FF
Code = 00

f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80

H

H

H

H
H

–1 –0.25 0 LSB
0 +0.1 +1 LSB

0V

15 ppm/°C

V

DD

15 pF

80 pF
VA = VDD, VB = 0 V, SHDN = 0 0.01 5 µA
VA = VDD, VB = 0 V, SHDN = 0, V

= +5 V 100 200 Ω

DD

DIGITAL INPUTS & OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
Input Capacitance

6

IH
IL
IH
IL
OH
OL

IL

C

IL

VDD = +5 V 2.4 V
VDD = +5 V 0.8 V
VDD = +3 V 2.1 V
VDD = +3 V 0.6 V
RL = 1 kΩ to V

DD

VDD–0.1 V
IOL = 1.6 mA, VDD = +5 V 0.4 V
VIN = 0 V or +5 V, VDD = +5 V ±1 µA

5pF

POWER SUPPLIES

Power Supply Range V
Supply Current (CMOS) I
Supply Current (TTL)
Power Dissipation (CMOS)

8

9

Power Supply Sensitivity PSS V

Range 2.7 5.5 V

I
P

DD
DD
DD

DISS

VIH = VDD or VIL = 0 V 0.01 5 µA
VIH = 2.4 V or 0.8 V, VDD = +5.5 V 0.9 4 mA
VIH = VDD or VIL = 0 V, VDD = +5.5 V 27.5 µW

= +5 V ± 10% 0.0002 0.001 %/%

DD

PSS VDD = +3 V ± 10% 0.006 0.03 %/%

DYNAMIC CHARACTERISTICS

6, 10

Bandwidth –3 dB BW_50K R = 50 kΩ 125 kHz

BW_100K R = 100 kΩ 71 kHz

Total Harmonic Distortion THD

Settling Time tS_50K VA = VDD, VB = 0 V, ±1% Error Band 9 µs

V

W

Resistor Noise Voltage e

Crosstalk

NOTES FOR 50 kΩ and 100 kΩ VERSIONS

1

Typicals represent average readings at +25°C and VDD = +5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 30 test circuit.
IW = VDD/R for VDD = +3 V or +5 V for the 50 kΩ and 100 kΩ versions.

3

V

AB

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL Specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.

5

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.

7

Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.

8

Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I

9

P

DISS

10

All Dynamic Characteristics use VDD = +5 V.

11

Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.

Specifications subject to change without notice.

11

= VDD, Wiper (VW) = No Connect.

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

W

t

_100K VA = VDD, VB = 0 V, ±1% Error Band 18 µs

S

_50K RWB = 25 kΩ, f = 1 kHz, RS = 0 20 nV/√Hz

NWB

_100K RWB = 50 kΩ, f = 1 kHz, RS = 0 29 nV/√Hz

e

NWB

C

T

VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 %

VA = VDD, VB = 0 V –65 dB

versus logic voltage.

DD

REV. B

–3–

AD8400/AD8402/AD8403–SPECIFICATIONS

1 kV VERSION
ELECTRICAL CHARACTERISTICS

(VDD = +3 V 6 10% or + 5 V 6 10%, VA = +VDD, VB = 0 V, –408C ≤ TA ≤ +858C unless
otherwise noted)

Parameter Symbol Conditions Min Typ1Max Units

DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs

Resistor Differential NL
Resistor Nonlinearity
Nominal Resistance
Resistance Tempco ∆R
Wiper Resistance R
Nominal Resistance Match ∆R/R

2

2

3

R-DNL RWB, VA = NC –5 –1 +3 LSB
R-INL RWB, VA = NC –4 ±1.5 +4 LSB
RT

/∆TV

AB

W

O

= +25°C, Model: AD840XYY1 0.8 1.2 1.5 kΩ

A

= VDD, Wiper = No Connect 700 ppm/°C

AB

IW = 1 V/R

AB

53 100 Ω

CH 1 to 2, VAB = VDD, TA = +25°C 0.75 2 %

DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs

Resolution N 8 Bits
Integral Nonlinearity
Differential Nonlinearity

Voltage Divider Temperature Coefficent ∆V
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance
Capacitance

6
6

Shutdown Supply Current
Shutdown Wiper Resistance R

4

4

5

Ax, Bx C
Wx C

7

INL –6 ±2 +6 LSB
DNL V
DNL V

/∆T Code = 80

W
WFSE
WZSE

V

A, B, W
A, B
W

I

DD_SD

W_SD

= +5 V –4 –1.5 +2 LSB

DD

= +3 V, TA = +25°C –5 –2 +5 LSB

DD

Code = FF
Code = 00

f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80

H

H

H

H
H

–20 –12 0 LSB
0 6 10 LSB

0V

25 ppm/°C

V

DD

75 pF

120 pF
VA = VDD, VB = 0 V, SHDN = 0 0.01 5 µA
VA = VDD, VB = 0 V, SHDN = 0, V

= +5 V 50 100 Ω

DD

DIGITAL INPUTS & OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
Input Capacitance

6

IH
IL
IH
IL
OH
OL

IL

C

IL

VDD = +5 V 2.4 V
VDD = +5 V 0.8 V
VDD = +3 V 2.1 V
VDD = +3 V 0.6 V
RL = 1 kΩ to V

DD

VDD–0.1 V
IOL = 1.6 mA, VDD = +5 V 0.4 V
VIN = 0 V or +5 V, VDD = +5 V ±1 µA

5pF

POWER SUPPLIES

Power Supply Range V
Supply Current (CMOS) I
Supply Current (TTL)
Power Dissipation (CMOS)

8

9

Power Supply Sensitivity PSS ∆V

Range 2.7 5.5 V

I
P

DD
DD
DD

DISS

VIH = VDD or VIL = 0 V 0.01 5 µA
VIH = 2.4 V or 0.8 V, VDD = +5.5 V 0.9 4 mA
VIH = VDD or VIL = 0 V, VDD = +5.5 V 27.5 µW

= +5 V ± 10% 0.0035 0.008 %/%

DD

PSS ∆VDD = +3 V ± 10% 0.05 0.13 %/%

DYNAMIC CHARACTERISTICS

6, 10

Bandwidth –3 dB BW_1K R = 1 kΩ 5,000 kHz
Total Harmonic Distortion THD
V

Settling Time t

W

Resistor Noise Voltage e
Crosstalk

NOTES FOR 1 kΩ VERSION

1

Typicals represent average readings at +25°C and VDD = +5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. See Figure 30 test circuit.
IW = 500 µA for VDD = +3 V and IW = 4 mA for VDD = +5 V for 1 kΩ version.

3

V

AB

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL Specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.

5

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.

7

Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.

8

Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I

9

P

DISS

10

All Dynamic Characteristics use VDD = +5 V.

11

Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.

Specifications subject to change without notice.

11

= VDD, Wiper (VW) = No Connect.

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

S

C

W

NWB

T

VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.015 %
VA = VDD, VB = 0 V, ±1% Error Band 0.5 µs
RWB = 500 Ω, f = 1 kHz, RS = 0 3 nV/√Hz
VA = VDD, VB = 0 V –65 dB

versus logic voltage.

DD

–4–

REV. B

AD8400/AD8402/AD8403–SPECIFICATIONS

WARNING!

ESD SENSITIVE DEVICE

±1%

±1% ERROR BAND

RS

1

0

V

DD

VDD/2

V

OUT

t

RS

t

S

All VERSIONS

(VDD = +3 V 6 10% or + 5 V 6 10%, VA = +VDD, VB = 0 V, –408C ≤ TA ≤ +858C unless

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ1Max Units

SWITCHING CHARACTERISTICS

Input Clock Pulse Width tCH, t
Data Setup Time t
Data Hold Time t
CLK to SDO Propagation Delay

CS Setup Time t
CS High Pulse Width t

Reset Pulse Width t
CLK Fall to

CS Rise Hold Time t

CS Rise to Clock Rise Setup t

NOTES

1

Typicals represent average readings at +25°C and VDD = +5 V.

2

Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.

3

See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using VDD = +3 V or +5 V. To avoid false clocking a minimum input logic slew rate of 1 V/µs should be maintained.

4

Propagation Delay depends on value of VDD, RL and CL–see applications text.

Specifications subject to change without notice.

1

SDI

CLK

V

CS

OUT

A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

0
1

0

1

0

V

DD

0V

Figure 1a. Timing Diagram

1

SDI

(DATA IN)

(DATA OUT)

SDO

V

CLK

CS

OUT

0

1

A'x OR D'x A'x OR D'x

0

t

PD_MIN

t

1

0

1

0

V

DD

0V

CH

t

CSS

Figure 1b. Detail Timing Diagram

2, 3

4

DAC REGISTER LOAD

Ax OR DxAx OR Dx

t

DS

t

DH

t

CL

t

CSH

otherwise noted)

CL
DS
DH

t

PD
CSS
CSW
RS
CSH
CS1

t

PD_MAX

t

CS1

t

CSW

t

S

±1 % ERROR BAND

Clock Level High or Low 10 ns

5ns
5ns

RL = 1 kΩ to +5 V, CL ≤ 20 pF 1 25 ns

10 ns
10 ns
50 ns
0ns
10 ns

Figure 1c. Reset Timing Diagram

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C, unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V

V

, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V

A

AX–BX, AX–WX, BX–W

. . . . . . . . . . . . . . . . . . . . . . ±20 mA

X

Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V

Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C

Maximum Junction Temperature (T

max) . . . . . . . . . +150°C

J

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C

Package Power Dissipation . . . . . . . . . . . . . . (T

Thermal Resistance (θ

)

JA

max–T

J

P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +83°C/W

P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +63°C/W

SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . +70°C/W

±1 %

SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . +120°C/W

TSSOP-14 (RU-14) . . . . . . . . . . . . . . . . . . . . . . +180°C/W

TSSOP-24 (RU-24) . . . . . . . . . . . . . . . . . . . . . . +143°C/W

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

DD

)/θ

A

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8400/AD8402/AD8403 feature proprietary ESD protection circuitry, perma­nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–5–

REV. B

AD8400/AD8402/AD8403

1
2
3
4

8
7
6
5

TOP VIEW

(Not to Scale)

AD8400

B1

CLK

V

DD

W1

A1

GND

CS

SDI

14
13
12
11
10

9
8

1
2
3
4

7

6

5

TOP VIEW

(Not to Scale)

AGND

V

DD

W1

A1

B1
B2
A2

W2

AD8402

SDI

CLK

RSDGND

SHDN

CS

13

16
15
14

24
23
22
21
20
19
18
17

TOP VIEW

(Not to Scale)

12

11

10

9

8

1
2
3
4

7

6

5

AD8403

AGND2

AGND1

W1

A1

B1
B2
A2

W2

W3

A3

B3

AGND4

B4
A4

W4

DGND

SHDN

RS

V

DD

AGND3

CS

SDI

CLK

SDO

ORDERING GUIDE

#CHs/ Temperature Package Package

Model kV Range Description Option*

AD8400AN10 X1/10 -40°C to +85°C PDIP-8 N-8
AD8400AR10 X1/10 -40°C to +85°C SO-8 SO-8
AD8402AN10 X2/10 -40°C to +85°C PDIP-14 N-14
AD8402AR10 X2/10 -40°C to +85°C SO-14 SO-14
AD8402ARU10 X2/10 -40°C to +85°C TSSOP-14 RU-14
AD8403AN10 X4/10 -40°C to +85°C PDIP-24 N-24
AD8403AR10 X4/10 -40°C to +85°C SOIC-24 SOL-24
AD8403ARU10 X4/10 -40°C to +85°C TSSOP-24 RU-24

AD8400AN50 X1/50 -40°C to +85°C PDIP-8 N-8
AD8400AR50 X1/50 -40°C to +85°C SO-8 SO-8
AD8402AN50 X2/50 -40°C to +85°C PDIP-14 N-14
AD8402AR50 X2/50 -40°C to +85°C SO-14 SO-14
AD8403AN50 X4/50 -40°C to +85°C PDIP-24 N-24
AD8403AR50 X4/50 -40°C to +85°C SOIC-24 SOL-24

AD8400AN100 X1/100 -40°C to +85°C PDIP-8 N-8
AD8400AR100 X1/100 -40°C to +85°C SO-8 SO-8
AD8402AN100 X2/100 -40°C to +85°C PDIP-14 N-14
AD8402AR100 X2/100 -40°C to +85°C SO-14 SO-14
AD8402ARU100 X2/100 -40°C to +85°C TSSOP-14 RU-14
AD8403AN100 X4/100 -40°C to +85°C PDIP-24 N-24
AD8403AR100 X4/100 -40°C to +85°C SOIC-24 SOL-24
AD8403ARU100 X4/100 -40°C to +85°C TSSOP-24 RU-24

AD8400AN1 X1/1 -40°C to +85°C PDIP-8 N-8
AD8400AR1 X1/1 -40°C to +85°C SO-8 SO-8
AD8402AN1 X2/1 -40°C to +85°C PDIP-14 N-14
AD8402AR1 X2/1 -40°C to +85°C SO-14 SO-14
AD8403AN1 X4/1 -40°C to +85°C PDIP-24 N-24
AD8403AR1 X4/1 -40°C to +85°C SOIC-24 SOL-24
AD8403ARU1 X4/1 -40°C to +85°C TSSOP-24 RU-24

*N = Plastic DIP; SO = Small Outline; RU = Thin Shrink SO.
The AD8400, AD8402 and the AD8403 contain 720 transistors.

Table I. Serial Data Word Format

ADDR DATA
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB MSB LSB

9

2

8

2

7

2

0

2

PIN CONFIGURATIONS

–6–

REV. B