ANALOG DEVICES AD8342 Service Manual

Active Receive Mixer

V

FEATURES

Broadband RF, LO, and IF ports
Conversion gain: 3.7 dB
Noise figure: 12.2 dB
Input IP3: 22.7 dBm
Input P1dB: 8.3 dBm
LO drive: 0 dBm
Differential high impedance RF input port
Single-ended, 50 Ω LO input port
Open-collector IF output port
Single-supply operation: 5 V @ 98 mA
Power-down mode
Exposed paddle LFCSP: 3 mm × 3 mm

APPLICATIONS

Cellular base station receivers
ISM receivers
Radio links
RF instrumentation

LF to 3 GHz

AD8342

FUNCTIONAL BLOCK DIAGRAM

PDC PWDN EXRB COMM

9

11

BIAS

2

Figure 1.

10

COMM

8

IFOP

7

6

IFOM

5

COMM

4

3

05352-001

12

COMM

13

RFCM

14

AD8342

RFIN

15

VPMX

16

1

VPLO LOCM LOIN COMM

GENERAL DESCRIPTION

The AD8342 is a high performance, broadband active mixer.
It is well suited for demanding receive-channel applications
that require wide bandwidth on all ports and very low
intermodulation distortion and noise figure.

The AD8342 provides a typical conversion gain of 3.7 dB with
an RF frequency of 238 MHz. The integrated LO driver presents
a 50 Ω input impedance with a low LO drive level, helping to
minimize the external component count.

The differential high impedance broadband RF port allows for
easy interfacing to both active devices and passive filters. The
RF input accepts input signals as large as 1.6 V p-p or 8 dBm
(relative to 50 Ω) at P1dB.

The open-collector differential outputs provide excellent balance
and can be used with a differential filter or IF amplifier, such as
the AD8370, AD8375, AD8351, AD8352, or ADL5561. These
outputs can also be converted to a single-ended signal using a
matching network or a balun transformer. The outputs are
capable of swinging 2 V p-p when biased to the VPOS supply
rail.

The AD8342 is fabricated on an Analog Devices, Inc.,
proprietary, high performance SiGe IC process. The AD8342 is
available in a 16-lead LFCSP. It operates over a −40°C to +85°C
temperature range. An evaluation board is also available.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007–2009 Analog Devices, Inc. All rights reserved.

AD8342

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Performance ........................................................................... 4

Spur Table .......................................................................................... 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

REVISION HISTORY

7/09—Rev. A to Rev. B

Changed RF and LO Frequency Range from 2.4 GHz to

3 GHz Throughout ........................................................................... 1

Changes to General Description Section ...................................... 1

Added Endnote 2 .............................................................................. 4

Added Low Frequency Applications Section .............................. 19

Added Figure 56 and Figure 57..................................................... 20

Changes to the Evaluation Board Section ................................... 21

Added Figure 59 to Figure 62 ........................................................ 22

Updated Outline Dimensions ....................................................... 24

Changes to Ordering Guide .......................................................... 24

1/07—Rev. 0 to Rev. A

Changes to Features .......................................................................... 1

Changes to General Description .................................................... 1

Changes to Table 2 ............................................................................ 4

Replaced the High Frequency Applications Section .................. 18

4/05—Revision 0: Initial Version

Typical Performance Characteristics ..............................................8

Circuit Description......................................................................... 14

AC Interfaces ................................................................................... 15

IF Port .......................................................................................... 16

LO Considerations ..................................................................... 17

High Frequency Applications ................................................... 18

Low Frequency Applications .................................................... 19

Evaluation Board ............................................................................ 21

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

Rev. B | Page 2 of 24

AD8342

SPECIFICATIONS

VS = 5 V, TA = 25°C, fRF = 238 MHz, fLO = 286 MHz, LO power = 0 dBm, ZO = 50 Ω, R
terminated into 100 Ω through a 2:1 ratio balun, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

RF INPUT INTERFACE

Return Loss High-Z input terminated with 100 Ω off-chip resistor 10 dB
Input Impedance

DC Bias Level Internally generated; port must be ac-coupled 2.4 V

OUTPUT INTERFACE

Output Impedance Differential impedance, frequency = 48 MHz 10||0.5 kΩ||pF
DC Bias Voltage Supplied externally 4.75 VS 5.25 V
Power Range Via a 2:1 impedance ratio transformer 13 dBm

LO INTERFACE

Return Loss 10 dB
DC Bias Voltage Internally generated; port must be ac-coupled VS − 1.6 V

POWER-DOWN INTERFACE

PWDN Threshold 3.5 V
PWDN Response Time Device enabled, IF output to 90% of its final level 0.4 μs
Device disabled, supply current <5 mA 4 μs

PWDN Input Bias Current Device enabled −80 μA
Device disabled +100 μA
POWER SUPPLY

Positive Supply Voltage 4.75 5 5.25 V

Quiescent Current

VPDC Supply current for bias cells 5 mA
VPMX, IFOP, IFOM Supply current for mixer, R

VPLO Supply current for LO limiting amplifier 35 mA
Total Quiescent Current VS = 5 V 85 98 113 mA
Power-Down Current Device disabled 500 μA

Frequency = 238 MHz (measured at RFIN with RFCM
ac-grounded)

= 1.82 kΩ 58 mA

BIAS

= 1.82 kΩ, RF termination = 100 Ω, IF

BIAS

1||0.4 kΩ||pF

Rev. B | Page 3 of 24

AD8342

AC PERFORMANCE

VS = 5 V, TA = 25°C, LO power = 0 dBm, ZO = 50 Ω, R
unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

1, 2

1

1

3.0 GHz

3.0 GHz

2.4 GHz

RF Frequency Range
LO Frequency Range
IF Frequency Range
Conversion Gain fRF = 460 MHz, fLO = 550 MHz, fIF = 90 MHz 3.2 dB
f

= 238 MHz, fLO = 286 MHz, fIF = 48 MHz 3.7 dB

RF

SSB Noise Figure fRF = 460 MHz, fLO = 550 MHz, fIF = 90 MHz 12.5 dB
f
Input Third-Order Intercept

Input Second-Order Intercept

= 238 MHz, fLO = 286 MHz, fIF = 48 MHz 12.2 dB

RF

= 460 MHz, f

f

RF1

= 90 MHz, f

f

IF1

= 238 MHz, f

f

RF1

f

= 48 MHz, f

IF1

= 460 MHz, f

f

RF1

= 140 MHz

f

IF2

= 238 MHz, f

f

RF1

f

= 98 MHz

IF2

Input 1 dB Compression Point fRF = 460 MHz, fLO = 550 MHz, fIF = 90 MHz 8.5 dBm
f

= 238 MHz, fLO = 286 MHz, fIF = 48 MHz 8.3 dBm

RF

LO to IF Output Leakage LO power = 0 dBm, fLO = 286 MHz −27 dBc
LO to RF Input Leakage LO power = 0 dBm, fLO = 286 MHz −55 dBc
2× LO to IF Output Leakage

LO power = 0 dBm, f

IF terminated into 100 Ω and measured with a differential probe
RF to IF Output Leakage RF power = −10 dBm, fRF = 238 MHz, fLO = 286 MHz −32 dBc
IF/2 Spurious RF power = −10 dBm, fRF = 238 MHz, fLO = 286 MHz −62 dBc

1

See the section for details. High Frequency Applications

2

See the Low Frequency Applications section for details.

= 1.82 kΩ, RF termination 100 Ω, IF terminated into 100 Ω via a 2:1 ratio balun,

BIAS

= 461 MHz, fLO = 550 MHz,

RF2

= 89 MHz, each RF tone −10 dBm

IF2

= 239 MHz, fLO = 286 MHz,

RF2

= 47 MHz, each RF tone −10 dBm

IF2

= 410 MHz, fLO = 550 MHz, f

RF2

= 188 MHz, fLO = 286 MHz, f

RF2

= 238 MHz, fLO = 286 MHz

RF

= 90 MHz,

IF1

= 48 MHz,

IF1

22.2 dBm

22.7 dBm

50 dBm

44 dBm

−47 dBm

Rev. B | Page 4 of 24

AD8342

SPUR TABLE

VS = 5 V, TA = 25°C, RF and LO power = 0 dBm, fRF = 238 MHz, fLO = 286MHz, ZO = 50 Ω, R
IF terminated into 100 Ω via a 2:1 ratio balun.

Note: Measured using standard test board. Typical noise floor of measurement system = −100 dBm.

Table 3.

m

nf

− mf

RF

0 <−100 −25 −54 −28 −45 −35 −39 −36 −42 −57 −44 −42 −41 −46 −59
1 −32 3.5 −42 −6 −48 −16 −50 −28 −57 −37 −68 −45 −54 −37 −61
2 −52 −47 −51 −49 −54 −56 −56 −62 −62 −66 −71 −80 −80 −67 −79
3 −81 −57 −79 −61 −82 −61 −74 −69 −94 −85 −89 −86 −86 −90 −81
4 −78 −70 −80 −79 −80 −85 −87 −92 −93 −96 −95 <−100 −97 <−100 −95
5 −98 −79 −95 −87 −96 −94 −95 −88 −98 −94 <−100 <−100 <−100 <−100 <−100
6 <−100 <−100 <−100 −99 <−100 −96 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

n

7 <−100 <−100 <−100 <−100 −96 <−100 −98 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 −97 <−100 <−100 <−100 <−100 <−100 <−100
9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 −99 <−100 <−100 <−100
10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 −99 <−100 <−100 <−100 <−100
11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 −96 <−100 −97 <−100 −96 <−100 <−100 <−100
12 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 −99 <−100 −98 <−100 <−100 <−100 <−100
13 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 −97 <−100 −97 −99 <−100 <−100
14 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 −98 −98 <−100 <−100 <−100
15 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

LO

= 1.82 kΩ, RF termination 100 Ω,

BIAS

Rev. B | Page 5 of 24

AD8342

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage, VS 5.5 V
RF Input Level 12 dBm
LO Input Level 12 dBm
PWDN Pin VS + 0.5 V
IFOP, IFOM Bias Voltage 5.5 V
Minimum Resistor from EXRB to COMM 1.8 kΩ
Internal Power Dissipation 650 mW
θJA 77°C/W
Maximum Junction Temperature 135°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 6 of 24

AD8342

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

M

RFIN

VPMX

RFC

COMM

14

13

15

16

PIN 1
INDICATOR

1VPLO

2LOCM

AD8342

3LOIN

TOP VIEW

(Not to Scale)

4COMM

5

6

OMM

IFOM

C

Figure 2. 16-Lead LFCSP

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 VPLO Positive Supply Voltage for the LO Buffer: 4.75 V to 5.25 V.
2 LOCM AC Ground for Limiting LO Amplifier. Internally biased to VS − 1.6 V. AC-couple to ground.
3 LOIN

LO Input. Nominal input level: 0 dBm. Input level range: −10 dBm to +4 dBm (relative to 50 Ω). Internally
biased to V

− 1.6 V. Must be ac-coupled.

S

4, 5, 8, 9, 13 COMM Device Common (DC Ground).
6, 7 IFOM, IFOP Differential IF Outputs (Open Collectors). Each requires dc bias of 5.00 V (nominal).
10 EXRB

Mixer Bias Voltage. Connect resistor from EXRB to ground. Typical value of 1.82 kΩ sets mixer current to

nominal value. Minimum resistor value from EXRB to ground = 1.8 kΩ. Internally biased to 1.17 V.
11 PWDN Connect to Ground for Normal Operation. Connect pin to VS for disable mode.
12 VPDC Positive Supply Voltage for the DC Bias Cell: 4.75 V to 5.25 V.
14 RFCM AC Ground for RF Input. Internally biased to 2.4 V. AC-couple to ground.
15 RFIN RF Input. Internally biased to 2.4 V. Must be ac-coupled.
16 VPMX Positive Supply Voltage for the Mixer: 4.75 V to 5.25 V.

12 VPDC

11 PWDN

10 EXRB

9COMM

8

7

IFOP

COMM

5352-002

Rev. B | Page 7 of 24

AD8342

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, TA = 25°C, RF power = −10 dBm, LO power = 0 dBm, ZO = 50 Ω, R
100 Ω via a 2:1 ratio balun, unless otherwise noted.

6

= 1.82 kΩ, RF termination 100 Ω, IF terminated into

BIAS

6

5

IF = 48MHz

4

GAIN (dB)

3

IF = 10MHz

2

1

50 550100 150 200 250 300 350 400 450 500

IF = 140MHz

IF = 90MHz

RF FREQ UENCY (MHz)

Figure 3. Conversion Gain vs. RF Frequency

5

IF = 48MHz

4

3

IF = 140MHz

GAIN (dB)

2

1

0
–15 –10 –5 0 5

LO LEVEL (dBm)

IF = 90MHz

IF = 10MHz

Figure 4. Gain vs. LO Level, RF Frequency = 238 MHz

5

RF = 238MHz

4

GAIN (dB)

3

2

05352-004

1

5010 100 150 200 250 300 350

IF FREQUENCY (MHz)

RF = 460MHz

05352-005

Figure 6. Conversion Gain vs. IF Frequency

5.0

4.5

4.0

3.5

3.0

2.5

GAIN (dB)

2.0

1.5

1.0

0.5

05352-025

0

4.75 5.254.85 4.95 5.05 5.15

VPOS (V)

05352-026

Figure 7. Gain vs. VPOS, fRF = 238 MHz, fLO = 286 MHz

5.0

4.5

4.0

3.5

3.0

2.5

GAIN (dB)

2.0

1.5

1.0

0.5

0

–40

–200 20406080

TEMPERATURE (°C)

Figure 5. Gain vs. Temperature, fRF = 238 MHz, fLO = 286 MHz

05352-039

Rev. B | Page 8 of 24

50

NORMAL MEAN = 3. 7
STD. DEV. = 0.06

45

40

35

30

25

20

PERCENTAGE

15

10

5

0

3.40

3.45 3. 50 3.55 3.60 3. 65 3.70 3.75 3.80 3. 85

CONVERSIO N GAIN (238MHz)

3.90

Figure 8. Conversion Gain Distribution, fRF = 238 MHz, fLO = 286 MHz

05352-054

AD8342

27

26

25

IF = 48MHz

24

23

22

21

INPUT IP3 (dBm)

20

19

18

17

50

100 150 200 250 300 350 400 450 500

Figure 9. Input IP3 vs. RF Frequency

27

26

25

24

23

22

21

INPUT IP3 (dBm)

20

19

18

17

–15

–13–11–9–7–5 –3–1 1 3

Figure 10. Input IP3 vs. LO Level, f

RF FREQ UENCY (MHz)

IF = 48MHz

IF = 90MHz

IF = 90MHz

IF = 140MHz

IF = 10MHz

140MHz

LO LEVEL (dBm)

= 238 MHz, f

RF1

IF = 10MHz

= 239 MHz

RF2

550

27

26

25

24

23

22

21

INPUT IP3 (dBm)

20

19

18

05352-007

17

10

50 100 150 200 250 300

RF = 238MHz

IF FREQUENCY (MHz)

RF = 460MHz

350

05352-008

Figure 12. Input IP3 vs. IF Frequency

27

26

25

24

23

22

21

INPUT IP3 (dBm)

20

19

18

05352-027

5

17

4.80 4. 85 4.90 4.95 5.00 5.05 5.10 5.15 5.20

4.75 5.25

VPOS (V)

Figure 13. Input IP3 vs. VPOS, fRF = 238 MHz, f

= 239 MHz

RF2

05352-028

LO Frequency = 286 MHz

27

26

25

24

23

22

21

INPUT IP3 (dBm)

20

19

18

17

–40

–200 20406080

TEMPERATURE (°C)

Figure 11. Input IP3 vs. Temperature, f

= 286 MHz

f

LO

= 238 MHz, f

RF1

= 239 MHz,

RF2

05352-032

Rev. B | Page 9 of 24

20

NORMAL MEAN = 22.7
STD. DEV. = 0.41

18

16

14

12

10

8

PERCENTAGE

6

4

2

0

20.6

21.0 21 .4 21.8 22.2 22.6 23.0 23.4 23.8 24.2

INPUT IP3 (238M Hz)

Figure 14. Input IP3 Distribution, fRF = 238 MHz, fLO = 286 MHz

05352-055

AD8342

13

12

11

90MHz

10

9

8

48MHz

7

INPUT P1dB (dBm)

6

5

4

3

50

100 150 200 250 300 350 400 450 500

140MHz

RF FREQ UENCY (MHz)

Figure 15. Input P1dB vs. RF Frequency

10.0

9.5

9.0

IF = 90MHz

8.5

8.0

7.5

7.0

INPUT P1dB (dBm)

6.5

6.0

5.5

5.0
–15

–13–11–9–7–5 –3–1 1 3

IF = 10MHz

IF = 140MHz

IF = 48MHz

LO LEVEL (dBm)

Figure 16. Input P1dB vs. LO Level, fRF = 238 MHz

10MHz

550

05352-013

05352-038

5

10

9

8

7

6

5

4

INPUT P1dB (dBm)

3

2

1

0

10

50 100 150 200 250 300 350

RF = 238MHz

IF FREQUENCY (MHz)

Figure 18. Input P1dB vs. IF Frequency

10

9

8

7

6

5

4

INPUT P1dB (dBm)

3

2

1

0

4.75 5.254.85 4.95 5.05 5.15

VPOS (V)

Figure 19. Input P1dB vs. VPOS, fRF = 238 MHz,

f

= 286 MHz

LO

RF = 460MHz

05352-014

05352-031

10

9

8

7

6

5

4

INPUT P1dB (dBm)

3

2

1

0

–40

–200 20406080

TEMPERATURE (°C)

Figure 17. Input P1dB vs. Temperature, fRF = 238 MHz, fLO = 286 MHz

05352-033

Rev. B | Page 10 of 24

28

NORMAL MEAN = 8. 3

26

STD. DEV. = 0.07

24

22

20

18

16

14

12

PERCENTAGE

10

8

6

4

2

0

8.00

8.05 8.10 8.15 8.20 8.25 8.30 8.35 8.40 8.45 8.50 8.55

IP1dB (238MHz)

Figure 20. Input IP3 Distribution, fRF = 238 MHz, fLO = 286 MHz

8.60

05352-056

AD8342

60

50

40

30

INPUT IP2 (dBm)

20

10

0

100

IF = 10MHz

IF = 140MHz

IF = 48MHz

150 200 250 300 350 400 450 500

RF FREQ UENCY (MHz)

Figure 21. Input IP2 vs. RF Frequency (Second RF = RF − 50 MHz)

60

58

56

54

52

50

48

INPUT IP2 (dBm)

46

44

42

40

–15

–13 –11 –9 –7 –5 –3 –1 1 3

IF = 10MHz

IF = 90MHz

IF = 140MHz

LO LEVEL (dBm)

IF = 48MHz

Figure 22. Input IP2 vs. LO Level, fRF = 238 MHz, f

IF = 90MHz

= 188 MHz

RF2

550

60

RF = 238MHz

50

40

30

INPUT IP2 (dBm)

20

10

05352-010

0

10

50 100 150 200 250 300 350

IF FREQUENCY (MHz)

RF = 460MHz

05352-011

Figure 24. Input IP2 vs. IF Frequency (Second RF = RF − 50 MHz)

60

58

56

54

52

50

48

INPUT IP2 (dBm)

46

44

42

05352-029

5

40

4.75 5.254.85 4.95 5.05 5.15

VPOS (V)

Figure 25. Input IP2 vs. VPOS, f

f

= 188 MHz, fLO = 286 MHz

RF2

= 238 MHz,

RF1

05352-030

14.0

13.5

13.0

12.5

12.0

NOISE FI GURE (dB)

11.5

11.0
50

100 150 200 250 300 350 400 450 500

RF FREQ UENCY (MHz)

Figure 23. Noise Figure vs. RF Frequency, IF Frequency = 48 MHz

05352-016

550

Rev. B | Page 11 of 24

16

14

12

10

8

6

NOISE FI GURE (dB)

4

2

0

10

60 110 160 210 260 310

RF = 238MHz

IF FREQUENCY (MHz)

RF = 460MHz

05352-017

Figure 26. Noise Figure vs. IF Frequency

AD8342

16

15

14

13

NF (dB)

12

11

10

–15

Figure 27. Noise Figure vs. LO Power, fRF = 238 MHz

5.0

4.5

4.0

3.5

3.0

2.5

GAIN (dB)

2.0

1.5

1.0

0.5

0

1.8

Figure 28. Gain vs. R

NF = 140MHz

NF = 10MHz

–13–11–9–7–5–3 –1 1 3

LO POWE R (dBm)

2.0 2.2 2. 4 2.6 2. 8 3.0 3. 2 3.4

R

, RF Frequency = 238 MHz, LO Frequency = 286 MHz

BIAS

BIAS

NF = 90MHz

NF = 48MHz

(kΩ)

30

25

20

15

PERCENTAGE

10

5

05352-018

5

0

11.8

11.9 12.0 12.1 12. 2 12.3 12.4 12.5 12. 6 12. 7

NOISE FIGURE (dB)

NORMAL MEAN = 12. 25
STD. DEV. = 0.14

12.8

05352-023

Figure 30. Noise Figure Distribution, fRF = 238 MHz, fLO = 286 MHz

3.0

BIAS

105

100

95

90

85

SUPPLY CURRENT (mA)

80

75

05352-015

,

30

25

INPUT IP3

20

15

NOISE FI GURE

10

5

NOISE FI GURE AND INPUT IP3 (dBm)

05352-024

0

1.8

2.0 2.2 2.4 2.6 2.8

R

BIAS

CURRENT

(kΩ)

Figure 31. Noise Figure, Input IP3, and Supply Current vs. R

f

= 238 MHz, f

RF1

= 239 MHz, fLO = 286 MHz

RF2

61

59

57

55

53

51

INPUT IP2 (dBm)

49

47

45

1.8

2.0 2.2 2. 4 2.6 2. 8 3.0 3. 2 3.4

Figure 29. Input IP2 vs. R

R

(kΩ)

BIAS

, fRF = 238 MHz (Second RF = RF – 50 MHz),

BIAS

= 286 MHz

f

LO

05352-037

Rev. B | Page 12 of 24

10

9

8

7

6

5

4

INPUT P1dB (dBm)

3

2

1

0

2.0 2.2 2. 4 2.6 2. 8 3.0 3. 2 3.4

1.8

Figure 32. Input P1dB vs. R

R

(kΩ)

BIAS

, fRF = 238 MHz, fLO = 286 MHz

BIAS

05352-036

AD8342

V

0

–10

–20

–30

–40

–50

LEAKAGE (dBc)

–60

–70

–80

–90

50

250 450 650 850

LO FREQUENCY (MHz)

Figure 33. LO to RF Leakage vs. LO Frequency, LO Power = 0 dBm

0

–5

–10

–15

–20

IF = 10MHz

FEEDTHROUGH (dBc)

–25

–30

–35

–40

–45

50

100 150 200 250 300 350 400 450 500

IF = 48MHz

RF FREQUENCY (M Hz)

Figure 34. RF to IF Feedthrough, RF Power = −10 dBm

550

120

100

80

60

40

SUPPLY CURRENT (mA)

20

05352-021

0

–40

–200 20406080

05352-034

TEMPERATURE (°C)

Figure 36. Supply Current vs. Temperature

0

–2

–4

–6

–8

–10

–12

RETURN LOSS ( dB)

–14

–16

05352-035

–18

60

160 260 360 460 560 660 760

860

05352-059

LO FREQUENCY (MHz)

Figure 37. LO Return Loss vs. LO Frequency

0

–5

–10

–15

–20

–25

–30

FEEDTHROUGH (dBc)

–35

–40

–45

50

150 250 350 450 550 650 75 0

LO FREQUENCY (MHz)

Figure 35. LO to IF Feedthrough vs. LO Frequency, LO Power = 0 dBm

05352-020

850

Rev. B | Page 13 of 24

100pF

POS

VPOS

RF IN

100pF0.1µF

VPDC PWDN EXRB COMM

13

1nF

100Ω

1nF

100pF0.1µF

100pF0.1µF

COMM

RFCM

14

RFIN

15

VPMX

16

VPLO LOCM LOIN COMM

1nF

1112

AD8342

21

1nF

10

3

LO IN

1.82kΩ

COMM

COMM

IFOP

IFOM

9

4

8

7

6

5

100pF 0. 1µF

TC2-1T

IF OUT
(50Ω)

VPOS

Figure 38. Characterization Circuit Used to Measure Typical Performance

Characteristics Data

05352-058

AD8342

A

CIRCUIT DESCRIPTION

The AD8342 is an active mixer, optimized for operation within
the input frequency range of near dc to 2.4 GHz. It has a
differential, high impedance RF input that can be terminated or
matched externally. The RF input can be driven either single­ended or differentially. The LO input is a single-ended 50 Ω
input. The IF outputs are differential open-collectors. The mixer
current can be adjusted by the value of an external resistor to
optimize performance for gain, compression, and intermodula­tion, or for low power operation. Figure 39 shows the basic
blocks of the mixer, including the LO buffer, RF voltage-to­current converter, bias cell, and mixing core.

The RF voltage to RF current conversion is done via a resistively
degenerated differential pair. To drive this port single-ended,
the RFCM pin should be ac-grounded while the RFIN pin is ac­coupled to the signal source. The RF inputs can also be driven
differentially. The voltage-to-current converter then drives the
emitters of a four-transistor switching core. This switching core
is driven by an amplified version of the local oscillator signal
connected to the LO input. There are three limiting gain stages
between the external LO signal and the switching core. The first
stage converts the single-ended LO drive to a well-balanced
differential drive. The differential drive then passes through two
more gain stages, which ensures that a limited signal drives the
switching core. This affords the user a lower LO drive
requirement, while maintaining excellent distortion and
compression performance. The output signal of these three LO
gain stages drives the four transistors within the mixer core to
commutate at the rate of the local oscillator frequency. The
output of the mixer core is taken directly from its open
collectors. The open-collector outputs present a high
impedance at the IF frequency. The conversion gain of the
mixer depends directly on the impedance presented to these
open collectors. In characterization, a 100 Ω load was presented
to the part via a 2:1 impedance transformer.

The device also features a power-down function. Application of
a logic low at the PWDN pin allows normal operation. A high
logic level at the PWDN pin shuts down the AD8342. Power
consumption when the part is disabled is less than 10 mW.

The bias for the mixer is set with an external resistor (R

BIAS

)
from the EXRB pin to ground. The value of this resistor directly
affects the dynamic range of the mixer. The external resistor
should not be lower than 1.82 kΩ. Permanent damage to the

part can result if values below 1.8 kΩ are used. This resistor sets
the dc current through the mixer core. The performance effects
of changing this resistor can be seen in the Ty p i ca l Per f o r m anc e
Characteristics section.

L

EXTERN

BIAS

RESISTORVPDC PWDN

BIAS

VPLO

IFOP

IFOM

5352-040

RFIN

RFCM

Figure 39. Simplified Schematic Showing the Key Elements of the AD8342

TO

V

I

LO

INPUT

As shown in Figure 40, the IF output pins, IFOP and IFOM, are
directly connected to the open collectors of the NPN transistors
in the mixer core so the differential and single-ended
impedances looking into this port are relatively high, on the
order of several k. A connection between the supply voltage
and these output pins is required for proper mixer core
operation.

IFOP IFOM

LOIN

RFCMRFIN

COMM

Figure 40. AD8342 Simplified Schematic

05352-041

The AD8342 has three pins for the supply voltage: VPDC,
VPMX, and VPLO. These pins are separated to minimize or
eliminate possible parasitic coupling paths within the AD8342
that could cause spurious signals or reduced interport isolation.
Consequently, each of these pins should be well bypassed and
decoupled as close to the AD8342 as possible.

Rev. B | Page 14 of 24

AD8342

AC INTERFACES

The AD8342 is designed to downconvert radio frequencies (RF)
to lower intermediate frequencies (IF) using a high- or low-side
local oscillator (LO). The LO is injected into the mixer core at
a frequency higher or lower than the desired input RF. The
frequency difference between the LO and the RF, f
side) or f

− fLO (low side), is the intermediate frequency, fIF. In

RF

− fRF (high

LO

addition to the desired RF signal, an RF image is downconverted
to the desired IF frequency. The image frequency is at f

+ f

LO

IF

when driven with a high-side LO. When using a broadband
load, the conversion gain of the AD8342 is nearly constant over
the specified RF input band (see Figure 3).

The AD8342 is designed to operate over a broad frequency
range. It is essential to ac couple RF and LO ports to prevent
dc offsets from skewing the mixer core in an asymmetrical
manner, potentially degrading noise figure and linearity.

The RF input of the AD8342 is high impedance, 1 kΩ across the
frequency range shown in Figure 41. The input capacitance
decreases with frequency due to package parasitics.

2.00 1.00

1.75

1.50 0.75

1.25

1.00 0.50

0.75

RESISTANCE (kΩ)

0.50 0.25

0.25

00

0

100M 200M 300M 400M 500M 600M 700M 800M 900M

FREQUENCY ( Hz)

CAPACITANCE (pF)

1G

05352-042

Figure 41. RF Input Impedance

The matching or termination used at the RF input of the
AD8342 has a direct effect on its dynamic range. The
characterization circuit, as well as the evaluation board, uses a
100 Ω resistor to terminate the RF port. This termination
resistor in shunt with the input stage results in a return loss of
better than −10 dBm (relative to 50 Ω). Tab l e 6 shows gain, IP3,
P1dB, and noise figure for four different input networks. This
data was measured at an RF frequency of 250 MHz and at an
LO frequency of 300 MHz.

Table 6. Dynamic Performance for Various Input Networks

Input
Network

50 Ω
Shunt

100 Ω
Shunt

500 Ω
Shunt

Matched
(Figure 42)

Gain (dB) 0.66 3.5 5.3 9.3
IIP3 (dBm) 25.4 22.9 20. 6 18.5
P1dB (dBm) 10.8 8.4 6.3 2.3
NF (dB) 14 12.5 10.2 10.5

The RF port can also be matched using an LC circuit, as shown
in Figure 42.

50Ω

100nH

3.6pF

1kΩ

(1000 + j0) Ω

Z
f

Z

L

O

MAIN

= 50Ω

= 250MHz

5352-043

Figure 42. Matching Circuit

Impedance transformations of greater than 10:1 result in a
higher Q circuit and thus a narrow RF input bandwidth. A 1 kΩ
resistor is placed across the RF input of the device in parallel
with the device internal input impedance, creating a 500 Ω load.
This impedance is matched to as close as possible to 50 Ω for
the source, with standard components using a shunt C, series L
matching circuit (see Figure 43).

50

25

10

POINT 1(1000 + j0) Ω
POINT 2(500 + j0) Ω
POINT 3(55.6 – j157.2) Ω
POINT 4(55.6 – j0.1) Ω

Figure 43. LC Matching Example

Q = 3

4

10

100

200

500

12

500

200

100

3

50

25

05352-044

Rev. B | Page 15 of 24

AD8342

IF PORT

The IF port comprises open-collector differential outputs. The
NPN open collectors can be modeled as current sources that are
shunted with resistances of ~10 kΩ in parallel with capacitances
of ~1 pF.

The specified performance numbers for the AD8342 were
measured with 100 Ω differential terminations. However,
different load impedances can be used where circumstances
dictate. In general, lower load impedances result in lower
conversion gain and lower output P1dB. Higher load imped­ances result in higher conversion gain for small signals, but
lower IP3 values for both input and output.

If the IF signal is to be delivered to a remote load, more than a
few millimeters away at high output frequencies, avoid
unintended parasitic effects due to the intervening PCB traces.
One approach is to use an impedance transforming network or
transformer located close to the AD8342. If very wideband
output is desired, a nearby buffer amplifier may be a better
choice, especially if IF response to dc is required. An example of
such a circuit is presented in Figure 45, in which the AD8351
differential amplifier is used to drive a pair of 75 Ω transmission
lines. The gain of the buffer can be independently set by
appropriate choice of the value for the gain resistor, R

50

45

40

35

30

25

20

RESISTANCE (kΩ)

15

10

5

0

0

100M 200M 300M 400M 500M 600M 700M 800M 900M

FREQUENCY ( Hz)

Figure 44. IF Port Impedance

+V

S

AD8342

COMM

8

RFC

7

IFOP

IFOM

COMM

6

5

R

+V

S

100Ω R

FC

Z

L

= 100Ω

Figure 45. AD8351 Used as Transmission Line Driver and Impedance Buffer

+V

S

+

AD8351

G

–

Tx LINE ZO = 75Ω

Tx LINE ZO = 75Ω

.

G

0.5

0.4

0.3

0.2

0.1

CAPACITANCE (pF)

0

–0.1

–0.2

1G

05352-045

Z

L

05352-046

The high input impedance of the AD8351 allows for a shunt
differential termination to provide the desired 100 Ω load to the
AD8342 IF output port.

It is necessary to bias the open-collector outputs using one of
the schemes presented in Figure 47 and Figure 48. Figure 47
illustrates the application of a center-tapped impedance
transformer. The turns ratio of the transformer should be
selected to provide the desired impedance transformation. In
the case of a 50 Ω load impedance, a 2-to-1 impedance ratio
transformer should be used to transform the 50 Ω load into a
100 Ω differential load at the IF output pins. Figure 48
illustrates a differential IF interface where pull-up choke
inductors are used to bias the open-collector outputs. The
shunting impedance of the choke inductors used to couple dc
current into the mixer core should be large enough at the IF
operating frequency so it does not load down the output current
before reaching the intended load. Additionally, the dc current
handling capability of the selected choke inductors needs to be
at least 45 mA. The self-resonant frequency of the selected
choke should be higher than the intended IF frequency. A
variety of suitable choke inductors is commercially available
from manufacturers such as Murata and Coilcraft®. Figure 46
shows the loading effects when using nonideal inductors. An
impedance transforming network may be required to transform
the final load impedance to 100 Ω at the IF outputs. There are
several good reference books that explain general impedance
matching procedures, including:

• Chris Bowick, RF Circuit Design, Newnes, Reprint Edition,

1997.

• David M. Pozar, Microwave Engineering, Wiley,

3rd Edition, 2004.

• Guillermo Gonzalez, Microwave Transistor Amplifiers:

Analysis and Design, Prentice Hall, Second Edition, 1996.

90

120

150

210

240

270

Figure 46. IF Port Loading Effects Due to Finite Q Pull-Up Inductors

(Murata BLM18HD601SN1D Chokes)

60

50MHz

500MHz

500MHz

300

30

330

REAL
CHOKES

0180

50MHz

IDEAL
CHOKES

05352-049

Rev. B | Page 16 of 24

AD8342

+V

S

AD8342

8

COMM

IFOP

IFOM

COMM

7

6

5

2:1

ZL = 100Ω

IF OUT

= 50Ω

Z

O

05352-047

Figure 47. Biasing the IF Port Open-Collector Outputs

Using a Center-Tapped Impedance Transformer

+V

S

AD8342

COMM

8

IFOP

IFOM

COMM

RFC

7

6

RFC

5

+V

S

Z

L

= 100Ω

IF

OUT+

IF OUT–

IMPEDANCE

TRANSFORMING

NETWORK

Z

L

05352-048

Figure 48. Biasing the IF Port Open-Collector Outputs

Using Pull-Up Choke Inductors

The AD8342 is optimized for driving a 100 Ω load. Although
the device is capable of driving a wide variety of loads, to
maintain optimum distortion and noise performance, it is
advised that the presented load at the IF outputs is close to
100 Ω. The linear differential voltage conversion gain of the
mixer can be modeled as

V

LOAD

RGA ×=

m

where:

g

1

G

m

π=1

R

is the single-ended load impedance.

LOAD

g

is the transistor transconductance and is equal to 1810/R

m

R

= 15 Ω.

e

The external R

m

×

+

Rg

em

resistor is used to control the power

BIAS

BIAS

dissipation and dynamic range of the AD8342. Because the
AD8342 has internal resistive degeneration, the conversion gain
is primarily determined by the load impedance and the on-chip
degeneration resistors. Figure 49 shows how gain varies with IF
load. The external R

resistor has only a small effect. The

BIAS

most direct way to affect conversion gain is by varying the load
impedance. Small loads result in lower gains while larger loads
increase the conversion gain. If the IF load impedance is too
large, it causes a decrease in linearity (P1dB, IP3). In order to
maintain positive conversion gain and preserve SFDR
performance, the differential load presented at the IF port
should remain in the range of about 100 Ω to 250 Ω.

30

25

20

15

10

VOLTAGE GAIN (dB)

5

0

10

100

IF LOAD (Ω)

MODELED

MEASURED

1000

05352-057

Figure 49. Voltage Conversion Gain vs. IF Loading

LO CONSIDERATIONS

The LOIN port provides a 50 Ω load impedance with common­mode decoupling on LOCM. Again, common-grade ceramic
capacitors provide sufficient signal coupling and bypassing of
the LO interface.

The LO signal needs to have adequate phase noise characteristics
and low second-harmonic content to prevent degradation of the
noise figure performance of the AD8342. An LO plagued with
poor phase noise can result in reciprocal mixing, a mechanism
that causes spectral spreading of the downconverted signal,
limiting the sensitivity of the mixer at frequencies adjacent to
any large input signals. The internal LO buffer provides enough
gain to hard-limit the input LO and provide fast switching of
the mixer core. Odd harmonic content present on the LO drive
signal should not impact mixer performance; however, even­order harmonics cause the mixer core to commutate in an
unbalanced manner, potentially degrading noise performance.
Simple lumped element low-pass filtering can be applied to help
reject the harmonic content of a given local oscillator, as shown

.

in Figure 50. The filter depicted is a common 3-pole Chebyshev,
designed to maintain a 1-to-1 source-to-load impedance ratio
with no more than 0.5 dB of ripple in the pass band. Other filter
structures can be effective as long as the second harmonic of the
LO is filtered to negligible levels, for example, ~30 dB below the
fundamental.

AD8342

LOIN3COMM

LOCM

L2

1.28R

2π

2

L

L

C3 =

f

c

R

S

LO

SOURCE

C1 =

f

- FILTER CUTOFF FREQUENCY

C

1.864

2π

f

R

c

C1 C3

FOR RS= R

L2 =

L

Figure 50. Using a Low-Pass Filter to Reduce LO Second Harmonic

4

R

L

1.834

f

R

2π

c

L

05352-050

Rev. B | Page 17 of 24

AD8342

–

HIGH FREQUENCY APPLICATIONS

The AD8342 is a broadband mixer capable of both up and
down conversion. Unlike other mixers that rely on on-chip
reactive circuitry to optimize performance over a specific band,
the AD8342 is a versatile general-purpose device that can be
used from arbitrarily low frequencies to several GHz. In
general, the following considerations help to ensure optimum
performance:

• Minimize ac loading impedance of IF port bias network.

• Maximize power transfer to the desired ac load.

• For maximum conversion gain and the lowest noise

performance, reactively match the input as described in the
IF Port section.

• For maximum input compression point and input intercept

points, resistively terminate the input as described in the
IF Port section.

As an example, Figure 51 shows the AD8342 as an up­converting mixer for a W-CDMA single-carrier transmitter
design. For this application, it was desirable to achieve −65 dBc
adjacent channel power ratio (ACPR) at a −13 dBm output
power level. The ACPR is a measure of both distortion and
noise carried into an adjacent frequency channel due to the
finite intercept points and noise figure of an active device.

100pF

170MHz

INPUT

100nH

4.7pF

VPOS

1nF

VPOS

100pF0.1pF

12

VPDC PWDN EXRB COMM

13

COMM

1nF

14

RFCM

499Ω

15

RFIN

16

100pF0.1µF

VPMX

VPLO LOCM LOIN COMM

1

100pF

Figure 51. W-CDMA Tx Up-Conversion Application Circuit

Because a W-CDMA channel encompasses a bandwidth of
almost 5 MHz, it is necessary to keep the Q of the matching
circuit low enough so that phase and magnitude variations are
below an acceptable level over the 5 MHz band. It is possible
to use purely reactive matching to transform a 50 Ω source
to match the raw ~1 kΩ input impedance of the AD8342.
However, the L and C component variations could present
production concerns due to the sensitivity of the match. For
this application, it is advantageous to shunt down the ~1 kΩ

11

AD8342

2

1nF

1970MHz

OSC

10

3

1.82kΩ

COMM

COMM

1nF

IFOP

IFOM

VPOS

9

4

100pF

8

34nH

VPOS

34nH

100pF

ETC1-1-13

1nF

1nF

2140MHz OUT

7

6

5

05352-052

input impedance using an external shunt termination resistor
to allow for a lower Q reactive matching network. The input is
terminated across the RFIN and RFCM pins using a 499 Ω
termination. The termination should be as close to the device as
possible to minimize standing wave concerns. The RFCM is
bypassed to ground using a 1 nF capacitor. A dc blocking
capacitor of 1 nF is used to isolate the dc input voltage present
on the RFIN pin from the source. A step-up impedance
transformation is realized using a series L shunt C reactive
network. The actual values used need to accommodate for the
series L and stray C parasitics of the connecting transmission
line segments. When using the customer evaluation board with
the components specified in Figure 51, the return loss over a
5 MHz band centered at 170 MHz was better than 10 dB.

External pull-up choke inductors are used to feed dc bias into
the open-collector outputs. It is desirable to select pull-up choke
inductors that present high loading reactance at the output
frequency. Coilcraft 0302CS series inductors were selected due
to their very high self-resonant frequency and Q. A 1:1 balun
was ac-coupled to the output to convert the differential output
to a single-ended signal and present the output with a 50-Ω ac
loading impedance.

The performance of the circuit is shown in Figure 52. The
average ACPR of the adjacent and alternate channels is
presented vs. output power. The circuit provides a 65 dBc ACPR
at −13 dBm output power. The optimum ACPR power level can
be shifted to the right or left by adjusting the output loading
and the loss of the input match.

60

–62

–64

–66

ACPR (dBc)

–68

–70

–25

–20 –15 –10 –5

OUTPUT PO WER (dBm)

Figure 52. Single Carrier W-CDMA ACPR Performance of Tx

Up-Conversion Circuit (Test Model 1_64)

ADJACENT
CHANNELS

ALTERNATE
CHANNELS

05352-053

0

Rev. B | Page 18 of 24

AD8342

The available frequency range of the AD8342 is extremely
broad. With adequate care, any of the mixer ports can be
optimized for extremely low frequencies, or up to several GHz.
The standard evaluation board is populated for broadband
performance from a few MHz to ~1GHz. The input match of
the RF port degrades at higher frequencies when using the
standard eval board. The broadband frequency range can be
extended by minimizing parasitics between the input
terminating resistor, R5, and the input pins.

100pF

VPOS

1nF

RF IN

VPOS

NOTES

1. INPUT TERMINATION PLACEDAS CLOSE AS POSSIBLETO RFINAND RFCM INPUTS.

0.1µF

1000pF0.1µF

VPDC PWDN EXRB COMM

13

1nF

100Ω

1000pF0.1µF

COMM

14

RFCM

15

RFIN

16

VPMX

VPLO LOCM LOIN COMM

1000pF

1112

AD8342

21

1nF

LO IN

10

3

1.82kΩ

1nF

COMM

IFOP

IFOM

COMM

9

8

7

6

5

4

100pF

TC2-1T

0.1µF

IF OUT
(190MHz)

VPOS

Figure 53. Modified Evaluation Board Schematic for Broadband

Down-Conversion Performance up to 3 GHz

The measurements in Figure 54 were made using the modified
evaluation board as configured in Figure 53.

30

OIP3

25

20

15

10

NF, GAIN, OIP3, IP1dB (dB, dBm)

Figure 54. Input OIP3, IP1dB, Gain and NF vs. RF Frequency for a 190 MHz IF

NF

IP1dB

GAIN

5

0

500 3000

1000 1500 2000 2500

RF FREQUENCY (M Hz)

Using a Low-Side LO.

05352-061

05352-060

The broadband frequency capabilities of the AD8342 makes it
an attractive solution for a variety of applications, including
cellular, CATV, point-to-point radio links, and test equipment.
As an example, the circuit depicted in Figure 53 can easily be
applied as a feedback mixer in a predistortion receiver design.
The performance depicted in Figure 55 was measured using a
160 MHz IF. Here, four W-CDMA carriers with high PAR are
down-converted for IF sampling so that transmit path
nonlinearities can be measured and minimized using digital
predistortion techniques.

RBW 30kHz
VBW 300kHz

REF –22.6dBm

–30

POS –22.564d Bm

–40

–50

–60

–70

–80

–90

–100

–110

–120

CENTER 160MHz SPAN 40.6MHz

STANDARD: W-CDMA 3GPP FWD

Tx CHANNELS
CH1 (REF) –20.65dBm
CH2 –20.29dBm
CH3 –20.25dBm
CH4 –20.29dBm

TOTAL –14.35d Bm

ATT 5dB

SWT 4s

4.06MHz

ADJACENT CHANNE L
LOWER –61.36d B
UPPER –60.84dB

ALTERNATE CHANNEL
LOWER –61.94d B
UPPER –61.72dB

05352-062

Figure 55. ACPR Performance for Multiple W-CDMA Carriers Being Down-

Converted from 2140 MHz to 160 MHz for Distortion Analysis

LOW FREQUENCY APPLICATIONS

The AD8342 can be used in extremely low frequency appli­cations. Figure 56 depicts the configuration with necessary
modifications at IF ports. Two 10  resistors are used to bias
the open collector outputs, and the output coupling capacitors
need to be large enough to allow intended low frequency
operation. Figure 57 illustrates the gain performance at fixed
IF of 10 kHz and 1 MHz for broadband down-conversion using
low-side LO.

Rev. B | Page 19 of 24

AD8342

V

+5

1N4148

0.1µF

1nF

RF IN

1nF

0.1µF 100pF

0.1µF 100pF

100Ω

100pF

COMM

RFCM

RFIN

VPMX

VPDC

12 11 10 9

13

14

15

16

1 2 3 4

VPLO

1nF 1nF

PWDN

EXRB

AD8342

LOIN

LOCM

LO IN

100pF

1.82kΩ

COMM

8

IFOP

7

IFOM

6

COMM

5

+5V

+5V

10Ω

10µF

10µF

10Ω

BALANCED
OUTPUT

COMM

COMM

Figure 56. Modified Evaluation Board Schematic for Down-Converting

Broadband RF to Low IF Frequencies.

20

15

10

IF = 1 MHz

CONVERSION GAIN (dB)

IF = 10 kHz

5

0

0.7 0.9 1.1 1. 3 1.5 1.7 1. 9 2.1 2.3 2. 5 2.7
RF FREQUENCY ( GHz)

05352-102

Figure 57. Gain Performance for 1 MHz and 10 kHz IF of Broadband Down-

Conversion

05352-101

Rev. B | Page 20 of 24

AD8342

EVALUATION BOARD

An evaluation board is available for the AD8342. The evaluation board is configured for single-ended signaling at the IF output port via a
balun transformer. The schematic for the evaluation board is presented in Figure 58. The representations of the board layout are included
in Figure 59 through Figure 62.

R8

10kΩ

R9
0Ω

10

11

PWDN

EXRB

DUT

LOCM LOIN

3

2

1

C7

INLO

C8
1000pF

Figure 58. Evaluation Board

1.82kΩ

9

COMM

COMM

IFOM

COMM

COMM

4

R6

IFOP

C11

100pF

8

7

6

5

OPEN

Z2
OPEN

R10

0Ω

Z1
OPEN

R12

OPEN

Z3

R11

0Ω

Z4

OPEN

R16

0Ω

C10

100pF

R15
0Ω

R3

OPEN

T1

34
2
16

TC2-1T

R4
OPEN

C9

0.1µF

IF_OUT+

100Ω TRACES,
NO GROUND PLANE

IF_OUT–

VPOS

05352-003

RF_IN

VPOS

PWDN

L1
0Ω

C14

OPEN

VPOSGND

C2

0.1µF

C5

0.1µF

PWDN

VPOS

0.1µF

W1

C12

50Ω

TRACE

R5
100Ω

R1

0Ω

R2

0Ω

R7

0Ω

1000pF

1000pF

C4
1000pF

C6
1000pF

C13
100pF

12

VPDC

13

COMM

C1

14

RFCM

C3

15

RFIN

16

VPMX

VPLO

1000pF

Table 7. Evaluation Board Configuration Options

Component Description Default Conditions

R1, R2, R7,
C2, C4, C5, C6, C9,
C10, C12, C13

Supply decoupling. Shorts or power supply decoupling resistors and filter
capacitors.

R1, R2, R7 = 0 Ω
C4, C6 = 1000 pF
C10, C13 = 100 pF

C2, C5, C9, C12 = 0.1 μF
R3, R4 Options for single-ended IF output circuit. R3, R4 = Open
R6, C11

resistor that sets the bias current for the mixer core. The capacitor

R

BIAS

provides ac bypass for R6.

R6 = 1.82 kΩ

C11 = 100 pF
R8 Pull down for the PWDN pin. R8 = 10 kΩ
R9 Link to PWDN pin. R9 = 0 Ω
C3, R5, C14, L1

RF input. C3 provides dc block for RF input. R5 provides a resistive input
termination. C16 and L1 are provided for reactive matching of the input.

C3 = 1000 pF

R5 = 100 Ω

C14 = Open

L1 = 0 Ω
C1

RF common ac coupling. Provides dc block for RF input common

C1 = 1000 pF

connection.
C8 LO input ac coupling. Provides dc block for the LO input. C8 = 1000 pF
C7

LO common ac coupling. Provides dc block for LO input common

C7 = 1000 pF

connection.
W1

Power down. The part is on when the PWDN is connected to ground via a

10 kΩ resistor. The part is disabled when PWDN is connected to the positive

) via W1.

S

) to the IF output pins.

S

T1 = TC2-1T, 2:1 (Mini-Circuits®)
R12 = Open
R10, R11, R15, R16 = 0 Ω
Z3, Z4 = Open

T1, R10, R11, R12,
R15, R16, Z3, Z4,
Z1, Z2,

supply (V

IF output interface. T1 converts a differential high impedance IF output to

single-ended. When loaded with 50 Ω, this balun presents a 100 Ω load to

the mixers collectors. The center tap of the primary is used to supply the

bias voltage (V

Z1, Z2 = Open

Rev. B | Page 21 of 24

AD8342

Figure 59. Evaluation Board Artwork Top

05352-104

05352-105

Figure 60. Evaluation Board Artwork Internal 1

Rev. B | Page 22 of 24

AD8342

Figure 61. Evaluation Board Artwork Internal 2

05352-106

05352-107

Figure 62. Evaluation Board Artwork Bottom

Rev. B | Page 23 of 24

AD8342

OUTLINE DIMENSIONS

0.50

PIN 1

INDICATOR

0.90

0.85

0.80

SEATING

PLANE

12° MAX

0.45

0.50

BSC

1.50 REF

0.60 MAX

BOTTOM VIE W

13

12

9

8

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DES CRIPTIONS
SECTION O F THIS DAT A SHEET.

3.00

BSC SQ

TOP

VIEW

0.30

0.23

0.18

2.75

BSC SQ

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

*

COMPLIANT

EXCEPT FO R EXPOSED PAD DI MENSION.

TO

JEDEC STANDARDS MO-220-VEED-2

Figure 63. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

3 mm x 3 mm Body, Very Thin Quad

(CP-16-3)

Dimensions in millimeters

EXPOSED

PAD

0.40

0.30

16

1

4

5

P

N

I

N

I

D

*

1.65

1.50 SQ

1.35

0.25 MIN

1

A

R

O

T

C

I

071708-A

ORDERING GUIDE

Ordering

Model Temperature Range Package Description Package Option Branding

AD8342ACPZ-REEL71 −40°C to +85°C

16-Lead Lead Frame Chip Scale Package

CP-16-3 Q01 1,500

[LFCSP_VQ], Reel

AD8342ACPZ-R21 −40°C to +85°C

16-Lead Lead Frame Chip Scale Package

CP-16-3 Q01 250

[LFCSP_VQ], Reel

AD8342ACPZ-WP1 −40°C to +85°C

16-Lead Lead Frame Chip Scale Package

CP-16-3 Q01 50

[LFCSP_VQ], Waffle Pack

AD8342-EVALZ1 Evaluation Board 1

1

Z = RoHS Compliant Part.

Quantity

©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05352-0-7/09(B)

Rev. B | Page 24 of 24