Analog Devices AD8327ARU-REEL, AD8327ARU, AD8327 Datasheet

5 V CATV Line Driver Coarse Step

FUNDAMENTAL FREQUENCY – MHz

–50

–60

–75

–65

–55

5 152535455565

DISTORTION – dBc

–70

HD3

HD2

V

OUT

= 60dBmV @ MAX GAIN

a

FEATURES
Supports DOCSIS Standard for Reverse Path

Transmission

Gain Programmable in 6.02 dB Steps over a 48.16 dB

Range

Low Distortion at 60 dBmV Output

–63 dBc SFDR at 21 MHz
–57 dBc SFDR at 42 MHz

Output Noise Level

–47 dBmV in 160 kHz

Maintains 75 ⍀ Output Impedance

Transmit Enable and Transmit Disable Modes
Upper Bandwidth: 160 MHz (Full Gain Range)
5 V Supply Operation
Supports SPI Interfaces

APPLICATIONS
Gain-Programmable Line Driver

DOCSIS High-Speed Data Modems

Interactive Cable Set-Top Boxes

PC Plug-in Cable Modems
General-Purpose Digitally Controlled Variable Gain Block

V

IN+

V

IN–

ZIN (SINGLE) = 800⍀
Z

(DIFF) = 1.6k⍀

IN

Output Power Control

FUNCTIONAL BLOCK DIAGRAM

VCC (5 PINS)

R1

DIFF OR
SINGLE
INPUT
AMP

R2

VERNIER

DATA CLK GND (5 PINS)

DATEN

ATTENUATION

CORE

8

DECODE

8

DATA LATCH

8

SHIFT

REGISTER

AD8327

BYP

AD8327

POWER

AMP

= 75⍀

Z

OUT

POWER-DOWN

LOGIC

TXEN

SLEEP

V

OUT

CXR

GENERAL DESCRIPTION

The AD8327 is a low-cost, digitally controlled, variable gain
amplifier optimized for coaxial line driving applications such as
cable modems that are designed to the MCNS-DOCSIS
upstream standard. An 8-bit serial word determines the desired
output gain over a 48.16 dB range resulting in gain changes of

6.02 dB/major carry.

The AD8327 comprises a digitally controlled variable attenuator
of 0 dB to –48.16 dB, which is preceded by a low noise, fixed
gain buffer and followed by a low distortion, high power amplifier.
The AD8327 accepts a differential or single-ended input
signal. The output is specified for driving a 75 Ω load, such
as coaxial cable.

Distortion performance of –63 dBc is achieved with an output
level up to 60 dBmV at 21 MHz bandwidth. A key performance
and cost advantage of the AD8327 results from the ability to
maintain a constant 75 Ω output impedance during Transmit
Enable and Transmit Disable conditions. In addition, this
device has a sleep mode function that reduces the quiescent
current to 5 mA.

The AD8327 is packaged in a low-cost 20-lead TSSOP, operates
from a single 5 V supply, and has an operational temperature
range of –40°C to +85°C.

Figure 1. Harmonic Distortion vs. Frequency

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD8327–SPECIFICATIONS

(TA = 25ⴗC, VS = 5 V, RL = 75 ⍀, V

IN(DIFFERENTIAL)

= 30 dBmV)

Parameter Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Specified AC Voltage P

= 60 dBmV, Max Gain 30 dBmV

OUT

Noise Figure Max Gain, f = 10 MHz 13.2 dB
Input Resistance Single-Ended Input 800 Ω

Differential Input 1600 Ω

Input Capacitance 2pF

GAIN CONTROL INTERFACE

Gain Range 47.16 48.16 49.16 dB
Maximum Gain Gain Code = 10000000 (128 Decimal) 29 30 31 dB
Minimum Gain Gain Code = 00000000 (0 Decimal) –19.16 –18.16 –17.16 dB
Gain Scaling Factor 6.02 dB/Major

Carry

OUTPUT CHARACTERISTICS

Bandwidth (–3 dB) All Gain Codes 160 MHz
Bandwidth Roll-Off f = 65 MHz 0.4 dB
Bandwidth Peaking All Gain Codes 0 dB
Output Noise Spectral Density Max Gain, f = 10 MHz –32 dBmV in

160 kHz

Min Gain, f = 10 MHz –47 dBmV in

160 kHz
Transmit Disable Mode (TXEN = 0), –66 dBmV in
f = 10 MHz 160 kHz

1 dB Compression Point Max Gain, f = 10 MHz 14.8 dBm
Differential Output Impedance Transmit Enable (TXEN = 1) and

Transmit Disable Mode (TXEN = 0) 75 ± 20% Ω

OVERALL PERFORMANCE

Second Order Harmonic Distortion f = 21 MHz, V

f = 42 MHz, V
f = 65 MHz, V

Third Order Harmonic Distortion f = 21 MHz, V

f = 42 MHz, V
f = 65 MHz, V

= 60 dBmV @ Max Gain –63 dBc

OUT

= 60 dBmV @ Max Gain –61 dBc

OUT

= 60 dBmV @ Max Gain –54 dBc

OUT

= 60 dBmV @ Max Gain –63 dBc

OUT

= 60 dBmV @ Max Gain –57 dBc

OUT

= 60 dBmV @ Max Gain –57 dBc

OUT

Adjacent Channel Power Adjacent Channel Width = Transmit Channel –62 dBc

Width = 160 K

SYM/SEC

Gain Linearity Error f = 10 MHz, Code to Code ±0.25 dB
Output Settling

Due to Gain Change (T
Due to Input Change Max Gain, V

) Min to Max Gain 60 ns

GS

= 30 dBmV 30 ns

IN

Isolation in Transmit Disable Mode Max Gain, TXEN = 0 V, f = 42 MHz, –52 dBc

VIN = 30 dBmV

POWER CONTROL

Transmit Enable Settling Time (T
Transmit Disable Settling Time (T
Transmit Enable Settling Time (T
Transmit Disable Settling Time (T
Between Burst Transients

Ramp Setting

2

2

)1Max Gain, VIN = 0 V 300 ns

ON

)1Max Gain, VIN = 0 V 40 ns

OFF

)2Max Gain, VIN = 0 V 2 µs

ON

)2Max Gain, VIN = 0 V 1.7 µs

OFF

Equivalent Output = 31 dBmV 3 mV p-p
Equivalent Output = 60 dBmV 25 mV p-p

2 µs

POWER SUPPLY

Operating Range 4.75 5 5.25 V
Quiescent Current Transmit Enable Mode (TXEN = 1) @ Dec 128 75 105 135 mA

Transmit Enable Mode (TXEN = 1) @ Dec 0 40 60 80 mA
Transmit Disable Mode @ All Gain Codes 10 15 20 mA
Sleep Mode @ All Gain Codes 3 5 7 mA

OPERATING TEMPERATURE –40 +85 °C
RANGE

NOTES

1

For Transmit Enable or Transmit Disable transitions using a 0 pF capacitor (at CXR pin) to ground.

2

For Transmit Enable or Transmit Disable transitions using a 100 pF capacitor (at CXR pin) to ground.

Specifications subject to change without notice.

–2–

REV. 0

AD8327

LOGIC INPUTS (TTL/CMOS-Compatible Logic)

(DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 5 V: Full Temperature Range)

Parameter Min Typ Max Unit

Logic “1” Voltage 2.1 5.0 V
Logic “0” Voltage 0 0.8 V
Logic “1” Current (V
Logic “0” Current (V
Logic “1” Current (V
Logic “0” Current (V
Logic “1” Current (V
Logic “0” Current (V

TIMING REQUIREMENTS

= 5 V) CLK, SDATA, DATEN 020nA

INH

= 0 V) CLK, SDATA, DATEN –600 –100 nA

INL

= 5 V) TXEN 50 190 µA

INH

= 0 V) TXEN –250 –30 µA

INL

= 5 V) SLEEP 50 190 µA

INH

= 0 V) SLEEP –250 –30 µA

INL

(Full Temperature Range, VCC = 5 V, tR = tF = 4 ns, f

= 8 MHz unless otherwise noted.)

CLK

Parameter Min Typ Max Unit

Clock Pulsewidth (t
Clock Period (t
Setup Time SDATA vs. Clock (t
Setup Time DATEN vs. Clock (t
Hold Time SDATA vs. Clock (t
Hold Time DATEN vs. Clock (t

) 16.0 ns

WH

) 32.0 ns

C

) 5.0 ns

DS

) 15.0 ns

ES

) 5.0 ns

DH

) 3.0 ns

EH

Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF)10ns

t

DS

SDATA

CLK

DATEN

TXEN

ANALOG

OUTPUT

VALID DATA WORD G1

MSB. . . .LSB

t

ES

8 CLOCK

CYCLES

SIGNAL AMPLITUDE (p-p)

Figure 2. Serial Interface Timing

SDATA

MSB MSB-1

t

C

t

WH

t

EH

GAIN TRANSFER (G1)

t

GS

VALID DATA BIT

t

DS

VALID DATA WORD G2

t

OFF

t

DH

GAIN TRANSFER (G2)

t

MSB-2

ON

REV. 0

CLK

Figure 3. SDATA Timing

–3–

AD8327

TOP VIEW

(Not to Scale)

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

9

10

AD8327

DATEN

V

IN–

V

IN+

GND

V

CC

SLEEP

BYP

V

CC

V

CC

GND

SDATA

CLK

GND

V

CC

TXEN

V

CC

V

OUT

GND

GND

CXR

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage +V

S

PIN CONFIGURATION

Pins 4, 6, 11, 12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

Input Voltages

Pins 17, 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V

Pins 1, 2, 3, 19, 20 . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V

Internal Power Dissipation

TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 mW

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 SDATA Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the

internal register with the MSB (Most Significant Bit) first.

2 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-

slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to
the slave. This requires the input serial data word to be valid at or before this clock transition.

3 TXEN Logic “0” disables transmission. Logic “1” enables transmission.

4, 6, 11, 12, 16 V

CC

Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin.

5, 8, 9, 13, 15 GND Common External Ground Reference

7 CXR Transmit Enable/Disable Timing Capacitor. This pin is decoupled with a 100 pF capacitor to GND.

10 V

OUT

Output Signal

14 BYP Internal Bypass. This pin must be externally ac-coupled (0.1 µF capacitor).

17 V

IN+

Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF
capacitor.

18 V

IN–

19 SLEEP Low Power Sleep Mode. Logic 0 enables Sleep mode, where Z

Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor.

goes to 200 Ω and supply

OUT

current is reduced to 5 mA. Logic 1 enables normal operation.

20 DATEN Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic

0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta­neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch
(holds the previous gain state) and simultaneously enables the register for serial data load.

ORDERING GUIDE

Model Temperature Range Package Description ␪

JA

Package Option

AD8327ARU –40°C to +85°C 20-Lead TSSOP 85°C/W* RU-20
AD8327ARU-REEL –40°C to +85°C 20-Lead TSSOP 85°C/W* RU-20
AD8327-EVAL Evaluation Board

*Thermal Resistance measured on SEMI standard 4-layer board.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8327 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–4–

REV. 0

Typical Performance Characteristics–AD8327

FREQUENCY – MHz

0

–10

–90

1

100010

ISOLATION – dBc

100

–20

–30

–70

–40

–50

–60

–80

TXEN = 0
VIN = 30dBmV

MAX GAIN

MIN GAIN

FREQUENCY – MHz

100

10

1000

1

10

–20

–30

0

–10

20

30

40

GAIN – dB

128D

64D

32D

01D

16D

08D

04D

02D

00D

FREQUENCY – MHz

90

85

80

75

70

65

60

55

1

100

10

IMPEDANCE – ⍀

TXEN = 0

TXEN = 1

+V

S

10␮F

0.1␮F

0.1␮F

V

165⍀

IN

0.1␮F

0.1␮F

V

IN–

AD8327

V

IN+

BYP CXR

V

CC

100pF

GND

0.1␮F

75⍀

REV. 0

TPC 1. Basic Test Circuit

0.6

0.5

0.4

0.3

0.2

0.1

0

GAIN ERROR – dB

–0.1

–0.2

–0.3

0 16 48 80 96 112 12832 64

f = 65MHz

f = 42MHz

f = 10MHz

f = 5MHz

GAIN CONTROL – Decimal Code

TPC 2. Gain Error vs. Gain Control

160

155

150

145

140

135

IMPEDANCE – ⍀

130

125

120

115

0.1␮F

165⍀

V

IN

0.1␮F

1

TPC 3. Input Impedance vs. Frequency

TXEN = 0

TXEN = 1

+V

S

V

IN–

AD8327

V

GND

IN+

FREQUENCY – MHz

OUT

0.1␮F

75⍀

10

TPC 4. Isolation in Transmit Disable Mode
vs. Frequency

TPC 5. AC Response

100

TPC 6. Output Impedance vs. Frequency

–5–

AD8327

–50

V

= 61dBmV

–55

–60

DISTORTION – dBc

–65

–70

56515

V

= 60dBmV

OUT

@ MAX GAIN

25 35 45 55

FUNDAMENTAL FREQUENCY – MHz

OUT

@ MAX GAIN

V

= 58dBmV

OUT

@ MAX GAIN

V

= 59dBmV

OUT

@ MAX GAIN

TPC 7. Second Order Harmonic Distortion vs. Frequency
for Various Output Levels

–50

FO = 5MHz

= 60dBmV @ MAX GAIN

V

–55

OUT

–60

–65

–70

–75

DISTORTION – dBc

–80

–85

HD2

HD3

–50

V

–55

–60

–65

–70

DISTORTION – dBc

–75

–80

= 61dBmV @ MAX GAIN

OUT

V

OUT

535

25 4515

FUNDAMENTAL FREQUENCY – MHz

V

= 60dBmV @ MAX GAIN

OUT

V

= 59dBmV @ MAX GAIN

OUT

= 58dBmV @ MAX GAIN

55 65

TPC 10. Third Order Harmonic Distortion vs. Frequency
for Various Output Levels

–50

FO = 21MHz

= 60dBmV @ MAX GAIN

V

OUT

–55

–60

–65

–70

–75

DISTORTION – dBc

–80

–85

HD2

HD3

–90

0 12816

32 48 64 112

GAIN CONTROL – Decimal Code

80 96

TPC 8. Harmonic Distortion vs. Gain Control

–50

F

= 42MHz

O

–55

–60

–65

–70

–75

DISTORTION – dBc

–80

–85

–90

= 60dBmV @ MAX GAIN

V

OUT

04832 6416

HD2

HD3

80 96

GAIN CONTROL – Decimal Code

112 128

TPC 9. Harmonic Distortion vs. Gain Control

–90

0 12816

32 48 64 112

GAIN CONTROL – Decimal Code

80 96

TPC 11. Harmonic Distortion vs. Gain Control

–50

FO = 65MHz

= 60dBmV @ MAX GAIN

V

OUT

–55

–60

–65

–70

–75

DISTORTION – dBc

–80

–85

–90

0 12816

32 48 64 112

GAIN CONTROL – Decimal Code

HD2

HD3

80 96

TPC 12. Harmonic Distortion vs. Gain Control

–6–

REV. 0