Analog Devices AD8325 Datasheet

5 V CATV Line Driver Fine Step

FUNDAMENTAL FREQUENCY – MHz

–50

5

DISTORTION – dBc

–52

–54

–56

–60

–64

15 25 35 45

55 65

–62

–58

V

OUT

= 60dBmV

@ MAX GAIN

V

OUT

= 62dBmV

@ MAX GAIN

V

OUT

= 61dBmV

@ MAX GAIN

V

OUT

= 59dBmV

@ MAX GAIN

a

FEATURES
Supports DOCSIS Standard for Reverse Path

Transmission

Gain Programmable in 0.75 dB Steps Over a 59.45 dB

Range

Low Distortion at 61 dBmV Output

–57 dBc SFDR at 21 MHz
–55 dBc SFDR at 42 MHz

Output Noise Level

–48 dBmV in 160 kHz

Maintains 75 ⍀ Output Impedance

Transmit Enable and Transmit Disable Modes
Upper Bandwidth: 100 MHz (Full Gain Range)
5 V Supply Operation
Supports SPI Interfaces

APPLICATIONS
Gain-Programmable Line Driver

DOCSIS High-Speed Data Modems

Interactive Cable Set-Top Boxes

PC Plug-in Cable Modems
General-Purpose Digitally Controlled Variable Gain Block

V

IN+

V

IN–

ZIN (SINGLE) = 800⍀
Z

(DIFF) = 1.6k⍀

IN

Output Power Control

FUNCTIONAL BLOCK DIAGRAM

VCC (7 PINS)

R1

DIFF OR
SINGLE
INPUT
AMP

R2

VERNIER

DATA CLK GND (11 PINS)

DATEN

AD8325

ATTENUATION

CORE

8

DECODE

8

DATA LATCH

8

SHIFT

REGISTER

AD8325

BYP

POWER

AMP

Z

DIFF =

OUT

75⍀

POWER-DOWN

LOGIC

TXEN

SLEEP

V

V

OUT+

OUT–

GENERAL DESCRIPTION

The AD8325 is a low-cost, digitally controlled, variable gain ampli­fier optimized for coaxial line driving applications such as cable
modems that are designed to the MCNS-DOCSIS upstream
standard. An 8-bit serial word determines the desired output gain
over a 59.45 dB range resulting in gain changes of 0.7526 dB/LSB.

The AD8325 comprises a digitally controlled variable attenuator
of 0 dB to –59.45 dB, which is preceded by a low noise, fixed
gain buffer and is followed by a low distortion high power ampli­fier. The AD8325 accepts a differential or single-ended input
signal. The output is specified for driving a 75 Ω load, such as
coaxial cable.

Distortion performance of –57 dBc is achieved with an output
level up to 61 dBmV at 21 MHz bandwidth. A key performance
and cost advantage of the AD8325 results from the ability to
maintain a constant 75 Ω output impedance during Transmit
Enable and Transmit Disable conditions. In addition, this
device has a sleep mode function that reduces the quiescent
current to 4 mA.

The AD8325 is packaged in a low-cost 28-lead TSSOP, operates
from a single 5 V supply, and has an operational temperature
range of –40°C to +85°C.

Figure 1. Worst Harmonic Distortion vs. Gain Control

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD8325–SPECIFICATIONS

(TA = 25ⴗC, VS = 5 V, RL = 75 ⍀, VIN (differential) = 31 dBmV, V

measured through

OUT

a 1:1 transformer1 with an insertion loss of 0.5 dB @ 10 MHz unless otherwise noted.)

Parameter Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Specified AC Voltage Output = 61 dBmV, Max Gain 31 dBmV
Noise Figure Max Gain, f = 10 MHz 13.8 dB
Input Resistance Single-Ended Input 800 Ω

Differential Input 1600 Ω

Input Capacitance 2pF

GAIN CONTROL INTERFACE

Gain Range 58.45 59.45 60.45 dB
Maximum Gain Gain Code = 79 Dec 29.2 30.0 30.8 dB
Minimum Gain Gain Code = 0 Dec –30.25 –29.45 –28.65 dB
Gain Scaling Factor 0.7526 dB/LSB

OUTPUT CHARACTERISTICS

Bandwidth (–3 dB) All Gain Codes 100 MHz
Bandwidth Roll-Off f = 65 MHz 1.6 dB
Bandwidth Peaking f = 65 MHz 0 dB
Output Noise Spectral Density Max Gain, f = 10 MHz –33 dBmV in

160 kHz

Min Gain, f = 10 MHz –48 dBmV in

160 kHz

Transmit Disable Mode, f = 10 MHz –68 dBmV in

160 kHz

1 dB Compression Point Max Gain, f = 10 MHz 18.5 dBm
Differential Output Impedance Transmit Enable and Transmit Disable Modes 75 ± 20% Ω

OVERALL PERFORMANCE

Second Order Harmonic Distortion f = 21 MHz, V

f = 42 MHz, V
f = 65 MHz, V

Third Order Harmonic Distortion f = 21 MHz, V

f = 42 MHz, V
f = 65 MHz, V

= 61 dBmV @ Max Gain –70 dBc

OUT

= 61 dBmV @ Max Gain –67 dBc

OUT

= 61 dBmV @ Max Gain –60 dBc

OUT

= 61 dBmV @ Max Gain –57 dBc

OUT

= 61 dBmV @ Max Gain –55 dBc

OUT

= 61 dBmV @ Max Gain –54 dBc

OUT

Adjacent Channel Power Adjacent Channel Width = Transmit Channel –53.8 dBc

Width = 160 K

SYM/SEC

Gain Linearity Error f = 10 MHz, Code to Code ±0.3 dB
Output Settling

Due to Gain Change (T
Due to Input Change Max Gain, V

) Min to Max Gain 60 ns

GS

= 31 dBmV 30 ns

IN

Isolation in Transmit Disable Mode Max Gain, TXEN = 0 V, f = 42 MHz, –33 dBc

VIN = 31 dBmV

POWER CONTROL

Transmit Enable Settling Time (TON) Max Gain, VIN = 0 V 300 ns
Transmit Disable Settling Time (T
Between Burst Transients

2

) Max Gain, VIN = 0 V 40 ns

OFF

Equivalent Output = 31 dBmV 3 mV p-p
Equivalent Output = 61 dBmV 50 mV p-p

POWER SUPPLY

Operating Range 4.75 5 5.25 V
Quiescent Current Transmit Enable Mode (TXEN = 1) 123 133 140 mA

Transmit Disable Mode (TXEN = 0) 30 35 10 mA
Sleep Mode 2 4 7 mA

OPERATING TEMPERATURE –40 +85 °C
RANGE

NOTES

1

TOKO 617DB-A0070 used for above specifications. MACOM ETC-1-IT-15 can be substituted.

2

Between Burst Transients measured at the output of a 42 MHz diplexer.

Specifications subject to change without notice.

–2–

REV. 0

AD8325

LOGIC INPUTS (TTL/CMOS-Compatible Logic)

(DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 5 V: Full Temperature Range)

Parameter Min Typ Max Unit

Logic “1” Voltage 2.1 5.0 V
Logic “0” Voltage 0 0.8 V
Logic “1” Current (V
Logic “0” Current (V
Logic “1” Current (V
Logic “0” Current (V
Logic “1” Current (V
Logic “0” Current (V

TIMING REQUIREMENTS

= 5 V) CLK, SDATA, DATEN 020nA

INH

= 0 V) CLK, SDATA, DATEN –600 –100 nA

INL

= 5 V) TXEN 50 190 µA

INH

= 0 V) TXEN –250 –30 µA

INL

= 5 V) SLEEP 50 190 µA

INH

= 0 V) SLEEP –250 –30 µA

INL

(Full Temperature Range, VCC = 5 V, TR = TF = 4 ns, f

= 8 MHz unless otherwise noted.)

CLK

Parameter Min Typ Max Unit

Clock Pulsewidth (T
Clock Period (T
Setup Time SDATA vs. Clock (T
Setup Time DATEN vs. Clock (T
Hold Time SDATA vs. Clock (T
Hold Time DATEN vs. Clock (T

) 16.0 ns

WH

) 32.0 ns

C

) 5.0 ns

DS

) 15.0 ns

ES

) 5.0 ns

DH

) 3.0 ns

EH

Input Rise and Fall Times, SDATA, DATEN, Clock (TR, TF)10ns

T

DS

SDATA

VALID DATA WORD G1

MSB. . . .LSB

T

C

T

WH

VALID DATA WORD G2

CLK

DATEN

TXEN

ANALOG

OUTPUT

T

ES

8 CLOCK

CYCLES

SIGNAL AMPLITUDE (p-p)

Figure 2. Serial Interface Timing

MSB

SDATA

CLK

T

EH

GAIN TRANSFER (G1)

T

VALID DATA BIT

MSB-1

T

DS

GAIN TRANSFER (G2)

T

OFF

GS

T

ON

MSB-2

T

DH

REV. 0

Figure 3. SDATA Timing

–3–

AD8325

TOP VIEW

(Not to Scale)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

AD8325

DATEN

GND

SDATA V

CC

CLK V

IN–

GND V

IN+

V

CC

GND

TXEN V

CC

SLEEP

GND

GND BYP

V

CC

V

CC

V

CC

V

CC

GND GND

GND GND

GND GND

OUT– OUT+

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage +V

S

PIN CONFIGURATION

Pins 5, 9, 10, 19, 20, 23, 27 . . . . . . . . . . . . . . . . . . . . . . 6 V

Input Voltages

Pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V

Pins 1, 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V

Internal Power Dissipation

TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 W

Operating Temperature Range . . . . . . . . . . . –40° C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model Temperature Range Package Description ␪

JA

Package Option

AD8325ARU –40°C to +85°C 28-Lead TSSOP 67.7°C/W* RU-28
AD8325ARU-REEL –40°C to +85°C 28-Lead TSSOP 67.7°C/W* RU-28
AD8325-EVAL Evaluation Board

*Thermal Resistance measured on SEMI standard 4-layer board.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8325 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

Pin No. Mnemonic Description

1 DATEN Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic

2 SDATA Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the

3 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-

4, 8, 11, 12, GND Common External Ground Reference.
13, 16, 17, 18,
22, 24, 28

5, 9, 10, 19, V
20, 23, 27

6 TXEN Logic “0” disables transmission. Logic “1” enables transmission.
7 SLEEP Low Power Sleep Mode. Logic 0 enables Sleep mode, where Z

14 OUT– Negative Output Signal.

15 OUT+ Positive Output Signal.
21 BYP Internal Bypass. This pin must be externally ac-coupled (0.1 µF cap).

25 V

26 V

CC

IN+

IN–

PIN FUNCTION DESCRIPTIONS

0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta­neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch
(holds the previous gain state) and simultaneously enables the register for serial data load.

internal register with the MSB (Most Significant Bit) first.

slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to
the slave. This requires the input serial data word to be valid at or before this clock transition.

Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin.

goes to 400 Ω and supply

OUT

current is reduced to 4 mA. Logic 1 enables normal operation.

Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF
capacitor.

Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor.

–4–

REV. 0

Typical Performance Characteristics–AD8325

FREQUENCY – MHz

ISOLATION – dB

–40

–100

–80

–60

0

–20

0.1 10010 10001

TXEN = 0
V

IN

= 31dBmV

MAX GAIN

MIN GAIN

34

V

= 61dBmV

@ MAX GAIN

31

OUT

CL= 0pF

CL= 10pF

V

0.1␮F

V

IN–

V

165⍀

IN

0.1␮F

AD8325

V

IN+

GND

CC

OUT–

OUT+

TOKO 617DB–A0070

TPC 1. Basic Test Circuit

0.5

f = 10MHz

0

f = 5MHz

–0.5

f = 42MHz

f = 65MHz

GAIN CONTROL – Decimal

GAIN ERROR – dB

–1.0

–1.5

–2.0

10 30 50 60

0

20 40

TPC 2. Gain Error vs. Gain Control

1:1

R

L

75⍀

70 80

GAIN – dB

28

25

0.1␮F

22

V

165⍀

IN

0.1␮F

19

V

CC

V

–

IN

+

V

GND

IN

FREQUENCY – MHz

CL= 20pF

TOKO617DB–A0070

1:1

OUT–

OUT+

101

CL= 50pF

L

TPC 4. AC Response for Various Cap Loads

–30

f = 10MHz
TXEN = 1

–34

–38

–42

–46

OUTPUT NOISE – dBmV IN 160kHz

–50

024

16 328

GAIN CONTROL – Decimal

40 48 56 64 72 80

TPC 5. Output Referred Noise vs. Gain Control

75⍀C

R

L

100

REV. 0

40

30

20

10

0

–10

GAIN – dB

–20

–30

–40

–50

0.1 100

1

TPC 3. AC Response

79D

46D

23D

00D

10 1000

FREQUENCY – MHz

TPC 6. Isolation in Transmit Disable Mode vs. Frequency

–5–