Analog Devices AD8323 Datasheet

5 V CATV Line Driver Fine Step

a

FEATURES
Supports DOCSIS Standard for Reverse Path

Transmission

Gain Programmable in 0.75 dB Steps Over a 53.5 dB

Range

Low Distortion at 60 dBmV Output

–56 dBc SFDR at 21 MHz
–55 dBc SFDR at 42 MHz

Output Noise Level

–48 dBmV in 160 kHz

Maintains 75 ⍀ Output Impedance

Power-Up and Power-Down Condition
Upper Bandwidth: 100 MHz (Full Gain Range)
5 V Supply Operation
Supports SPI Interfaces

APPLICATIONS
Gain-Programmable Line Driver

HFC High-Speed Data Modems

Interactive Set-Top Boxes

PC Plug-in Modems
General-Purpose Digitally Controlled Variable Gain Block

V

IN+

V

IN–

ZIN (SINGLE) = 800⍀
Z

(DIFF) = 1.6k⍀

IN

Output Power Control

FUNCTIONAL BLOCK DIAGRAM

VCC (7 PINS)

R1

DIFF OR
SINGLE
INPUT
AMP

R2

BUFFER

DATA CLK GND (11 PINS)

DATEN

AD8323

ATTENUATION

CORE

8

DECODE

8

DATA LATCH

8

SHIFT

REGISTER

AD8323

BYP

POWER

AMP

Z

DIFF =

OUT

75⍀

POWER-DOWN

LOGIC

PD SLEEP

V

V

OUT+

OUT–

GENERAL DESCRIPTION

The AD8323 is a low-cost, digitally controlled, variable gain ampli­fier optimized for coaxial line driving applications such as cable
modems that are designed to the MCNS-DOCSIS upstream
standard. An 8-bit serial word determines the desired output gain
over a 53.5 dB range resulting in gain changes of 0.7526 dB/LSB.

The AD8323 comprises a digitally controlled variable attenuator
of 0 dB to –53.5 dB, which is preceded by a low noise, fixed
gain buffer and is followed by a low distortion high power am­plifier. The AD8323 accepts a differential or single-ended input
signal. The output is specified for driving a 75 Ω load, such as
coaxial cable.

Distortion performance of –56 dBc is achieved with an output
level up to 60 dBmV at 21 MHz bandwidth. A key performance
and cost advantage of the AD8323 results from the ability to main­tain a constant 75 Ω output impedance during power-up and
power-down conditions. This eliminates the need for external 75 Ω
termination, resulting in twice the effective output voltage when
compared to a standard operational amplifier. In addition, this
device has a sleep mode function that reduces the quiescent
current to 4 mA.

The AD8323 is packaged in a low-cost 28-lead TSSOP, operates
from a single 5 V supply, and has an operational temperature
range of –40°C to +85°C.

–50

–55

–60

–65

DISTORTION – dBc

–70

–75

8 162432404856

0

GAIN CONTROL – DEC Code

FO = 42MHz

= 60dBmV @ MAX GAIN

P

O

HD3

HD2

64 72

Figure 1. Harmonic Distortion vs. Gain Control

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD8323–SPECIFICATIONS

(TA = 25ⴗC, VS = 5 V, RL = RIN = 75 ⍀, VIN = 116 mV p-p, V
transformer1 with an insertion loss of 0.5 dB @ 10 MHz unless otherwise noted.)

measured through a 1:1

OUT

Parameter Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Specified AC Voltage Output = 60 dBmV, Max Gain 116 mV p-p
Noise Figure Max Gain, f = 10 MHz 13.8 dB
Input Resistance Single-Ended Input 800 Ω

Differential Input 1600 Ω

Input Capacitance 2pF

GAIN CONTROL INTERFACE

Gain Range 52.5 53.5 54.5 dB
Maximum Gain Gain Code = 71 Dec 26.5 27.5 28.5 dB
Minimum Gain Gain Code = 0 Dec –27 –26 –25 dB
Gain Scaling Factor 0.7526 dB/LSB

OUTPUT CHARACTERISTICS

Bandwidth (–3 dB) All Gain Codes 100 MHz
Bandwidth Roll-Off f = 65 MHz 1.3 dB
Bandwidth Peaking f = 65 MHz 0 dB
Output Noise Spectral Density Max Gain, f = 10 MHz –34 dBmV in

160 kHz

Min Gain, f = 10 MHz –48 dBmV in

160 kHz

Power-Down Mode, f = 10 MHz –68 dBmV in

160 kHz

1 dB Compression Point Max Gain, f = 10 MHz 18.5 dBm
Differential Output Impedance Power-Up and Power-Down 75 ± 20% Ω

OVERALL PERFORMANCE

Second Order Harmonic Distortion f = 21 MHz, P

f = 42 MHz, P
f = 65 MHz, P

Third Order Harmonic Distortion f = 21 MHz, P

f = 42 MHz, P
f = 65 MHz, P

= 60 dBmV @ Max Gain –77 dBc

OUT

= 60 dBmV @ Max Gain –71 dBc

OUT

= 60 dBmV @ Max Gain –64 dBc

OUT

= 60 dBmV @ Max Gain –56 dBc

OUT

= 60 dBmV @ Max Gain –55 dBc

OUT

= 60 dBmV @ Max Gain –53 dBc

OUT

Gain Linearity Error f = 10 MHz, Code to Code ±0.3 dB
Output Settling to 1 mV

Due to Gain Change Min to Max Gain 60 ns
Due to Input Step Change Max Gain, V

= 0 V to 116 mV p-p 30 ns

IN

Signal Feedthrough Max Gain, PD = 0, f = 42 MHz –30 dBc

POWER CONTROL

Power-Up Settling Time to 1 mV Max Gain, V
Power-Down Settling Time to 1 mV Max Gain, V
Between Burst Transients

2

Equivalent Output = 31 dBmV 3 mV p-p

= 0 300 ns

IN

= 0 40 ns

IN

Equivalent Output = 60 dBmV 30 mV p-p

POWER SUPPLY

Operating Range 4.75 5 5.25 V
Quiescent Current Power-Up Mode 123 133 140 mA

Power-Down Mode 30 35 40 mA
Sleep Mode 2 4 7 mA

OPERATING TEMPERATURE –40 +85 °C
RANGE

NOTES

1

TOKO 617DB-A0070 used for above specifications. MACOM ETC-1-IT-15 can be substituted.

2

Between Burst Transients measured at the output of a 42 MHz diplexer.

Specifications subject to change without notice.

–2–

REV. 0

AD8323

VALID DATA BIT

MSB

MSB-1 MSB-2

T

DS

T

DH

SDATA

CLK

LOGIC INPUTS (TTL/CMOS Compatible Logic)

(DATEN, CLK, SDATA, PD, SLEEP, VCC = 5 V: Full Temperature Range)

Parameter Min Typ Max Unit

Logic “1” Voltage 2.1 5.0 V
Logic “0” Voltage 0 0.8 V
Logic “1” Current (V
Logic “0” Current (V
Logic “1” Current (V
Logic “0” Current (V
Logic “1” Current (V
Logic “0” Current (V

TIMING REQUIREMENTS

= 5 V) CLK, SDATA, DATEN 020nA

INH

= 0 V) CLK, SDATA, DATEN –600 –100 nA

INL

= 5 V) PD 50 190 µA

INH

= 0 V) PD –250 –30 µA

INL

= 5 V) SLEEP 50 190 µA

INH

= 0 V) SLEEP –250 –30 µA

INL

(Full Temperature Range, VCC = 5 V, TR = TF = 4 ns, f

= 8 MHz unless otherwise noted.)

CLK

Parameter Min Typ Max Unit

Clock Pulsewidth (T
Clock Period (T
Setup Time SDATA vs. Clock (T
Setup Time DATEN vs. Clock (T
Hold Time SDATA vs. Clock (T
Hold Time DATEN vs. Clock (T

) 16.0 ns

WH

) 32.0 ns

C

) 5.0 ns

DS

) 15.0 ns

ES

) 5.0 ns

DH

) 3.0 ns

EH

Input Rise and Fall Times, SDATA, DATEN, Clock (TR, TF)10ns

T

DS

SDATA

CLK

VALID DATA WORD G1

MSB. . . .LSB

T

C

T

WH

VALID DATA WORD G2

ANALOG

OUTPUT

DATEN

PD

SIGNAL AMPLITUDE (p-p)

T

ES

8 CLOCK CYCLES

T

EH

GAIN TRANSFER (G1)

T

GS

T

OFF

Figure 2. Serial Interface Timing

PEDESTAL

GAIN TRANSFER (G2)

T

ON

REV. 0

Figure 3. SDATA Timing

–3–

AD8323

TOP VIEW

(Not to Scale)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

AD8323

DATEN

GND

SDATA V

CC

CLK V

IN–

GND V

IN+

V

CC

GND

PD

V

CC

SLEEP

GND

GND BYP

V

CC

V

CC

V

CC

V

CC

GND GND

GND GND

GND GND

OUT– OUT+

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage +V

S

PIN CONFIGURATION

Pins 5, 9, 10, 19, 20, 23, 27 . . . . . . . . . . . . . . . . . . . . . . 6 V

Input Voltages

Pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V

Pins 1, 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V

Internal Power Dissipation

TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 W

Operating Temperature Range . . . . . . . . . . . –40° C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model Temperature Range Package Description ␪

JA

Package Option

AD8323ARU –40°C to +85°C 28-Lead TSSOP 67.7°C/W* RU-28
AD8323ARU-REEL –40°C to +85°C 28-Lead TSSOP 67.7°C/W* RU-28
AD8323-EVAL Evaluation Board

*Thermal Resistance measured on SEMI standard 4-layer board.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8323 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

Pin No. Mnemonic Description

1 DATEN Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic

2 SDATA Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the

3 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-

4, 8, 11,12, GND Common External Ground Reference.
13, 16, 17, 18,
22, 24, 28

5, 9, 10, 19, V
20, 23, 27

6 PD Logic “0” powers down the part. Logic “1” powers up the part.
7 SLEEP Low Power Sleep Mode. In the Sleep mode, the AD8323’s supply current is reduced to 4 mA. A

14 OUT– Negative Output Signal.

15 OUT+ Positive Output Signal.
21 BYP Internal Bypass. This pin must be externally ac-coupled (0.1 µF cap).

25 V

26 V

CC

IN+

IN–

PIN FUNCTION DESCRIPTIONS

0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta­neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch
(holds the previous gain state) and simultaneously enables the register for serial data load.

internal register with the MSB (Most Significant Bit) first.

slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to
the slave. This requires the input serial data word to be valid at or before this clock transition.

Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin.

Logic “0” powers down the part (High Z

State) and a Logic “1” powers up the part.

OUT

Noninverting Input. DC-biased to approximately VCC/2. For single-ended inverting operation,
use a 0.1 µF decoupling capacitor and a 39.2 Ω resistor between V

and ground.

IN+

Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor.

–4–

REV. 0

Typical Performance Characteristics–

GAIN CONTROL – Decimal

OUTPUT NOISE – dBmV in 160kHz

–30

0

–34

–38

–42

–46

–50

8 16 2432 4048 566472

f = 10MHz
PD = 1

FREQUENCY – MHz

FEEDTHROUGH – dB

0

0.1

–20

–40

–60

–80

–100

1 10 100

1k

MAX GAIN

MIN GAIN

PD = 0
V

IN

= 116mV p-p

AD8323

GAIN ERROR – dB

–0.5

1.5

1.0

0.5

0.0

V

IN

R

V

CC

0.1␮F

V

IN–

V

IN+

GND

TI

0.1␮F

39.2⍀

82.5⍀

TPC 1. Basic Test Circuit

TOKO 617DB–A0070

0.1␮F

OUT–

OUT+

0.1␮F

f = 10MHz

f = 5MHz

f = 42MHz

1:1

OUT

34

IN

31

28

R

75⍀

L

GAIN – dB

25

V

IN–

V

IN+

1:1

OUT

C

L

CL = 50pF

22

19

1 10 100

FREQUENCY – MHz

R

L

75⍀

CL = 20pF

P

= 60dBmV

OUT

@ MAX GAIN

CL = 0pF

CL = 10pF

TPC 4. AC Response for Various Cap Loads

–1.0

–1.5

0

8 16 24 32404856

TPC 2. Gain Error vs. Gain Control

40

30

20

10

0

GAIN – dB

–10

–20

–30

–40

0.1

1 10 100 1k

TPC 3. AC Response

f = 65MHz

GAIN CONTROL – Decimal

71D

46D

23D

00D

FREQUENCY – MHz

64 72

TPC 5. Output Referred Noise vs. Gain Control

TPC 6. Input Signal Feedthrough vs. Frequency

REV. 0

–5–