ANALOG DEVICES AD8317 Service Manual

1 MHz to 10 GHz, 55 dB

VOUT

V

FEATURES

Wide bandwidth: 1 MHz to 10 GHz
High accuracy: ±1.0 dB over temperature
55 dB dynamic range up to 8 GHz ± 3 dB error
Stability over temperature: ±0.5 dB
Low noise measurement/controller output, VOUT
Pulse response time: 6 ns/10 ns (fall/rise)
Small footprint, 2 mm × 3 mm LFCSP
Supply operation: 3.0 V to 5.5 V @ 22 mA
Fabricated using high speed SiGe process

APPLICATIONS

RF transmitter PA setpoint control and level monitoring
Power monitoring in radio link transmitters
RSSI measurement in base stations, WLANs, WiMAX, and radars

GENERAL DESCRIPTION

The AD8317 is a demodulating logarithmic amplifier, capable
of accurately converting an RF input signal to a corresponding
decibel-scaled output. It employs the progressive compression
technique over a cascaded amplifier chain, each stage of which
is equipped with a detector cell. The device can be used in either
measurement or controller modes. The AD8317 maintains
accurate log conformance for signals of 1 MHz to 8 GHz and
provides useful operation to 10 GHz. The input dynamic range
is typically 55 dB (re: 50 ) with less than ±3 dB error. The
AD8317 has 6 ns/10 ns response time (fall time/rise time) that
enables RF burst detection to a pulse rate of beyond 50 MHz.
The device provides unprecedented logarithmic intercept stability
vs. ambient temperature conditions. A supply of 3.0 V to 5.5 V
is required to power the device. Current consumption is typically
22 mA, and it decreases to 200 µA when the device is disabled.

The AD8317 can be configured to provide a control voltage to a
power amplifier or a measurement output from the VOUT pin.
Because the output can be used for controller applications, special
attention has been paid to minimize wideband noise. In this
mode, the setpoint control voltage is applied to the VSET pin.

Log Detector/Controller

AD8317

FUNCTIONAL BLOCK DIAGRAM

POS

GAIN
BIAS

DET DET DET DET

INHI

INLO

The feedback loop through an RF amplifier is closed via VOUT,
the output of which regulates the output of the amplifier to a
magnitude corresponding to V
(V

− 0.1 V) output capability at the VOUT pin, suitable for

POS

controller applications. As a measurement device, VOUT is
externally connected to VSET to produce an output voltage,
V

, that is a decreasing linear-in-dB function of the RF input

OUT

signal amplitude.
The logarithmic slope is −22 mV/dB, determined by the VSET

interface. The intercept is 15 dBm (re: 50 Ω, CW input) using
the INHI input. These parameters are very stable against supply
and temperature variations.

The AD8317 is fabricated on a SiGe bipolar IC process and is
available in a 2 mm × 3 mm, 8-lead LFCSP with an operating
temperature range of −40°C to +85°C.

TADJ

SLOPE

COMM

Figure 1.

. The AD8317 provides 0 V to

SET

IV

IV

VSET

CLPF

05541-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005–2008 Analog Devices, Inc. All rights reserved.

AD8317

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 10

Using the AD8317 .......................................................................... 11

Basic Connections ...................................................................... 11

REVISION HISTORY

3/08—Rev. A to Rev. B

Changes to Features .......................................................................... 1

Changes to General Description .................................................... 1

Changes to Measurement Mode Section ..................................... 12

Changes to Equation 12 ................................................................. 15

8/07—Rev. 0 to Rev. A

Changes to f = 8.0 GHz, ±1 dB Dynamic Range Parameter ....... 4

Changes to Table 2 ............................................................................ 6

Changes to Figure 20 ...................................................................... 10

Changes to Setpoint Interface Section and Figure 22 ................ 12

Changes Figure 27 .......................................................................... 13

Changes to Table 5 .......................................................................... 17

Added Die Information Section ................................................... 19

Changes to Ordering Guide .......................................................... 21

10/05—Revision 0: Initial Version

Input Signal Coupling ................................................................ 11

Output Interface ......................................................................... 11

Setpoint Interface ....................................................................... 11

Temperature Compensation of Output Voltage ..................... 12

Measurement Mode ................................................................... 12

Setting the Output Slope in Measurement Mode .................. 13

Controller Mode ......................................................................... 13

Output Filtering .......................................................................... 15

Operation Beyond 8 GHz ......................................................... 15

Evaluation Board ............................................................................ 16

Die Information .............................................................................. 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

Rev. B | Page 2 of 20

AD8317

SPECIFICATIONS

V

= 3 V, C

POS

Table 1.

Parameter Conditions Min Typ Max Unit

SIGNAL INPUT INTERFACE INHI (Pin 1)

Specified Frequency Range 0.001 10 GHz
DC Common-Mode Voltage V

MEASUREMENT MODE

f = 900 MHz R

Input Impedance 1500||0.33 Ω||pF
±1 dB Dynamic Range TA = 25°C 50 dB

−40°C < TA < +85°C 46 dB
Maximum Input Level ±1 dB error −3 dBm

Minimum Input Level ±1 dB error −53 dBm
Slope

Intercept
Output Voltage, High Power In PIN = −10 dBm 0.42 0.58 0.78 V
Output Voltage, Low Power In PIN = −40 dBm 1.00 1.27 1.40 V

f = 1.9 GHz R

Input Impedance 950||0.38 Ω||pF
±1 dB Dynamic Range TA = 25°C 50 dB

−40°C < TA < +85°C 48 dB
Maximum Input Level ±1 dB error −4.00 dBm
Minimum Input Level ±1 dB error −54 dBm
Slope
Intercept
Output Voltage, High Power In PIN = −10 dBm 0.35 0.54 0.80 V
Output Voltage, Low Power In PIN = −35 dBm 0.75 1.21 1.35 V

f = 2.2 GHz R

Input Impedance 810||0.39 Ω||pF
±1 dB Dynamic Range TA = 25°C 50 dB

−40°C < TA < +85°C 47 dB
Maximum Input Level ±1 dB error −5 dBm
Minimum Input Level ±1 dB error −55 dBm
Slope
Intercept
Output Voltage, High Power In PIN = −10 dBm 0.53 V
Output Voltage, Low Power In PIN = −40 dBm 1.20 V

f = 3.6 GHz R

Input Impedance 300||0.33 Ω||pF
±1 dB Dynamic Range TA = 25°C 42 dB

−40°C < TA < +85°C 40 dB
Maximum Input Level ±1 dB error −6 dBm
Minimum Input Level ±1 dB error −48 dBm

Slope
Intercept
Output Voltage, High Power In PIN = −10 dBm 0.47 V
Output Voltage, Low Power In PIN = −40 dBm 1.16 V

= 1000 pF, TA = 25°C, 52.3 Ω termination resistor at INHI, unless otherwise noted.

LPF

− 0.6 V

POS

VOUT (Pin 5) shorted to VSET (Pin 4), sinusoidal
input signal

= 18 kΩ

TAD J

1

−25 −22 −19.5 mV/dB

1

12 15 21 dBm

= 8 kΩ

TAD J

1

−25 −22 −19.5 mV/dB

1

10 14 20 dBm

= 8 kΩ

TAD J

1

−22 mV/dB

1

14 dBm

= 8 kΩ

TAD J

1

−22 mV/dB

1

11 dBm

Rev. B | Page 3 of 20

AD8317

Parameter Conditions Min Typ Max Unit

f = 5.8 GHz R

Input Impedance 110||0.05 Ω||pF
±1 dB Dynamic Range TA = 25°C 50 dB

−40°C < TA < +85°C 48 dB
Maximum Input Level ±1 dB error −4 dBm
Minimum Input Level ±1 dB error −54 dBm

1

Slope

−22 mV/dB

Intercept

1

16 dBm

Output Voltage, High Power In PIN = −10 dBm 0.59 V
Output Voltage, Low Power In PIN = −40 dBm 1.27 V

f = 8.0 GHz R

Input Impedance 28||0.79 Ω||pF
±1 dB Dynamic Range TA = 25°C 44 dB

−40°C < TA < +85°C 35 dB
Maximum Input Level ±1 dB error −2 dBm
Minimum Input Level ±1 dB error −46 dBm

2

Slope

−22 mV/dB

Intercept

2

21 dBm

Output Voltage, High Power In PIN = −10 dBm 0.70 V
Output Voltage, Low Power In PIN = −40 dBm 1.39 V

OUTPUT INTERFACE VOUT (Pin 5)

Voltage Swing V
V
Output Current Drive V
Small Signal Bandwidth RFIN = −10 dBm, from CLPF to VOUT 140 MHz
Output Noise

Fall Time

Rise Time

Video Bandwidth (or Envelope Bandwidth) 50 MHz

VSET INTERFACE VSET (Pin 4)

Nominal Input Range RFIN = 0 dBm, measurement mode 0.35 V
RFIN = −50 dBm, measurement mode 1.40 V
Logarithmic Scale Factor −45 dB/V
Input Resistance RFIN = −20 dBm, controller mode, V

TAD J INTERFACE TADJ ( Pin 6)

Input Resistance TADJ = 0.9 V, sourcing 50 A 13 kΩ
Disable Threshold Voltage TADJ = open V

POWER INTERFACE VPOS (Pin 7)

Supply Voltage 3.0 5.5 V
Quiescent Current 18 22 30 mA

vs. Temperature −40°C ≤ TA ≤ +85°C 60 µA/°C

Disable Current TADJ = V

1

Slope and intercept are determined by calculating the best-fit line between the power levels of −40 dBm and −10 dBm at the specified input frequency.

2

Slope and intercept are determined by calculating the best-fit line between the power levels of −34 dBm and −16 dBm at 8.0 GHz.

= 500 Ω

TAD J

= open

TAD J

= 0 V, RFIN = open V

SET

= 1.7 V, RFIN = open 10 mV

SET

= 0 V, RFIN = open 10 mA

SET

RFIN = 2.2 GHz, −10 dBm, f

= open

C

LPF

= 100 kHz,

NOISE

Input level = no signal to −10 dBm, 90% to 10%,
C

= 8 pF

LPF

Input level = no signal to −10 dBm, 90% to 10%,

= open, R

C

LPF

= 150 Ω

OUT

Input level = −10 dBm to no signal, 10% to 90%,

= 8 pF

C

LPF

Input level = −10 dBm to no signal, 10% to 90%,
C

= open, R

LPF

= 150 Ω

OUT

= 1 V 40 kΩ

SET

200 µA

POS

90 nV/√Hz

18 ns

6 ns

20 ns

10 ns

− 0.1 V

POS

− 0.4 V

POS

Rev. B | Page 4 of 20

AD8317

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage, V
V

Voltage 0 V to V

SET

Input Power (Single-Ended, Re: 50 Ω) 12 dBm
Internal Power Dissipation 0.73 W
θJA 55°C/W
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 260°C

5.7 V

POS

POS

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 5 of 20

AD8317

C

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1INHI

OMM

2

AD8317

TOP VIEW

3CLPF

(Not to Scale)

4VSET

Figure 2. Pin Configuration

8INLO

7VPOS

6TADJ

5VOUT

05541-002

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 INHI RF Input. Nominal input range of −50 dBm to 0 dBm, re: 50 Ω; ac-coupled RF input.
2 COMM Device Common. Connect to a low impedance ground plane.
3 CLPF

Loop Filter Capacitor. In measurement mode, this capacitor sets the pulse response time and video bandwidth.

In controller mode, the capacitance on this node sets the response time of the error amplifier/integrator.
4 VSET Setpoint Control Input for Controller Mode or Feedback Input for Measurement Mode.
5 VOUT

Measurement and Controller Output. In measurement mode, VOUT provides a decreasing linear-in-dB

representation of the RF input signal amplitude. In controller mode, VOUT is used to control the gain of a VGA or

VVA with a positive gain sense (increasing voltage increases gain).
6 TADJ

Temperature Compensation Adjustment. Frequency-dependent temperature compensation is set by connecting

a ground-referenced resistor to this pin.
7 VPOS Positive Supply Voltage: 3.0 V to 5.5 V.
8 INLO RF Common for INHI. AC-coupled RF common.
Paddle Internally connected to COMM; solder to a low impedance ground plane.

Rev. B | Page 6 of 20

AD8317

TYPICAL PERFORMANCE CHARACTERISTICS

V

= 3 V; TA = +25°C, −40°C, +85°C; C

POS

by using the best-fit line between P

2.00

IN

= 1000 pF, unless otherwise noted. Black: +25°C; Blue: −40°C; Red: +85°C. Error is calculated

LPF

= −40 dBm and PIN = −10 dBm at the specified input frequency, unless otherwise noted

2.0

2.00

2.0

1.75

1.50

1.25

(V)

1.00

OUT

V

0.75

0.50

0.25

0
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5

(dBm)

P

IN

Figure 3. V

2.00

1.75

1.50

1.25

(V)

1.00

OUT

V

0.75

and Log Conformance vs. Input Amplitude at 900 MHz,

OUT

R

TADJ

= 18 kΩ

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

2.0

1.5

1.0

0.5

0

–0.5

1.75

1.50

1.25

(V)

1.00

OUT

ERROR (dB)

05541-003

ERROR (dB)

V

0.75

0.50

0.25

0
–60 –55 –50 –45 –40 –3 5 –30 –25 –20 –15 –10 –5 0 5

(dBm)

P

IN

Figure 6. V

2.00

1.75

1.50

1.25

(V)

1.00

OUT

V

0.75

and Log Conformance vs. Input Amplitude at 3.6 GHz,

OUT

R

TADJ

= 8 kΩ

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

2.0

1.5

1.0

0.5

0

–0.5

ERROR (dB)

05541-006

ERROR (dB)

0.50

0.25

0
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5

(dBm)

P

IN

Figure 4. V

2.00

1.75

1.50

1.25

(V)

1.00

OUT

V

0.75

0.50

0.25

0

–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5

Figure 5. V

and Log Conformance vs. Input Amplitude at 1.9 GHz,

OUT

and Log Conformance vs. Input Amplitude at 2.2 GHz,

OUT

R

R

TADJ

P

TADJ

= 8 kΩ

(dBm)

IN

= 8 kΩ

–1.0

–1.5

–2.0

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0.50

0.25

0
–60 –55 –50 –45 –40 –3 5 –30 –25 –20 –15 –10 –5 0 5

(dBm)

R

TADJ

P

IN

= 500 Ω

(dBm)

P

IN

05541-004

Figure 7. V

2.00

1.75

1.50

1.25

(V)

1.00

OUT

ERROR (dB)

05541-005

V

0.75

0.50

0.25

0
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5

Figure 8. V
R

TADJ

and Log Conformance vs. Input Amplitude at 5.8 GHz,

OUT

and Log Conformance vs. Input Amplitude at 8.0 GHz,

OUT

= Open, Error Calculated from PIN = −34 dBm to PIN = −16 dBm

–1.0

–1.5

–2.0

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

05541-007

ERROR (dB)

05541-008

Rev. B | Page 7 of 20

AD8317

2.00

2.0

2.00

2.0

1.75

1.50

1.25

(V)

1.00

OUT

V

0.75

0.50

0.25

0
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5

P

(dBm)

IN

Figure 9. V

2.00

1.75

1.50

1.25

(V)

1.00

OUT

V

0.75

and Log Conformance vs. Input Amplitude at 900 MHz,

OUT

Multiple Devices, R

TADJ

= 18 kΩ

1.5

1.0

0.5

0

ERROR (dB)

–0.5

–1.0

–1.5

–2.0

10

05541-009

2.0

1.5

1.0

0.5

0

ERROR (dB)

–0.5

1.75

1.50

1.25

(V)

1.00

OUT

V

0.75

0.50

0.25

0

–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10

PIN (dBm)

Figure 12. V

2.00

1.75

1.50

1.25

(V)

1.00

OUT

V

0.75

and Log Conformance vs. Input Amplitude at 3.6 GHz,

OUT

Multiple Devices, R

TADJ

= 8 kΩ

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

2.0

1.5

1.0

0.5

0

–0.5

ERROR (dB)

05541-012

ERROR (dB)

0.50

0.25

0
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5

P

(dBm)

IN

Figure 10. V

2.00

1.75

1.50

1.25

(V)

1.00

OUT

V

0.75

0.50

0.25

0

–60 –55 –50 –45 –4 0 –35 –30 –25 –20 –15 –10 –5 0 5

Figure 11. V

and Log Conformance vs. Input Amplitude at 1.9 GHz,

OUT

Multiple Devices, R

PIN (dBm)

and Log Conformance vs. Input Amplitude at 2.2 GHz,

OUT

Multiple Devices, R

TADJ

TADJ

= 8 kΩ

= 8 kΩ

–1.0

–1.5

–2.0

10

05541-010

2.0

1.5

1.0

0.5

0

ERROR (dB)

–0.5

–1.0

–1.5

–2.0

05541-011

0.50

0.25

0
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5

P

(dBm)

IN

Figure 13. V

2.00

1.75

1.50

1.25

(V)

1.00

OUT

V

0.75

0.50

0.25

0
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10

Figure 14. V

and Log Conformance vs. Input Amplitude at 5.8 GHz,

OUT

Multiple Devices, R

P

IN

and Log Conformance vs. Input Amplitude at 8.0 GHz,

OUT

Multiple Devices, R

Error Calculated from P

IN

= 500 Ω

TADJ

(dBm)

= Open,

TADJ

= −34 dBm to PIN = −16 dBm

–1.0

–1.5

–2.0

10

05541-013

2.0

1.5

1.0

0.5

0

ERROR (dB)

–0.5

–1.0

–1.5

–2.0

05541-014

Rev. B | Page 8 of 20

AD8317

j1

j0.5

j2

10000

–60dBm

j0.2

0

0.2 0.5 1 2

–j0.2

8000MHz

START FREQUENCY = 0.05G Hz
STOP FREQUENCY = 10GHz

–j0.5

10000MHz

–j2

–j1

5800MHz

3600MHz

100MHz

900MHz

1900MHz

2200MHz

Figure 15. Input Impedance vs. Frequency; No Termination Resistor on INHI

(Impedance De-Embedded to Input Pins), Z

3

= 50 Ω

0

Δ : 1.86V

@ : 1.69V

1000

100

NOISE SPECTRAL DENSITY (nV/ Hz)

10

1k 10k 100k 1M

05541-015

Figure 18. Noise Spectral Density of Output; C

10000

1000

100

–40dBm

–20dBm

0dBm

FREQUENCY ( Hz)

RF OFF

LPF

–10dBm

= Open

10M

05541-018

4

Ch3 500mV Ch4 200mV M4.00µs

T 12.7560µs

Figure 16. Power-On/Power-Off Response Time; V

Input AC-Coupling Capacitors = 10 pF; C

CH1 200mV

Figure 17. V

Pulse Response Time; Pulsed RF Input 0.1 GHz, −10 dBm;

OUT

M20.0ns A CH1 1.40V

T 943.600ns

= Open; R

C

LPF

LOAD

A Ch3 620mV

= 150 Ω

= Open

LPF

= 3.0 V;

POS

05541-017

CH1 RISE

10.44ns

CH1 FALL

6.113ns

05541-016

NOISE SPE CTRAL DENSITY (n V/ Hz)

10

1k 10k 100k 1M

FREQUENCY ( Hz)

10M

05541-019

Figure 19. Noise Spectral Density of Output Buffer (from CLPF to VOUT);

= 0.1 μF

C

LPF

2.00

1.75

1.50

1.25

(V)

1.00

OUT

V

0.75

0.50

3.3V

0.25

3.0V

3.6V

0

–55 –45 –35 –25 –15 –5 5 15

–65

P

(dBm)

IN

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

ERROR (d B)

05541-020

Figure 20. Output Voltage Stability vs. Supply Voltage at 1.9 GHz

When V

Varies by 10%

POS

Rev. B | Page 9 of 20

AD8317

VOUT

V

THEORY OF OPERATION

The AD8317 is a 6-stage demodulating logarithmic amplifier,
specifically designed for use in RF measurement and power
control applications at frequencies up to 10 GHz. A block
diagram is shown in Figure 21. Sharing much of its design
with the AD8318 logarithmic detector/controller, the AD8317
maintains tight intercept variability vs. temperature over a 50 dB
range. Additional enhancements over the AD8318, such as a
reduced RF burst response time of 6 ns to 10 ns, 22 mA supply
current, and board space requirements of only 2 mm × 3 mm,
add to the low cost and high performance benefits of the AD8317.

TADJ

SLOPE

COMM

IV

IV

VSET

CLPF

INHI

INLO

POS

GAIN

BIAS

DET DET DET DET

Figure 21. Block Diagram

A fully differential design, using a proprietary, high speed SiGe
process, extends high frequency performance. Input INHI receives
the signal with a low frequency impedance of nominally 500 Ω
in parallel with 0.7 pF. The maximum input with ±1 dB log­conformance error is typically 0 dBm (re: 50 Ω). The noise
spectral density referred to the input is 1.15 nV/√Hz, which is
equivalent to a voltage of 118 µV rms in a 10.5 GHz bandwidth
or a noise power of −66 dBm (re: 50 Ω). This noise spectral
density sets the lower limit of the dynamic range. However,
the low end accuracy of the AD8317 is enhanced by specially
shaping the demodulating transfer characteristic to partially

05541-021

compensate for errors due to internal noise. The common pin,
COMM, provides a quality low impedance connection to the
printed circuit board (PCB) ground. The package paddle, which
is internally connected to the COMM pin, should also be grounded
to the PCB to reduce thermal impedance from the die to the PCB.

The logarithmic function is approximated in a piecewise fashion
by six cascaded gain stages. (For a more comprehensive expla­nation of the logarithm approximation, see the AD8307 data
sheet.) The cells have a nominal voltage gain of 9 dB each and a
3 dB bandwidth of 10.5 GHz. Using precision biasing, the gain
is stabilized over temperature and supply variations. The overall
dc gain is high, due to the cascaded nature of the gain stages. An
offset compensation loop is included to correct for offsets
within the cascaded cells. At the output of each of the gain
stages, a square-law detector cell is used to rectify the signal.

The RF signal voltages are converted to a fluctuating differential
current having an average value that increases with signal level.
Along with the six gain stages and detector cells, an additional
detector is included at the input of the AD8317, providing a
50 dB dynamic range in total. After the detector currents are
summed and filtered, the following function is formed at the
summing node:

I

× log10(VIN/V

D

) (1)

INTERCEPT

where:

I

is the internally set detector current.

D

is the input signal voltage.

V

IN

V

is the intercept voltage (that is, when VIN = V

INTERCEPT

INTERCEPT

,

the output voltage would be 0 V, if it were capable of going to 0 V).

Rev. B | Page 10 of 20

AD8317

V

V

VOUT

V

C

V

USING THE AD8317

BASIC CONNECTIONS

The AD8317 is specified for operation up to 10 GHz; as a result,
low impedance supply pins with adequate isolation between
functions are essential. A power supply voltage of between 3.0 V
and 5.5 V should be applied to VPOS. Power supply decoupling
capacitors of 100 pF and 0.1 µF should be connected close to
this power supply pin.

(3.0VTO 5.5V)

S

C5

0.1µF

R2
0Ω

C4

C2

47nF

R1

52.3Ω

SIGNAL

INPUT

1

SEE THE TEMPERATURE COMPENSATION OF OUTPUT VOLTAGE SECTION.

2

SEE THE OUTPUT FILTERING SECTION.

C1

47nF

100pF

8 7 6 5

INLO VPOS TADJ VOUT

AD8317

INHI

COMM CLPF VSET

1 2 3 4

1

2

V

OUT

R4
0Ω

Figure 22. Basic Connections

The paddle of the LFCSP package is internally connected to
COMM. For optimum thermal and electrical performance, the
paddle should be soldered to a low impedance ground plane.

INPUT SIGNAL COUPLING

The RF input (INHI) is single-ended and must be ac-coupled.
INLO (input common) should be ac-coupled to ground.
Suggested coupling capacitors are 47 nF ceramic 0402-style
capacitors for input frequencies of 1 MHz to 10 GHz. The
coupling capacitors should be mounted close to the INHI and
INLO pins. The coupling capacitor values can be increased to
lower the high-pass cutoff frequency of the input stage. The
high-pass corner is set by the input coupling capacitors and the
internal 10 pF high-pass capacitor. The dc voltage on INHI and
INLO is approximately one diode voltage drop below V

POS

5pF 5pF

18.7kΩ 18.7kΩ

INHI

INLO

CURRENT

2kΩ

gm

STAGE

Figure 23. Input Interface

FIRST

GAIN

STAGE

A = 9dB

OFFSET
COMP

While the input can be reactively matched, in general, this is not
necessary. An external 52.3 Ω shunt resistor (connected on the
signal side of the input coupling capacitors, as shown in

.

POS

05541-023

Rev. B | Page 11 of 20

05541-022

Figure 22) combines with the relatively high input impedance to
give an adequate broadband 50 Ω match.

The coupling time constant, 50 × C
corner with a 3 dB attenuation at f
C1 = C2 = C

. Using the typical value of 47 nF, this high-pass

C

corner is ~68 kHz. In high frequency applications, f

/2, forms a high-pass

C

= 1/(2π × 50 × CC ), where

HP

should be

HP

as large as possible to minimize the coupling of unwanted low
frequency signals. In low frequency applications, a simple RC
network forming a low-pass filter should be added at the input
for similar reasons. This low-pass filter network should generally
be placed at the generator side of the coupling capacitors, thereby
lowering the required capacitance value for a given high-pass
corner frequency.

OUTPUT INTERFACE

The VOUT pin is driven by a PNP output stage. An internal
10 Ω resistor is placed in series with the output and the VOUT
pin. The rise time of the output is limited mainly by the slew
on CLPF. The fall time is an RC-limited slew given by the load
capacitance and the pull-down resistance at VOUT. There is an
internal pull-down resistor of 1.6 kΩ. A resistive load at VOUT
is placed in parallel with the internal pull-down resistor to
provide additional discharge current.

POS

CLPF

OMM

0.8V

+

–

10Ω

1200Ω

400Ω

05541-024

Figure 24. Output Interface

To reduce the fall time, VOUT should be loaded with a resistive
load of <1.6 kΩ. For example, with an external load of 150 Ω,
the AD8317 fall time is <7 ns.

SETPOINT INTERFACE

The V
internal op amp. The V

1.5 kΩ resistor to generate I
applied to VSET, the feedback loop forces

If V

The result is

input drives the high impedance (40 kΩ) input of an

SET

voltage appears across the internal

SET

. When a portion of V

SET

−I

× log10(VIN/V

D

= V

SET

V

/2x, then I

OUT

= (−ID × 1.5 kΩ × 2x) × log10(VIN/V

OUT

SET

INTERCEPT

= V

SET

20kΩ

20kΩ

) = I

SET

/(2x × 1.5 kΩ).

OUT

V

SET

COMM

(2)

INTERCEPT

I

SET

1.5kΩ

COMM

05541-025

Figure 25. VSET Interface

is

OUT

)

AD8317

The slope is given by

× 2x × 1.5 kΩ = −22 mV/dB × x

−I

D

For example, if a resistor divider to ground is used to generate a
V

voltage of V

SET

/2, x = 2. The slope is set to −880 V/decade

OUT

or −44 mV/dB.

TEMPERATURE COMPENSATION OF OUTPUT VOLTAGE

The primary component of the variation in V
as the input signal amplitude is held constant, is the drift of the
intercept. This drift is also a weak function of the input signal
frequency; therefore, provision is made for the optimization of
internal temperature compensation at a given frequency by
providing Pin TADJ.

V

INTERNAL

TADJ

R

TADJ

1.5k

COMM COMM

Figure 26. TADJ Interface

R

is connected between TADJ and ground. The value of

TAD J

this resistor partially determines the magnitude of an analog
correction coefficient, which is used to reduce intercept drift.

The relationship between output temperature drift and
frequency is not linear and cannot be easily modeled. As a
result, experimentation is required to choose the correct
TADJ resistor. Ta b l e 4 shows the recommended values for
some commonly used frequencies.

Table 4. Recommended R

TADJ

Values

Frequency Recommended R

50 MHz 18 kΩ
100 MHz 18 kΩ
900 MHz 18 kΩ

1.8 GHz 8 kΩ

1.9 GHz 8 kΩ

2.2 GHz 8 kΩ

3.6 GHz 8 kΩ

5.3 GHZ 500 Ω

5.8 GHz 500 Ω
8 GHz Open

OUT

AD8317

I

COMP

Ω

TAD J

vs. temperature,

05541-026

MEASUREMENT MODE

When the V
back to the VSET pin, the device operates in measurement
mode. As seen in Figure 27, the AD8317 has an offset voltage,
a negative slope, and a V
end of its input signal range.

voltage or a portion of the V

OUT

measurement intercept at the high

OUT

voltage is fed

OUT

2.00

V

IDEAL

OUT

V

1.75

1.50

1.25

(V)

1.00

OUT

V

0.75

0.50

0.25

0

–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15

SLOPE AND I NTERCEPT

25°C

OUT

ERROR 25°C

RANGE FOR

CALCULATION OF

P

(dBm)

IN

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

INTERCEPT

Figure 27. Typical Output Voltage vs. Input Signal

The output voltage vs. input signal voltage of the AD8317 is
linear-in-dB over a multidecade range. The equation for this
function is

V

= X × V

OUT

= X × V

SLOPE/dB

× log10(VIN/V

SLOPE/DEC

× 20 × log10(VIN/V

) (3)

INTERCEPT

) (4)

INTERCEPT

where:

X is the feedback factor in V
V
V

the V

V

An offset voltage, V

is nominally −440 mV/decade, or −22 mV/dB.

SLOPE/DEC

is the x-axis intercept of the linear-in-dB portion of

INTERCEPT

vs. PIN curve (see Figure 27).

OUT

is 2 dBV for a sinusoidal input signal.

INTERCEPT

OFFSET

the detector signal, so that the minimum value for V
X × V

; therefore, for X = 1, the minimum V

OFFSET

= V

OUT

/X.

SET

, of 0.35 V is internally added to

is

OUT

is 0.35 V.

OUT

The slope is very stable vs. process and temperature variation.
When base-10 logarithms are used, V

SLOPE/DECADE

volts/decade. A decade corresponds to 20 dB; V
V

represents the slope in volts/dB.

SLOPE/dB

As noted in Equation 3 and Equation 4, the V

represents the

SLOPE/DECADE

voltage has a

OUT

/20 =

negative slope. This is also the correct slope polarity to control
the gain of many power amplifiers in a negative feedback con­figuration. Because both the slope and intercept vary slightly
with frequency, it is recommended to refer to the Specifications
section for application-specific values for slope and intercept.

Although demodulating log amps respond to input signal
voltage, not input signal power, it is customary to discuss the
amplitude of high frequency signals in terms of power. In this
case, the characteristic impedance of the system, Z

, must be

0

known to convert voltages to their corresponding power levels.
The following equations are used to perform this conversion:

P [dBm] = 10 × log

P [dBV] = 20 × log

P [dBm] = P [dBV] − 10 × log

2

/(Z0 × 1 mW)) (5)

10(VRMS

/1 V

10(VRMS

) (6)

RMS

× 1 mW/1 V

10(Z0

2

) (7)

RMS

05541-027

Rev. B | Page 12 of 20

AD8317

For example, P

for a sinusoidal input signal expressed in

INTERCEPT

terms of dBm (decibels referred to 1 mW), in a 50 Ω system is

P
P

2 dBV − 10 × log

[dBm] =

INTERCEPT

[dBV] − 10 × log10(Z0 × 1 mW/1 V

INTERCEPT

(50 × 10−3) = 15 dBm (8)

10

RMS

2

) =

For a square wave input signal in a 200 Ω system,

P

−1 dBV − 10 × log

INTERCEPT

=

[(200 Ω × 1 mW/1 V

10

2

)] = 6 dBm

RMS

Further information on the intercept variation dependence
upon waveform can be found in the AD8313 and AD8307
data sheets.

SETTING THE OUTPUT SLOPE IN MEASUREMENT MODE

To operate in measurement mode, VOUT must be connected
to VSET. Connecting VOUT directly to VSET yields the nominal
logarithmic slope of approximately −22 mV/dB. The output
swing corresponding to the specified input range is then approx­imately 0.35 V to 1.7 V. The slope and output swing can be
increased by placing a resistor divider between VOUT and
VSET (that is, one resistor from VOUT to VSET and one
resistor from VSET to ground). The input impedance of VSET
is approximately 40 kΩ. Slope-setting resistors should be kept
below 20 kΩ to prevent this input impedance from affecting
the resulting slope. If two equal resistors are used (for example,
10 kΩ/10 kΩ), the slope doubles to approximately −44 mV/dB.

AD8317

VOUT

VSET

Figure 28. Increasing the Slope

10kΩ

10kΩ

–44mV/dB

05541-028

CONTROLLER MODE

The AD8317 provides a controller mode feature at the VOUT
pin. By using V
AD8317 to control subsystems, such as power amplifiers (PAs),
variable gain amplifiers (VGAs), or variable voltage attenuators
(VVAs), that have output power that increases monotonically
with respect to their gain control signal.

To operate in controller mode, the link between VSET and
VOUT is broken. A setpoint voltage is applied to the VSET
input, VOUT is connected to the gain control terminal of the
VGA, and the RF input of the detector is connected to the
output of the VGA (usually using a directional coupler and
some additional attenuation). Based on the defined relationship

for the setpoint voltage, it is possible for the

SET

between V

and the RF input signal when the device is in

OUT

measurement mode, the AD8317 adjusts the voltage on VOUT
(VOUT is now an error amplifier output) until the level at the
RF input corresponds to the applied V

. When the AD8317

SET

operates in controller mode, there is no defined relationship
between the V

and the V

SET

voltage; V

OUT

settles to a value

OUT

that results in the correct input signal level appearing at
INHI/INLO.

For this output power control loop to be stable, a ground­referenced capacitor must be connected to the CLPF pin. This
capacitor, C

, integrates the error signal (in the form of a

FLT

current) to set the loop bandwidth and ensure loop stability.
Further details on control loop dynamics can be found in the

AD8315 data sheet.

DIRECTIONA L

COUPLER

ATT ENU ATOR

47nF

INHI

52.3Ω

INLO

47nF

Figure 29. Controller Mode

Decreasing V

, which corresponds to demanding a higher

SET

signal from the VGA, increases V

VGA/VVA

GAIN
CONTROL
VOLTAGE

VOUT

AD8317

VSET

CLPF

C

. The gain control voltage

OUT

FLT

RFIN

DAC

05541-029

of the VGA must have a positive sense. A positive control
voltage to the VGA increases the gain of the device.

The basic connections for operating the AD8317 in an auto­matic gain control (AGC) loop with the ADL5330 are shown in
Figure 30. The ADL5330 is a 10 MHz to 3 GHz VGA. It offers a
large gain control range of 60 dB with ±0.5 dB gain stability.
This configuration is similar to Figure 29.

The gain of the ADL5330 is controlled by the output pin of the
AD8317. This voltage, V

, has a range of 0 V to near V

OUT

POS

. To
avoid overdrive recovery issues, the AD8317 output voltage can
be scaled down using a resistive divider to interface with the 0 V
to 1.4 V gain control range of the ADL5330.

A coupler/attenuation of 21 dB is used to match the desired
maximum output power from the VGA to the top end of the
linear operating range of the AD8317 (approximately −5 dBm
at 900 MHz).

Rev. B | Page 13 of 20

AD8317

V

V

RF INPUT

SIGNAL

100pF

+5

VPSx COMx

INHI

OPHI

ADL5330

OPLO

GAIN

10kΩ

VOUT VPOS

AD8317

LOG AMP

TADJ

DAC

1nF

100pF

SETPOINT

VOLTAGE

INLO

4.12kΩ

VSET INHI

18kΩ

Figure 30. AD8317 Operating in Controller Mode to Provide Automatic Gain Control Functionality in Combination with the ADL5330

Figure 31 shows the transfer function of the output power vs.
the setpoint voltage over temperature for a 900 MHz sine wave
with an input power of −1.5 dBm. Note that the power control
of the AD8317 has a negative sense. Decreasing V

, which

SET

corresponds to demanding a higher signal from the ADL5330,
increases gain.

The AGC loop is capable of controlling signals just under the
full 60 dB gain control range of the ADL5330. The performance
over temperature is most accurate over the highest power range,
where it is generally most critical. Across the top 40 dB range
of output power, the linear conformance error is well within
±0.5 dB over temperature.

30

20

10

4

3

2

+5V

COMM

+5

RF OUTPUT

120nH

INLOCLPF

47nF

47nF

120nH

100pF

100pF

52.3Ω

DIRECTIO NAL
COUPLER

ATT ENU ATOR

SIGNAL

05541-030

For the AGC loop to remain in equilibrium, the AD8317 must
track the envelope of the ADL5330 output signal and provide
the necessary voltage levels to the ADL5330 gain control input.
Figure 32 shows an oscilloscope screenshot of the AGC loop
depicted in Figure 30. A 100 MHz sine wave with 50% AM
modulation is applied to the ADL5330. The output signal from
the VGA is a constant envelope sine wave with amplitude corre­sponding to a setpoint voltage at the AD8317 of 1.5 V. Also
shown is the gain control response of the AD8317 to the
changing input envelope.

AM MODULATED INPUT

1

AD8317 OUTPUT

0

–10

–20

OUTPUT POWER (dBm)

–30

–40

–50

0.2 0. 4 0.6 0.8 1.0 1.4 1.8

SETPOINT VOLTAGE (V)

1.61.2

Figure 31. ADL5330 Output Power vs. AD8317 Setpoint Voltage, P

1

0

–1

–2

–3

–4

0

.

2

= −1.5 dBm

IN

ERROR (dB)

3

ADL5330 OUTPUT

2

CH1 200mV
CH3 50.0mVΩ

Ch2 200mV

M2.00ms

T 640.00µs

A CH2 820mV

05541-032

Figure 32. Oscilloscope Screenshot Showing an AM Modulated Input Signal

and the Response from the AD8317

05541-031

Rev. B | Page 14 of 20

AD8317

Figure 33 shows the response of the AGC RF output to a pulse
on VSET. As V

decreases from 1.7 V to 0.4 V, the AGC loop

SET

responds with an RF burst. In this configuration, the input
signal to the ADL5330 is a 1 GHz sine wave at a power level
of −15 dBm.

T

AD8317 VSET PULSE

I

LOG

1.5kΩ

3.5pF

AD8317

+4

VOUT

CLPF

C

FLT

05541-037

1

ADL5330 OUTPUT

2

CH2 50mVΩ

M10.0µsCH1 2.00V

T 699.800µs

A CH1 2.48V

05541-033

Figure 33. Oscilloscope Screenshot Showing

the Response Time of the AGC Loop

Response time and the amount of signal integration are con­trolled by C

. This functionality is analogous to the feedback

FLT

capacitor around an integrating amplifier. Although it is
possible to use large capacitors for C

, in most applications,

FLT

values under 1 nF provide sufficient filtering.

Calibration in controller mode is similar to the method used
in measurement mode. A simple 2-point calibration can be
done by applying two known V

voltages or DAC codes and

SET

measuring the output power from the VGA. Slope and intercept
can then be calculated by:

− V

)/(P

− P

Slope = (V

SET1

Intercept = P

V

= Slope × (P

SETx

OUT1

SET2

OUT1

− V

/Slope (10)

SET1

− Intercept) (11)

OUTX

) (9)

OUT2

More information on the use of the ADL5330 in AGC applica­tions can be found in the ADL5330 data sheet.

OUTPUT FILTERING

For applications in which maximum video bandwidth and,
consequently, fast rise time are desired, it is essential that the
CLPF pin be left unconnected and free of any stray capacitance.

The nominal output video bandwidth of 50 MHz can be reduced
by connecting a ground-referenced capacitor (C
pin, as shown in Figure 34. This is generally done to reduce
output ripple (at twice the input frequency for a symmetric
input waveform such as sinusoidal signals).

) to the CLPF

FLT

Rev. B | Page 15 of 20

Figure 34. Lowering the Postdemodulation Bandwidth

C

is selected by

FLT

=

C

FLT

π

1

××

BandwidthVideo

pF5.3

−

)k5.12(

(12)

The video bandwidth should typically be set to a frequency
equal to about one-tenth the minimum input frequency. This
ensures that the output ripple of the demodulated log output,
which is at twice the input frequency, is well filtered.

In many log amp applications, it may be necessary to lower
the corner frequency of the postdemodulation filter to achieve
low output ripple while maintaining a rapid response time to
changes in signal level. An example of a 4-pole active filter is
shown in the AD8307 data sheet.

OPERATION BEYOND 8 GHz

The AD8317 is specified for operation up to 8 GHz, but it provides
useful measurement accuracy over a reduced dynamic range of
up to 10 GHz. Figure 35 shows the performance of the AD8317
over temperature at 10 GHz when the device is configured as
shown in Figure 22. Dynamic range is reduced at this frequency,
but the AD8317 does provide 30 dB of measurement range
within ±3 dB of linearity error.

2.0

1.8

1.6

1.4

1.2

(V)

1.0

OUT

V

0.8

0.6

0.4

0.2

0

–40 –35 –30 –25 –20 –15 –10 –5 0 5

Figure 35. V

and Log Conformance vs. Input Amplitude at 10.0 GHz,

OUT

Multiple Devices, R

P

(dBm)

IN

TADJ

= Open, C

= 1000 pF

LPF

Implementing an impedance match for frequencies beyond
8 GHz can improve the sensitivity of the AD8317 and measure­ment range.

Operation beyond 10 GHz is possible, but part-to-part
variation, most notably in the intercept, becomes significant.

5

4

3

2

1

0

–1

ERROR (dB)

–2

–3

–4

–5

05541-038

AD8317

V

T

EVALUATION BOARD

Table 5. Evaluation Board (Rev. A) Configuration Options

Component Function Default Conditions

VPOS, GND Supply and Ground Connections. Not applicable
R1, C1, C2

R5, R7

R2, R3, R4, R6, RL, CL

R2, R3

C4, C5

C3

Input Interface.
The 52.3 Ω resistor in Position R1 combines with the internal input impedance
of the AD8317 to give a broadband input impedance of about 50 Ω. C1 and C2
are dc-blocking capacitors. A reactive impedance match can be implemented
by replacing R1 with an inductor and C1 and C2 with appropriately valued
capacitors.

Temperature Compensation Interface.
The internal temperature compensation network is optimized for input signals
up to 3.6 GHz when R7 is 10 kΩ. This circuit can be adjusted to optimize
performance for other input frequencies by changing the value of the resistor
in Position R7. See Table 4 for specific R

resistor values.

TAD J

Output Interface—Measurement Mode.
In measurement mode, a portion of the output voltage is fed back to the VSET
pin via R2. The magnitude of the slope of the VOUT output voltage response
can be increased by reducing the portion of V

that is fed back to VSET. R6

OUT

can be used as a back-terminating resistor or as part of a single-pole, low-pass
filter.

Output Interface—Controller Mode.
In this mode, R2 must be open. In controller mode, the AD8317 can control the
gain of an external component. A setpoint voltage is applied to Pin VSET, the
value of which corresponds to the desired RF input signal level applied to the
AD8317 RF input. A sample of the RF output signal from this variable gain
component is selected, typically via a directional coupler, and applied to the
AD8317 RF input. The voltage at the VOUT pin is applied to the gain control of
the variable gain element. A control voltage is applied to the VSET pin. The
magnitude of the control voltage can optionally be attenuated via the voltage
divider comprising R2 and R3, or a capacitor can be installed in Position R3 to
form a low-pass filter along with R2.

Power Supply Decoupling.
The nominal supply decoupling consists of a 100 pF filter capacitor placed
physically close to the AD8317 and a 0.1 µF capacitor placed nearer to the
power supply input pin.

Filter Capacitor.
The low-pass corner frequency of the circuit that drives the VOUT pin can be
lowered by placing a capacitor between CLPF and ground. Increasing this
capacitor increases the overall rise/fall time of the AD8317 for pulsed input
signals. See the Output Filtering section for more details.

POS

TADJ

R6

1kΩ

GND

CL
OPENRLOPEN

V

SET

RFIN

52.3Ω

C4

0.1µF

C5

C1

47nF

R1

C2

47nF

100pF

8 7 6 5

INLO VPOS TADJ VOUT

AD8317

INHI

COMM CLPF VSET

1 2 3 4

R5
200Ω

R7

OPEN

C3

8.2pF
R3

OPEN

VOUT_ALT

R4
OPEN

R2
0Ω

R1 = 52.3 Ω (Size 0402)
C1 = 47 nF (Size 0402)
C2 = 47 nF (Size 0402)

R5 = 200 Ω (Size 0402)
R7 = open (Size 0402)

R2 = 0 Ω (Size 0402)
R3 = open (Size 0402)
R4 = open (Size 0402)
R6 = 1 kΩ (Size 0402)
RL = CL = open (Size 0402)

R2 = open (Size 0402)
R3 = open (Size 0402)

C4 = 0.1 µF (Size 0603)
C5 = 100 pF (Size 0402)

C3 = 8.2 pF (Size 0402)

V

OU

05541-034

Figure 36. Evaluation Board Schematic

Rev. B | Page 16 of 20

AD8317

05541-036

05541-035

Figure 37. Component Side Layout

Figure 38. Component Side Silkscreen

Rev. B | Page 17 of 20

AD8317

X

DIE INFORMATION

1

2

2

ADI AD8317

3

4

DB1

BOND PAD STATI STICS

ALL MEASURMENT S IN MICRO NS.
MINIMUM PASSIVATION OPENING: 59 × 59 MIN PAD PITCH: 89

DIE SIZE CALCULATIO N
ALL MEASURMENT S IN MICRO NS.

DIEX (WIDTH OF DIE IN X DIRECTION) = 670
DIEY (WIDTH OF DIE IN Y DIRECTION) = 1325

DIE THICKNESS = 305 MICRONS

BALL BOND SHEAR ST RENGTH SPECIFICATION: MINI MUM 15 GRAMS

8

7

Y

6

5

05541-039

Figure 39. Die Outline Dimensions

Table 6. Die Pad Function Descriptions

Pin No. Mnemonic Description

1 INHI RF Input. Nominal input range of −50 dBm to 0 dBm, re: 50 Ω; ac-coupled RF input.
2, 2 COMM Device Common. Connect both pads to a low impedance ground plane.
3 CLPF

Loop Filter Capacitor. In measurement mode, this capacitor sets the pulse response time and video
bandwidth. In controller mode, the capacitance on this node sets the response time of the error

amplifier/integrator.
4 VSET Setpoint Control Input for Controller Mode or Feedback Input for Measurement Mode.
5 VOUT

Measurement and Controller Output. In measurement mode, VOUT provides a decreasing linear-in dB

representation of the RF input signal amplitude. In controller mode, VOUT is used to control the gain of

a VGA or VVA with a positive gain sense (increasing voltage increases gain).
6 TADJ

Temperature Compensation Adjustment. Frequency-dependent temperature compensation is set by

connecting a ground-referenced resistor to this pin.
7 VPOS Positive Supply Voltage: 3.0 V to 5.5 V.
8 INLO RF Common for INHI. AC-coupled RF common.
DB1 COMM Device Common. Connect to a low impedance ground plane.

Rev. B | Page 18 of 20

AD8317

C

OUTLINE DIMENSIONS

1.89

1.74

1.59

5

EXPOSEDPAD

BOTTOM VIEW

4

8

1

0.50 BSC

0.25

0.20

0.15

0.15

0.10

0.05

INDI

PIN 1

ATO R

1.95

1.75

1.55

3.25

3.00

2.75

TOP VIEW

2.95

2.75

2.55

2.25

2.00

1.75

0.60

0.45

0.30

0.55

0.40

0.30

1.00

0.85

0.80

SEATING

PLANE

12° MAX

0.30

0.23

0.18

0.80 MAX

0.65 TYP

0.20 REF

0.05 MAX

0.02 NOM

031207-A

Figure 40. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]

2 mm × 3 mm Body, Very Thin, Dual Lead

(CP-8-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8317ACPZ-R7
AD8317ACPZ-R2
AD8317ACPZ-WP
AD8317ACHIPS −40°C to +85°C Die
AD8317-EVALZ

1

Z = RoHS Compliant Part.

1

−40°C to +85°C 8-Lead LFCSP_VD, 7” Tape and Reel CP-8-1 Q1

1

−40°C to +85°C 8-Lead LFCSP_VD, 7” Tape and Reel CP-8-1 Q1

1

−40°C to +85°C 8-Lead LFCSP_VD, Waffle Pack CP-8-1 Q1

1

Evaluation Board

Rev. B | Page 19 of 20

AD8317

NOTES

©2005–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05541-0-3/08(B)

Rev. B | Page 20 of 20