10 MHz, 20 V/μs, G = 1, 10, 100, 1000 iCMOS
Programmable Gain Instrumentation Amplifier
Data Sheet
FEATURES
Small package: 10-lead MSOP
Programmable gains: 1, 10, 100, 1000
Digital or pin-programmable gain setting
Wide supply: ±5 V to ±15 V
Excellent dc performance
High CMRR: 100 dB (minimum), G = 100
Low gain drift: 10 ppm/°C (maximum)
Low offset drift: 1.2 V/°C (maximum), G = 1000
Excellent ac performance
Fast settling time: 780 ns to 0.001% (maximum)
High slew rate: 20 V/µs (minimum)
Low distortion: −110 dB THD at 1 kHz,10 V swing
High CMRR over frequency: 100 dB to 20 kHz (minimum)
Low noise: 10 nV/√Hz, G = 1000 (maximum)
Low power: 4 mA
APPLICATIONS
Data acquisition
Biomedical analysis
Test and measurement
GENERAL DESCRIPTION
The AD8253 is an instrumentation amplifier with digitally
programmable gains that has gigaohm (GΩ) input impedance,
low output noise, and low distortion, making it suitable for
interfacing with sensors and driving high sample rate analog-todigital converters (ADCs).
It has a high bandwidth of 10 MHz, low THD of −110 dB, and
fast settling time of 780 ns (maximum) to 0.001%. Offset drift and
gain drift are guaranteed to 1.2 V/°C and 10 ppm/°C, respectively,
for G = 1000. In addition to its wide input common voltage range,
it boasts a high common-mode rejection of 100 dB at G = 1000
from dc to 20 kHz. The combination of precision dc performance
coupled with high speed capabilities makes the AD8253 an
excellent candidate for data acquisition. Furthermore, this
monolithic solution simplifies design and manufacturing and
boosts performance of instrumentation by maintaining a tight
match of internal resistors and amplifiers.
The AD8253 user interface consists of a parallel port that allows
users to set the gain in one of two different ways (see Figure 1
for the functional block diagram). A 2-bit word sent via a bus
can be latched using the
transparent gain mode, where the state of logic levels at the gain
port determines the gain.
WR
input. An alternative is to use
AD8253
FUNCTIONAL BLOCK DIAGRAM
A1 A0DGND WR
4562
1
–IN
10
+IN
8 3
+V
80
70
G = 1000
60
50
G = 100
40
30
G = 10
GAIN (dB)
20
10
G = 1
0
–10
–20
1k 10k 100k 1M 10M 100M
Table 1. Instrumentation Amplifiers by Category
General
Purpose
Zero
Drift
AD82201 AD82311 AD620 AD6271 AD8250
AD8221 AD85531 AD621 AD6231 AD8251
AD8222 AD85551 AD524 AD82231 AD8253
AD82241 AD85561 AD526
AD8228 AD85571 AD624
1
Rail-to-rail output.
The AD8253 is available in a 10-lead MSOP package and is
specified over the −40°C to +85°C temperature range, making it
an excellent solution for applications where size and packing
density are important considerations.
LOGIC
AD8253
S
–V
S
Figure 1.
FREQUENCY (Hz)
Figure 2. Gain vs. Frequency
Mil
Grade
Low
Power
9
REF
7
OUT
06983-001
006983-023
High Speed
PGA
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2012 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
AD8253 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Diagram ........................................................................... 5
Absolute Maximum Ratings ............................................................ 6
Maximum Power Dissipation ..................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 16
Gain Selection ............................................................................. 16
Power Supply Regulation and Bypassing ................................ 18
Input Bias Current Return Path ............................................... 18
Input Protection ......................................................................... 18
Reference Terminal .................................................................... 19
Common-Mode Input Voltage Range ..................................... 19
Layout .......................................................................................... 19
RF Interference ........................................................................... 19
Driving an Analog-to-Digital Converter ................................ 20
Applications Information .............................................................. 21
Differential Output .................................................................... 21
Setting Gains with a Microcontroller ...................................... 21
Data Acquisition ......................................................................... 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
10/12—Rev. A to Rev. B
Changed Digital Input Voltage Low Maximum Parameter from
1.2 V to 2.1 V and Changed Digital Input Voltage High Typical
Parameter from 1.5 V to 2.8 V ........................................................ 4
Updated Outline Dimensions ....................................................... 23
8/08—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 23
7/08—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet AD8253
SPECIFICATIONS
+VS = +15 V, −VS = −15 V, V
Table 2.
Parameter Conditions Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR)
CMRR to 60 Hz with 1 kΩ Source Imbalance +IN = −IN = −10 V to +10 V
G = 1 80 100 dB
G = 10 96 120 dB
G = 100 100 120 dB
G = 1000 100 120 dB
CMRR to 20 kHz1 +IN = −IN = −10 V to +10 V
G = 1 80 dB
G = 10 96 dB
G = 100 100 dB
G = 1000 100 dB
NOISE
Voltage Noise, 1 kHz, RTI
G = 1 45 nV/√Hz
G = 10 12 nV/√Hz
G = 100 11 nV/√Hz
G = 1000 10 nV/√Hz
0.1 Hz to 10 Hz, RTI
G = 1 2.5 μV p-p
G = 10 1 μV p-p
G = 100 0.5 μV p-p
G = 1000 0.5 μV p-p
Current Noise, 1 kHz 5 pA/√Hz
Current Noise, 0.1 Hz to 10 Hz 60 pA p-p
VOLTAGE OFFSET
Offset RTI VOS G = 1, 10, 100, 1000 ±150 + 900/G μV
Over Temperature T = −40°C to +85°C ±210 + 900/G μV
Average TC T = −40°C to +85°C ±1.2 + 5/G μV/°C
Offset Referred to the Input vs. Supply (PSR) VS = ±5 V to ±15 V ±5 + 25/G μV/V
INPUT CURRENT
Input Bias Current 5 50 nA
Over Temperature2 T = −40°C to +85°C 40 60 nA
Average TC T = −40°C to +85°C 400 pA/°C
Input Offset Current 5 40 nA
Over Temperature T = −40°C to +85°C 40 nA
Average TC T = −40°C to +85°C 160 pA/°C
DYNAMIC RESPONSE
Small-Signal −3 dB Bandwidth
G = 1 10 MHz
G = 10 4 MHz
G = 100 550 kHz
G = 1000 60 kHz
Settling Time 0.01% ΔOUT = 10 V step
G = 1 700 ns
G = 10 680 ns
G = 100 1.5 μs
G = 1000 14 μs
= 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
REF
Rev. B | Page 3 of 24
AD8253 Data Sheet
Parameter Conditions Min Typ Max Unit
Settling Time 0.001% ΔOUT = 10 V step
G = 1 780 ns
G = 10 880 ns
G =100 1.8 μs
G = 1000 1.8 μs
Slew Rate
G = 1 20 V/μs
G = 10 20 V/μs
G = 100 12 V/μs
G = 1000 2 V/μs
Total Harmonic Distortion + Noise
f = 1 kHz, R
= 10 kΩ, ±10 V,
L
G = 1, 10 Hz to 22 kHz bandpass filter
GAIN
Gain Range G = 1, 10, 100, 1000 1 1000 V/V
Gain Error OUT = ±10 V
G = 1 0.03 %
G = 10, 100, 1000 0.04 %
Gain Nonlinearity OUT = −10 V to +10 V
G = 1 RL = 10 kΩ, 2 kΩ, 600 Ω 5 ppm
G = 10 RL = 10 kΩ, 2 kΩ, 600 Ω 3 ppm
G = 100 RL = 10 kΩ, 2 kΩ, 600 Ω 18 ppm
G = 1000 RL = 10 kΩ, 2 kΩ, 600 Ω 110 ppm
Gain vs. Temperature All gains 3 10 ppm/°C
INPUT
Input Impedance
Differential 4||1.25
Common Mode 1||5
Input Operating Voltage Range VS = ±5 V to ±15 V −VS + 1 +VS − 1.5 V
Over Temperature3 T = −40°C to +85°C −VS + 1.2 +VS − 1.7 V
OUTPUT
Output Swing −13.7 +13.6 V
Over Temperature4 T = −40°C to +85°C −13.7 +13.6 V
Short-Circuit Current 37 mA
REFERENCE INPUT
RIN 20 kΩ
IIN +IN, −IN, REF = 0 1 μA
Voltage Range −VS +VS V
Gain to Output 1 ± 0.0001 V/V
DIGITAL LOGIC
Digital Ground Voltage, DGND Referred to GND −VS + 4.25 0 +VS − 2.7 V
Digital Input Voltage Low Referred to GND DGND 2.1 V
Digital Input Voltage High Referred to GND 2.8 +VS V
Digital Input Current 1 μA
Gain Switching Time5 325 ns
t
See Figure 3 timing diagram 15 ns
SU
tHD 30 ns
t
-LOW
WR
t
-HIGH
WR
20 ns
15 ns
−110 dB
GΩpF
GΩpF
Rev. B | Page 4 of 24
Data Sheet AD8253
Parameter Conditions Min Typ Max Unit
POWER SUPPLY
Operating Range ±5 ±15 V
Quiescent Current, +IS 4.6 5.3 mA
Quiescent Current, −IS 4.5 5.3 mA
Over Temperature T = −40°C to +85°C 6 mA
TEMPERATURE RANGE
Specified Performance −40 +85 °C
1
See Figure 20 for CMRR vs. frequency for more information on typical performance over frequency.
2
Input bias current over temperature: minimum at hot and maximum at cold.
3
See Figure 30 for input voltage limit vs. supply voltage and temperature.
4
See Figure 32, Figure 33, and Figure 34 for output voltage swing vs. supply voltage and temperature for various loads.
5
Add time for the output to slew and settle to calculate the total time for a gain change.
TIMING DIAGRAM
WR
t
WR-HIGH
t
WR-LOW
A0, A1
t
SU
t
HD
6983-003
Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section)
Rev. B | Page 5 of 24
AD8253 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage ±17 V
Power Dissipation See Figure 4
Output Short-Circuit Current Indefinite1
Common-Mode Input Voltage ±VS
Differential Input Voltage ±VS
power is the voltage between the supply pins (V
quiescent current (I
midsupply, the total drive power is V
dissipated in the package and some of which is dissipated in the
load (V
The difference between the total drive power and the load
power is the drive power dissipated in the package.
Digital Logic Inputs ±VS
Storage Temperature Range –65°C to +125°C
Operating Temperature Range2 –40°C to +85°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 140°C
θJA (4-Layer JEDEC Standard Board) 112°C/W
Package Glass Transition Temperature 140°C
1
Assumes the load is referenced to midsupply.
2
Temperature for specified performance is −40°C to +85°C. For performance
to +125°C, see the Typical Performance Characteristics section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
In single-supply operation with R
case is V
Airflow increases heat dissipation, effectively reducing θ
addition, more metal directly in contact with the package leads
from metal traces through holes, ground, and power planes
reduces the θ
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature on a 4-layer JEDEC
standard board.
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8253 package is
limited by the associated rise in junction temperature (T
the die. The plastic encapsulating the die locally reaches the
junction temperature. At approximately 140°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8253. Exceeding
a junction temperature of 140°C for an extended period can
result in changes in silicon devices, potentially causing failure.
The still-air thermal properties of the package and PCB (θ
the ambient temperature (T
the package (P
) determine the junction temperature of the die.
D
), and the total power dissipated in
A
The junction temperature is calculated as
θPTT
J
The power dissipated in the package (P
D
A
JA
) is the sum of the
D
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
) on
J
JA
),
ESD CAUTION
). Assuming the load (RL) is referenced to
S
/2 × I
S
× I
OUT
P
= Quiescent Power + (Total Drive Power − Load Power)
D
D
OUT
2.00
1.75
1.50
1.25
1.00
0.75
0.50
MAXIMUM POW ER DISSIPATION (W )
0.25
0
–40 –20 120100806040200
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
).
OUT
V
V
IVP
SS
OUTS
R
2
L
= VS/2.
.
JA
AMBIENT TEMPERATURE (°C)
V
–
referenced to −VS, the worst
L
) times the
S
, some of which is
OUT
2
OUT
R
L
JA
. In
06983-004
Rev. B | Page 6 of 24
Data Sheet AD8253
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–IN
1
2
DGND
–V
A0
A1
3
S
4
5
AD8253
TOP VIEW
(Not to Scal e)
Figure 5. 10-Lead MSOP (RM-10) Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN Inverting Input Terminal. True differential input.
2 DGND Digital Ground.
3 −VS Negative Supply Terminal.
4 A0 Gain Setting Pin (LSB).
5 A1 Gain Setting Pin (MSB).
6
WR
Write Enable.
7 OUT Output Terminal.
8 +VS Positive Supply Terminal.
9 REF Reference Voltage Terminal.
10 +IN Noninverting Input Terminal. True differential input.
10
+IN
9
REF
+V
8
S
7
OUT
6
WR
06983-005
Rev. B | Page 7 of 24
AD8253 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA @ 25°C, +VS = +15 V, −VS = −15 V, RL = 10 k, unless otherwise noted.
210
180
150
120
90
NUMBER OF UNITS
60
30
0
–60 –40 –20 0 20
CMRR (µV/V)
06983-006
Figure 6. Typical Distribution of CMRR, G = 1
240
210
180
150
120
90
NUMBER OF UNITS
60
30
0
–60 –20–40
INPUT OFFSET CURRENT ( nA)
Figure 9. Typical Distribution of Input Offset Current
6040200
06983-009
180
150
120
90
NUMBER OF UNIT S
60
30
0
–200 –100
INPUT OFFSET VOLTAGE, V
Figure 7. Typical Distribution of Offset Voltage, V
300
250
200
OSI
, RTI (µV)
90
80
70
60
50
G = 100
40
NOISE (nV/Hz)
30
20
10
G = 1000
2001000
06983-007
OSI
0
1 100k
10 100 1k 10k
Figure 10. Voltage Spectral Density Noise vs. Frequency
G = 10
FREQUENCY (Hz)
G = 1
06983-010
150
NUMBER OF UNITS
100
50
0
–90 –30–60
INPUT BIAS CURRENT (nA)
Figure 8. Typical Distribution of Input Bias Current
9060300
06983-008
Rev. B | Page 8 of 24
1s/DIV2µV/DIV
Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1
06983-011
Loading...