ANALOG DEVICES AD 8253 ARMZ Datasheet

10 MHz, 20 V/μs, G = 1, 10, 100, 1000 iCMOS

Programmable Gain Instrumentation Amplifier

Data Sheet

FEATURES

Small package: 10-lead MSOP
Programmable gains: 1, 10, 100, 1000
Digital or pin-programmable gain setting
Wide supply: ±5 V to ±15 V

Excellent dc performance

High CMRR: 100 dB (minimum), G = 100
Low gain drift: 10 ppm/°C (maximum)
Low offset drift: 1.2 V/°C (maximum), G = 1000

Excellent ac performance

Fast settling time: 780 ns to 0.001% (maximum)
High slew rate: 20 V/µs (minimum)
Low distortion: −110 dB THD at 1 kHz,10 V swing
High CMRR over frequency: 100 dB to 20 kHz (minimum)
Low noise: 10 nV/√Hz, G = 1000 (maximum)
Low power: 4 mA

APPLICATIONS

Data acquisition
Biomedical analysis
Test and measurement

GENERAL DESCRIPTION

The AD8253 is an instrumentation amplifier with digitally
programmable gains that has gigaohm (GΩ) input impedance,
low output noise, and low distortion, making it suitable for
interfacing with sensors and driving high sample rate analog-to­digital converters (ADCs).

It has a high bandwidth of 10 MHz, low THD of −110 dB, and
fast settling time of 780 ns (maximum) to 0.001%. Offset drift and
gain drift are guaranteed to 1.2 V/°C and 10 ppm/°C, respectively,
for G = 1000. In addition to its wide input common voltage range,
it boasts a high common-mode rejection of 100 dB at G = 1000
from dc to 20 kHz. The combination of precision dc performance
coupled with high speed capabilities makes the AD8253 an
excellent candidate for data acquisition. Furthermore, this
monolithic solution simplifies design and manufacturing and
boosts performance of instrumentation by maintaining a tight
match of internal resistors and amplifiers.

The AD8253 user interface consists of a parallel port that allows
users to set the gain in one of two different ways (see Figure 1
for the functional block diagram). A 2-bit word sent via a bus
can be latched using the
transparent gain mode, where the state of logic levels at the gain
port determines the gain.

WR

input. An alternative is to use

AD8253

FUNCTIONAL BLOCK DIAGRAM

A1 A0DGND WR

4562

1

–IN

10

+IN

8 3

+V

80

70

G = 1000

60

50

G = 100

40

30

G = 10

GAIN (dB)

20

10

G = 1

0

–10

–20

1k 10k 100k 1M 10M 100M

Table 1. Instrumentation Amplifiers by Category

General
Purpose

Zero
Drift

AD82201 AD82311 AD620 AD6271 AD8250
AD8221 AD85531 AD621 AD6231 AD8251
AD8222 AD85551 AD524 AD82231 AD8253
AD82241 AD85561 AD526
AD8228 AD85571 AD624

1

Rail-to-rail output.

The AD8253 is available in a 10-lead MSOP package and is
specified over the −40°C to +85°C temperature range, making it
an excellent solution for applications where size and packing
density are important considerations.

LOGIC

AD8253

S

–V

S

Figure 1.

FREQUENCY (Hz)

Figure 2. Gain vs. Frequency

Mil
Grade

Low
Power

9

REF

7

OUT

06983-001

006983-023

High Speed
PGA

Rev. B Document Feedback

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Tel: [phone] ©2008–2012 Analog Devices, Inc. All rights reserved.

Technical Support www.analog.com

AD8253 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Diagram ........................................................................... 5

Absolute Maximum Ratings ............................................................ 6

Maximum Power Dissipation ..................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 16

Gain Selection ............................................................................. 16

Power Supply Regulation and Bypassing ................................ 18

Input Bias Current Return Path ............................................... 18

Input Protection ......................................................................... 18

Reference Terminal .................................................................... 19

Common-Mode Input Voltage Range ..................................... 19

Layout .......................................................................................... 19

RF Interference ........................................................................... 19

Driving an Analog-to-Digital Converter ................................ 20

Applications Information .............................................................. 21

Differential Output .................................................................... 21

Setting Gains with a Microcontroller ...................................... 21

Data Acquisition ......................................................................... 22

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 23

REVISION HISTORY

10/12—Rev. A to Rev. B

Changed Digital Input Voltage Low Maximum Parameter from

1.2 V to 2.1 V and Changed Digital Input Voltage High Typical

Parameter from 1.5 V to 2.8 V ........................................................ 4

Updated Outline Dimensions ....................................................... 23

8/08—Rev. 0 to Rev. A

Changes to Ordering Guide .......................................................... 23

7/08—Revision 0: Initial Version

Rev. B | Page 2 of 24

Data Sheet AD8253

SPECIFICATIONS

+VS = +15 V, −VS = −15 V, V

Table 2.

Parameter Conditions Min Typ Max Unit

COMMON-MODE REJECTION RATIO (CMRR)

CMRR to 60 Hz with 1 kΩ Source Imbalance +IN = −IN = −10 V to +10 V

G = 1 80 100 dB
G = 10 96 120 dB
G = 100 100 120 dB
G = 1000 100 120 dB

CMRR to 20 kHz1 +IN = −IN = −10 V to +10 V

G = 1 80 dB
G = 10 96 dB
G = 100 100 dB
G = 1000 100 dB

NOISE

Voltage Noise, 1 kHz, RTI

G = 1 45 nV/√Hz
G = 10 12 nV/√Hz
G = 100 11 nV/√Hz
G = 1000 10 nV/√Hz

0.1 Hz to 10 Hz, RTI
G = 1 2.5 μV p-p
G = 10 1 μV p-p
G = 100 0.5 μV p-p
G = 1000 0.5 μV p-p

Current Noise, 1 kHz 5 pA/√Hz
Current Noise, 0.1 Hz to 10 Hz 60 pA p-p

VOLTAGE OFFSET

Offset RTI VOS G = 1, 10, 100, 1000 ±150 + 900/G μV

Over Temperature T = −40°C to +85°C ±210 + 900/G μV
Average TC T = −40°C to +85°C ±1.2 + 5/G μV/°C

Offset Referred to the Input vs. Supply (PSR) VS = ±5 V to ±15 V ±5 + 25/G μV/V

INPUT CURRENT

Input Bias Current 5 50 nA

Over Temperature2 T = −40°C to +85°C 40 60 nA
Average TC T = −40°C to +85°C 400 pA/°C

Input Offset Current 5 40 nA

Over Temperature T = −40°C to +85°C 40 nA
Average TC T = −40°C to +85°C 160 pA/°C

DYNAMIC RESPONSE

Small-Signal −3 dB Bandwidth

G = 1 10 MHz
G = 10 4 MHz
G = 100 550 kHz
G = 1000 60 kHz

Settling Time 0.01% ΔOUT = 10 V step

G = 1 700 ns
G = 10 680 ns
G = 100 1.5 μs
G = 1000 14 μs

= 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.

REF

Rev. B | Page 3 of 24

AD8253 Data Sheet

Parameter Conditions Min Typ Max Unit

Settling Time 0.001% ΔOUT = 10 V step

G = 1 780 ns
G = 10 880 ns
G =100 1.8 μs
G = 1000 1.8 μs

Slew Rate

G = 1 20 V/μs
G = 10 20 V/μs
G = 100 12 V/μs
G = 1000 2 V/μs

Total Harmonic Distortion + Noise

f = 1 kHz, R

= 10 kΩ, ±10 V,

L

G = 1, 10 Hz to 22 kHz band­pass filter

GAIN

Gain Range G = 1, 10, 100, 1000 1 1000 V/V
Gain Error OUT = ±10 V

G = 1 0.03 %
G = 10, 100, 1000 0.04 %

Gain Nonlinearity OUT = −10 V to +10 V

G = 1 RL = 10 kΩ, 2 kΩ, 600 Ω 5 ppm
G = 10 RL = 10 kΩ, 2 kΩ, 600 Ω 3 ppm
G = 100 RL = 10 kΩ, 2 kΩ, 600 Ω 18 ppm
G = 1000 RL = 10 kΩ, 2 kΩ, 600 Ω 110 ppm

Gain vs. Temperature All gains 3 10 ppm/°C

INPUT

Input Impedance

Differential 4||1.25
Common Mode 1||5

Input Operating Voltage Range VS = ±5 V to ±15 V −VS + 1 +VS − 1.5 V
Over Temperature3 T = −40°C to +85°C −VS + 1.2 +VS − 1.7 V

OUTPUT

Output Swing −13.7 +13.6 V
Over Temperature4 T = −40°C to +85°C −13.7 +13.6 V
Short-Circuit Current 37 mA

REFERENCE INPUT

RIN 20 kΩ
IIN +IN, −IN, REF = 0 1 μA
Voltage Range −VS +VS V
Gain to Output 1 ± 0.0001 V/V

DIGITAL LOGIC

Digital Ground Voltage, DGND Referred to GND −VS + 4.25 0 +VS − 2.7 V
Digital Input Voltage Low Referred to GND DGND 2.1 V
Digital Input Voltage High Referred to GND 2.8 +VS V
Digital Input Current 1 μA
Gain Switching Time5 325 ns
t

See Figure 3 timing diagram 15 ns

SU

tHD 30 ns
t

-LOW

WR

t

-HIGH

WR

20 ns
15 ns

−110 dB

GΩpF
GΩpF

Rev. B | Page 4 of 24

Data Sheet AD8253

Parameter Conditions Min Typ Max Unit

POWER SUPPLY

Operating Range ±5 ±15 V
Quiescent Current, +IS 4.6 5.3 mA
Quiescent Current, −IS 4.5 5.3 mA
Over Temperature T = −40°C to +85°C 6 mA

TEMPERATURE RANGE

Specified Performance −40 +85 °C

1

See Figure 20 for CMRR vs. frequency for more information on typical performance over frequency.

2

Input bias current over temperature: minimum at hot and maximum at cold.

3

See Figure 30 for input voltage limit vs. supply voltage and temperature.

4

See Figure 32, Figure 33, and Figure 34 for output voltage swing vs. supply voltage and temperature for various loads.

5

Add time for the output to slew and settle to calculate the total time for a gain change.

TIMING DIAGRAM

WR

t

WR-HIGH

t

WR-LOW

A0, A1

t

SU

t

HD

6983-003

Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section)

Rev. B | Page 5 of 24

AD8253 Data Sheet





ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage ±17 V
Power Dissipation See Figure 4
Output Short-Circuit Current Indefinite1
Common-Mode Input Voltage ±VS
Differential Input Voltage ±VS

power is the voltage between the supply pins (V
quiescent current (I
midsupply, the total drive power is V
dissipated in the package and some of which is dissipated in the
load (V

The difference between the total drive power and the load
power is the drive power dissipated in the package.

Digital Logic Inputs ±VS
Storage Temperature Range –65°C to +125°C
Operating Temperature Range2 –40°C to +85°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 140°C
θJA (4-Layer JEDEC Standard Board) 112°C/W
Package Glass Transition Temperature 140°C

1

Assumes the load is referenced to midsupply.

2

Temperature for specified performance is −40°C to +85°C. For performance

to +125°C, see the Typical Performance Characteristics section.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any

In single-supply operation with R
case is V

Airflow increases heat dissipation, effectively reducing θ
addition, more metal directly in contact with the package leads
from metal traces through holes, ground, and power planes
reduces the θ

Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature on a 4-layer JEDEC

standard board.
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8253 package is
limited by the associated rise in junction temperature (T
the die. The plastic encapsulating the die locally reaches the
junction temperature. At approximately 140°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8253. Exceeding
a junction temperature of 140°C for an extended period can
result in changes in silicon devices, potentially causing failure.

The still-air thermal properties of the package and PCB (θ
the ambient temperature (T
the package (P

) determine the junction temperature of the die.

D

), and the total power dissipated in

A

The junction temperature is calculated as

θPTT 

J

The power dissipated in the package (P

D

A

JA

) is the sum of the

D

quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent

) on

J

JA

),

ESD CAUTION

). Assuming the load (RL) is referenced to

S

/2 × I

S

× I

OUT

P

= Quiescent Power + (Total Drive Power − Load Power)

D

D

OUT

2.00

1.75

1.50

1.25

1.00

0.75

0.50

MAXIMUM POW ER DISSIPATION (W )

0.25

0

–40 –20 120100806040200

Figure 4. Maximum Power Dissipation vs. Ambient Temperature

).

OUT



V

V





IVP

SS




OUTS



R

2

L

= VS/2.

.

JA

AMBIENT TEMPERATURE (°C)



V



–




referenced to −VS, the worst

L

) times the

S

, some of which is

OUT

2

OUT

R

L

JA

. In

06983-004

Rev. B | Page 6 of 24

Data Sheet AD8253

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

–IN

1

2

DGND

–V

A0

A1

3

S

4

5

AD8253

TOP VIEW

(Not to Scal e)

Figure 5. 10-Lead MSOP (RM-10) Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 −IN Inverting Input Terminal. True differential input.
2 DGND Digital Ground.
3 −VS Negative Supply Terminal.
4 A0 Gain Setting Pin (LSB).
5 A1 Gain Setting Pin (MSB).
6

WR

Write Enable.
7 OUT Output Terminal.
8 +VS Positive Supply Terminal.
9 REF Reference Voltage Terminal.
10 +IN Noninverting Input Terminal. True differential input.

10

+IN

9

REF

+V

8

S

7

OUT

6

WR

06983-005

Rev. B | Page 7 of 24

AD8253 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

TA @ 25°C, +VS = +15 V, −VS = −15 V, RL = 10 k, unless otherwise noted.

210

180

150

120

90

NUMBER OF UNITS

60

30

0

–60 –40 –20 0 20

CMRR (µV/V)

06983-006

Figure 6. Typical Distribution of CMRR, G = 1

240

210

180

150

120

90

NUMBER OF UNITS

60

30

0

–60 –20–40

INPUT OFFSET CURRENT ( nA)

Figure 9. Typical Distribution of Input Offset Current

6040200

06983-009

180

150

120

90

NUMBER OF UNIT S

60

30

0

–200 –100

INPUT OFFSET VOLTAGE, V

Figure 7. Typical Distribution of Offset Voltage, V

300

250

200

OSI

, RTI (µV)

90

80

70

60

50

G = 100

40

NOISE (nV/Hz)

30

20

10

G = 1000

2001000

06983-007

OSI

0

1 100k

10 100 1k 10k

Figure 10. Voltage Spectral Density Noise vs. Frequency

G = 10

FREQUENCY (Hz)

G = 1

06983-010

150

NUMBER OF UNITS

100

50

0

–90 –30–60

INPUT BIAS CURRENT (nA)

Figure 8. Typical Distribution of Input Bias Current

9060300

06983-008

Rev. B | Page 8 of 24

1s/DIV2µV/DIV

Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1

06983-011

Data Sheet AD8253

20

18

16

14

12

10

8

6

4

2

500nV/DIV

1s/DIV

06983-012

Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1000

18

16

14

12

10

8

NOISE (pA/ Hz)

6

4

2

0

1100k

10 100 1k 10k

FREQUENCY (Hz)

06983-013

Figure 13. Current Noise Spectral Density vs. Frequency

CHANGE IN INPUT OFFSET VOLTAGE (µV)

0

0.01 0.1 1 10
WARM-UP TIME (Minutes)

06983-015

Figure 15. Change in Input Offset Voltage vs. Warm-Up Time, G = 1000

140

120

G = 1000

100

80

60

PSRR (dB)

40

20

0

10 1M

100 1k 10k 100k

FREQUENCY (Hz)

G = 1

G = 100

G = 10

Figure 16. Positive PSRR vs. Frequency, RTI

06983-016

Figure 14. 0.1 Hz to 10 Hz Current Noise

140

120

100

80

60

PSRR (dB)

40

20

1s/DIV140pA/DIV

06983-014

0

10 1M

100 1k 10k 100k

G = 10

FREQUENCY (Hz)

G = 100

G = 1000

G = 1

06983-017

Figure 17. Negative PSRR vs. Frequency, RTI

Rev. B | Page 9 of 24

AD8253 Data Sheet

20

10

0

–10

–20

–30

–40

INPUT BIAS CURRENT (nA)

–50

–60

–15 –10 –5 0 5 10 15

I

+

B

IB–

I

OS

COMMON-MODE VOLTAGE (V)

12.0

10.5

9.0

7.5

6.0

4.5

3.0

1.5

0

INPUT OFF SET CURRENT (n A)

Figure 18. Input Bias Current and Offset Current vs. Common-Mode Voltage

30

25

20

15

120

100

80

60

CMRR (dB)

40

20

0

10

06983-018

100 1k 10k 100k 1M

FREQUENCY (Hz)

G = 1000

G = 100

G = 10

G = 1

06983-021

Figure 21. CMRR vs. Frequency, 1 kΩ Source Imbalance

15

10

5

10

5

OFFSET CURRENT (nA)

0

INPUT BIAS CURRENT AND

–5

–10

–60 –40 –20 0 20 40 60 80 100 120 140

I

–

B

IB+

I

OS

TEMPERATURE (°C)

Figure 19. Input Bias Current and Offset Current vs. Temperature

CMRR (dB)

120

100

80

60

40

20

0

10

100 1k 10k 100k 1M

FREQUENCY (Hz)

G = 1000

G = 100

G = 1

G = 10

Figure 20. CMRR vs. Frequency

0

CMRR (µV /V)

–5

–10

–15

–50 130

–30–101030507090110

06983-019

TEMPERATURE (° C)

06983-022

Figure 22. CMRR vs. Temperature, G = 1

80

70

G = 1000

60

50

G = 100

40

30

G = 10

GAIN (dB)

20

10

G = 1

0

–10

–20

1k 10k 100k 1M 10M 100M

06983-020

FREQUENCY (Hz)

006983-023

Figure 23. Gain vs. Frequency

Rev. B | Page 10 of 24

Data Sheet AD8253

40

400

30

20

10

0

–10

–20

NONLINEARITY (10ppm/DIV)

–30

–40

–10–8–6–4–20246810

OUTPUT VO LTAGE (V)

Figure 24. Gain Nonlinearity, G = 1, RL = 10 kΩ, 2 kΩ, 600 Ω

40

30

20

10

0

–10

–20

NONLINEARITY (10ppm/DIV)

–30

–40

–10–8–6–4–20246810

OUTPUT VO LTAGE (V)

Figure 25. Gain Nonlinearity, G = 10, RL = 10 kΩ, 2 kΩ, 600 Ω

300

200

100

0

–100

–200

NONLINEARITY (10 ppm/ DIV)

–300

–400

–10–8–6–4–20246810

06983-024

OUTPUT VOLTAGE (V)

06983-027

Figure 27. Gain Nonlinearity, G = 1000, RL = 10 kΩ, 2 kΩ, 600 Ω

16

12

8

–14.1V, +7.3V

4

0

–4

–8

INPUT COMMON-MODE VOLTAGE (V)

–12

–16

06983-025

–16 16

–4V, +1.9V

–4V, –1.9V

–14.1V, –7.3V +13.8V, –7.3V

–12 –8 –4 0 4 8 12

0V, +13.9V

VS, ±15V

0V, +3.8V

VS= ±5V

0V, –4.2V

0V, –14.2V

OUTPUT VOLTAGE (V)

+3.8V, +1.9V

+3.8V, –1.9V

+13.8V, +7.3V

06983-028

Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 1

80

60

40

20

0

–20

–40

NONLINEARITY (10ppm/ DIV)

–60

–80

–10–8–6–4–20246810

Figure 26. Gain Nonlinearity, G = 100, R

OUTPUT VOLTAGE (V)

= 10 kΩ, 2 kΩ, 600 Ω

L

06983-026

Figure 29. Input Common-Mode Voltage Range vs. Output Voltage, G = 1000

Rev. B | Page 11 of 24

16

12

8

–14.4V, +6V

4

0

–4

–8

INPUT COMMON-MODE VOL TAGE (V)

–12

–16

–16 16

–4.3V, +2V

–4.3V, –2V

–14.4V, –6V

–12 –8 –4 0 4 8 12

0V, +13.7V

VS ±15V

0V, +3.8V

VS= ±5V

0V, –4.2V

0V, –14.1V

OUTPUT VOLTAGE (V)

+14.1V, +6V

+4.3V, +2V

+4.3V, –2V

+14.1V, –6V

06983-029

AD8253 Data Sheet

V

V

V

V

+

S

–1

–2

+25°C

+125°C

+85°C

–40°C

+

–0.2

–0.4

–0.6

–0.8

–1.0

S

+125°C

+85°C

5

+

2

°

C

–40°C

INPUT VOLTAGE (V)

+2

REFERRED TO SUPPLY VOLTAGES

+1

–V

+125°C

S

416

6 8 10 12 14

–40°C

+85°C

SUPPLY VOLTAGE (±VS)

Figure 30. Input Voltage Limit vs. Supply Voltage, G = 1, V

25

FAU LT

CONDITIO N

20

(OVER-DRIVEN

INPUT)

15

G=1000

10

5

+IN +IN

0

–5

CURRENT (mA)

–10

–15

–20

–25

–1

–10

+Vs

–Vs

–100µ

10µ

100µ

–10µ/

–1m

–10m

–100m

DIFFERENTIAL INPUT VOLTAGE (V)

1m

+25°C

= 0 V, RL = 10 kΩ

REF

FAU LT

CONDIT ION

(OVER-DRIVEN

INPUT)

G=1000

10m

100m

Figure 31. Fault Current Draw vs. Input Voltage, G = 1000, RL = 10 kΩ

+1.0

+0.8

OUTPUT VOLT AGE SWING (V)

+0.6

REFERRED TO SUPPLY VOLTAGES

+0.4

+0.2

–V

S

416

06983-030

+85°C

+125°C

6 8 10 12 14

SUPPLY VOLTAGE (±VS)

+

–40°C

2

°

C

5

06983-033

Figure 33. Output Voltage Swing vs. Supply Voltage, G =1000, RL = 10 kΩ

15

10

5

–IN–IN

1

10

06983-031

0

–5

OUTPUT VOLTAGE SWING (V)

+

–10

–15

100 10k

2

5

°

–40°C

+85°C

C

5

+

2

°

C

–40°C

+125°C

+85°C

+125°C

LOAD RESIST ANCE ()

1k

06983-034

Figure 34. Output Voltage Swing vs. Load Resistance

+

S

–0.2

–0.4

–0.6

–0.8

–1.0

+85°C

–1.2

+1.2

+1.0

+0.8

OUTPUT VO LTAGE SWING (V)

+0.6

REFERRED TO SUPPLY VOL TAGES

+0.4

+0.2

–V

S

416

+

–40°C

6 8 10 12 14

+125°C

5

2

°

C

–40°C

+

°

5

2

C

+125°C

SUPPLY VOLTAGE (±VS)

+85°C

Figure 32. Output Voltage Swing vs. Supply Voltage, G = 1000, RL = 2 kΩ

06983-032

+

S

–0.4

–0.8

–1.2

–1.6

–2.0

+2.0

+1.6

+1.2

OUTPUT VOLTAGE SWING (V)

+0.8

REFERRED TO SUPPLY VOLTAGES

+0.4

–V

S

416

6 8 10 12 14

OUTPUT CURRENT (mA)

–40°C
+25°C
+85°C
+125°C

06983-035

Figure 35. Output Voltage Swing vs. Output Current

Rev. B | Page 12 of 24

Data Sheet AD8253

NO

LOAD

47pF

100pF

2µs/DIV20mV/DIV

06983-036

Figure 36. Small-Signal Pulse Response for Various Capacitive Loads, G = 1

5V/DIV

664ns TO 0. 01%

0.002%/DIV

744ns TO 0. 001%

5V/DIV

1392ns TO 0.01%

0.002%/DIV

1712ns TO 0. 001%

2µs/DIV

TIME (µs)

Figure 39. Large-Signal Pulse Response and Settling Time,

= 10 kΩ

L

5V/DIV

0.002%/DIV

G = 100, R

12.88µs TO 0.01%

16.64µs TO 0.001%

06983-039

2µs/DIV

TIME (µs)

06983-037

Figure 37. Large-Signal Pulse Response and Settling Time, G = 1, RL = 10 kΩ

5V/DIV

656ns TO 0. 01%

0.002%/DIV

840ns TO 0. 001%

TIME (µs)

2µs/DIV

06983-038

Figure 38. Large-Signal Pulse Response and Settling Time,

G = 10, R

= 10 kΩ

L

10µs/DIV

TIME (µs)

Figure 40. Large-Signal Pulse Response and Settling Time,

G = 1000, R

20mV/DIV 2µs/DIV

= 10 kΩ

L

Figure 41. Small-Signal Response,

= 2 kΩ, CL = 100

G = 1, R

L

06983-040

06983-041

Rev. B | Page 13 of 24

AD8253 Data Sheet

1400

1200

1000

SETTL ED TO 0.001%

SETTL ED TO 0.01%

4 6 8 10 12 14 16 18

STEP SIZE (V)

SETTL ED TO 0.001%

SETTL ED TO 0.01%

06983-045

20mV/DIV 2µs/DIV

Figure 42. Small-Signal Response,

G = 10, R

= 2 kΩ, CL = 100 pF

L

800

600

TIME (ns)

400

200

06983-042

0

220

Figure 45. Settling Time vs. Step Size, G = 1, RL = 10 kΩ

1400

1200

1000

800

600

TIME (ns)

20mV/DIV 20µs/DIV

Figure 43. Small-Signal Response,

G = 100, R

20mV/DIV 20µs/ DIV

Figure 44. Small-Signal Response, G = 1000, R

= 2 kΩ, CL = 100 pF

L

= 2 kΩ, CL = 100 pF

L

400

200

06983-043

0

220

4 6 8 1012141618

STEP SIZE (V)

06983-046

Figure 46. Settling Time vs. Step Size, G = 10, RL = 10 kΩ

2000

1800

1600

1400

1200

1000

TIME (ns)

800

600

400

06983-044

200

0

220

4 6 8 10 12 14 16 18

SETTL ED TO 0.001%

SETTL ED TO 0.01%

STEP SIZE (V)

06983-047

Figure 47. Settling Time vs. Step Size, G = 100, RL = 10 kΩ

Rev. B | Page 14 of 24

Data Sheet AD8253

20

18

16

14

12

10

TIME (µs)

8

6

4

2

0

220

4 6 8 1012141618

SETTL ED TO 0.001%

SETTLED TO 0.01%

STEP SIZE (V)

06983-048

Figure 48. Settling Time vs. Step Size, G = 1000, RL = 10 kΩ

0

–10

–20

–30

–40

–50

–60

–70

THD + N (dB)

–80

–90

–100

–110

–120

10 1M

G = 1000

G = 100

G = 10

G = 1

100 1k 10k 100k

FREQUENCY (Hz)

Figure 50. Total Harmonic Distortion vs. Frequency,

10 Hz to 500 kHz Band-Pass Filter, 2 kΩ Load

06983-050

0

–10

–20

–30

–40

–50

–60

–70

THD + N (dB)

–80

–90

–100

–110

–120

10 1M

G = 1000

G = 100

G = 10

G = 1

100 1k 10k 100k

FREQUENCY (Hz)

Figure 49. Total Harmonic Distortion vs. Frequency,

10 Hz to 22 kHz Band-Pass Filter, 2 kΩ Load

06983-049

Rev. B | Page 15 of 24

AD8253 Data Sheet

–

V

V

V

V

THEORY OF OPERATION

+

S

+V

S

IN

+IN

1.2k

–V

S

+V

S

1.2k

–V

S

The AD8253 is a monolithic instrumentation amplifier based
on the classic 3-op-amp topology, as shown in Figure 51. It is
fabricated on the Analog Devices, Inc., proprietary iCMOS®
process that provides precision linear performance and a robust
digital interface. A parallel interface allows users to digitally
program gains of 1, 10, 100, and 1000. Gain control is achieved
by switching resistors in an internal precision resistor array (as
shown in Figure 51).

All internal amplifiers employ distortion cancellation circuitry
and achieve high linearity and ultralow THD. Laser-trimmed
resistors allow for a maximum gain error of less than 0.03% for
G = 1 and a minimum CMRR of 100 dB for G = 1000. A pinout
optimized for high CMRR over frequency enables the AD8253
to offer a guaranteed minimum CMRR over frequency of 80 dB
at 20 kHz (G = 1). The balanced input reduces the parasitics
that in the past had adversely affected CMRR performance.

GAIN SELECTION

This section describes how to configure the AD8253 for basic
operation. Logic low and logic high voltage limits are listed in
the Specifications section. Typically, logic low is 0 V and logic
high is 5 V; both voltages are measured with respect to DGND.
Refer to the specifications table (Table 2) for the permissible
voltage range of DGND. The gain of the AD8253 can be set
using two methods: transparent gain mode and latched gain
mode. Regardless of the mode, pull-up or pull-down resistors
should be used to provide a well-defined voltage at the A0 and
A1 pins.

–V

S

A1

DIGITAL
GAIN
CONTROL

A2

+V

S

WR

–V

S

Figure 51. Simplified Schematic

2.2k

2.2k

+

S

A1A0

–V

S

10k 10k

+V

S

OUT

–V

S

+V

S

REF

–V

S

6983-061

+V

–V

10k

S

S

A3

10k

DGND

Transparent Gain Mode

The easiest way to set the gain is to program it directly via a
logic high or logic low voltage applied to A0 and A1. Figure 52
shows an example of this gain setting method, referred to through­out the data sheet as transparent gain mode. Tie

WR
negative supply to engage transparent gain mode. In this mode,
any change in voltage applied to A0 and A1 from logic low to
logic high, or vice versa, immediately results in a gain change.
Table 5 is the truth table for transparent gain mode, and Figure 52

shows the AD8253 configured in transparent gain mode.

+15

10F0.1µF

+IN

WR

–15V

A1

+5V

A0

+5V
G = 1000

AD8253

REF

–IN

10F0.1µF

NOTE:

1. IN TRANSPARENT GAIN MODE, WR IS TIED TO 

THE VOLT AGE LEVELS ON A0 AND A1 DETE RMINE
THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE
SET TO LOGIC HIGH, RESULTING IN A GAIN OF 1000.

DGND DGND

–15V

.

S

Figure 52. Transparent Gain Mode, A0 and A1 = High, G = 1000

to the

6983-051

Rev. B | Page 16 of 24

Data Sheet AD8253

V

Table 5. Truth Table Logic Levels for Transparent Gain Mode

WR

A1 A0 Gain

−VS Low Low 1

−VS Low High 10

−VS High Low 100

−VS High High 1000

Latched Gain Mode

Some applications have multiple programmable devices such
as multiplexers or other programmable gain instrumentation
amplifiers on the same PCB. In such cases, devices can share a
data bus. The gain of the AD8253 can be set using

WR

as a latch,
allowing other devices to share A0 and A1. Figure 53 shows a
schematic using this method, known as latched gain mode. The
AD8253 is in this mode when

WR

is held at logic high or logic

low, typically 5 V and 0 V, respectively. The voltages on A0 and A1

WR

are read on the downward edge of the

signal as it transitions
from logic high to logic low. This latches in the logic levels on
A0 and A1, resulting in a gain change. See the truth table listing
in Table 6 for more on these gain changes.

+15

10F0.1µF

+IN

WR

+

A1

A0

G = PREVIOUS
STATE

WR

A1

A0

+5V
0V

+5V
0V

+5V
0V

G = 1000

AD8253

–IN

10F0.1µF

NOTE:

1. ON THE DOWNWARD EDGE OF WR, AS I T TRANSITI ONS
FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0
AND A1 ARE READ AND LATCHED IN, RESULTING IN A
GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SW ITCHES T O G = 1000.

–

–15V

Figure 53. Latched Gain Mode, G = 1000

REF

DGND DGND

06983-052

Table 6. Truth Table Logic Levels for Latched Gain Mode

WR

A1 A0 Gain

High to Low Low Low Change to 1
High to Low Low High Change to 10
High to Low High Low Change to 100
High to Low High High Change to 1000
Low to Low X1 X
Low to High X1 X
High to High X1 X

1

X = don’t care.

1

No change

1

No change

1

No change

On power-up, the AD8253 defaults to a gain of 1 when in
latched gain mode. In contrast, if the AD8253 is configured in
transparent gain mode, it starts at the gain indicated by the
voltage levels on A0 and A1 on power-up.

Timing for Latched Gain Mode

In latched gain mode, logic levels at A0 and A1 must be held for
a minimum setup time, t

, before the downward edge of WR

SU

latches in the gain. Similarly, they must be held for a minimum
hold time, t
the gain is latched in correctly. After t

, after the downward edge of WR to ensure that

HD

, A0 and A1 may change

HD

logic levels, but the gain does not change until the next downward

WR

edge of
is t

WR-HIGH

. The minimum duration that WR can be held high

, and t

is the minimum duration that WR can

WR-LOW

be held low. Digital timing specifications are listed in Table 2.
The time required for a gain change is dominated by the settling
time of the amplifier. A timing diagram is shown in Figure 54.

When sharing a data bus with other devices, logic levels applied
to those devices can potentially feed through to the output of
the AD8253. Feedthrough can be minimized by decreasing the
edge rate of the logic signals. Furthermore, careful layout of the
PCB also reduces coupling between the digital and analog
portions of the board.

WR

A0, A1

t

WR-HIGH

t

SU

t

WR-LOW

t

HD

6983-053

Figure 54. Timing Diagram for Latched Gain Mode

Rev. B | Page 17 of 24

AD8253 Data Sheet

V

POWER SUPPLY REGULATION AND BYPASSING

The AD8253 has high PSRR. However, for optimal performance,
a stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect per­formance. As in all linear circuits, bypass capacitors must be
used to decouple the amplifier.

Place a 0.1 µF capacitor close to each supply pin. A 10 µF tantalum
capacitor can be used farther away from the part (see Figure 55)
and, in most cases, it can be shared by other precision integrated
circuits.

+

S

REF

10µF

LOAD

10µF

V

OUT

06983-054

0.1µF

WR

A1

+IN

A0

AD8253

–IN

DGND

0.1µF

DGND

–V

S

Figure 55. Supply Decoupling, REF, and Output Referred to Ground

INPUT BIAS CURRENT RETURN PATH

The AD8253 input bias current must have a return path to its
local analog ground. When the source, such as a thermocouple,
cannot provide a return current path, one should be created
(see Figure 56).

INCORRECT

+V

S

AD8253

–V

TRANSFORMER

S

+V

S

AD8253

–V

THERMOCOUPL E

C

C

CAPACITIVEL Y COUPLED

S

+V

S

AD8253

–V

S

REF

Figure 56. Creating an I

REF

REF

10M

f

=

HIGH- PASS

2RC

CAPACITIVEL Y COUPLED

CORRECT

TRANSFORMER

THERMOCOUPL E

C

R

1

C

R

Path

BIAS

+V

S

AD8253

–V

S

+V

S

AD8253

–V

S

+V

S

AD8253

–V

S

REF

REF

REF

INPUT PROTECTION

All terminals of the AD8253 are protected against ESD. An external
resistor should be used in series with each of the inputs to limit
current for voltages greater than 0.5 V beyond either supply rail.
In such a case, the AD8253 safely handles a continuous 6 mA
current at room temperature. For applications where the AD8253
encounters extreme overload voltages, external series resistors
and low leakage diode clamps such as BAV199Ls, FJH1100s, or
SP720s should be used.

06983-055

Rev. B | Page 18 of 24

Data Sheet AD8253

REFERENCE TERMINAL

The reference terminal, REF, is at one end of a 10 k resistor
(see Figure 51). The instrumentation amplifier output is
referenced to the voltage on the REF terminal; this is useful
when the output signal needs to be offset to voltages other than
its local analog ground. For example, a voltage source can be
tied to the REF pin to level shift the output so that the AD8253
can interface with a single-supply ADC. The allowable reference
voltage range is a function of the gain, common-mode input,
and supply voltages. The REF pin should not exceed either +V
or −V

by more than 0.5 V.

S

S

For best performance, especially in cases where the output is
not measured with respect to the REF terminal, source imped­ance to the REF terminal should be kept low because parasitic
resistance can adversely affect CMRR and gain accuracy.

INCORRECT

AD8253

V

REF

Figure 57. Driving the Reference Pin

V

REF

CORRECT

AD8253

+

OP1177

–

6983-056

COMMON-MODE INPUT VOLTAGE RANGE

The 3-op-amp architecture of the AD8253 applies gain and then
removes the common-mode voltage. Therefore, internal nodes
in the AD8253 experience a combination of both the gained
signal and the common-mode signal. This combined signal can
be limited by the voltage supplies even when the individual
input and output signals are not. Figure 28 and Figure 29 show
the allowable common-mode input voltage ranges for various
output voltages, supply voltages, and gains.

LAYOUT

Grounding

In mixed-signal circuits, low level analog signals need to be
isolated from the noisy digital environment. Designing with the
AD8253 is no exception. Its supply voltages are referenced to an
analog ground. Its digital circuit is referenced to a digital ground.
Although it is convenient to tie both grounds to a single ground
plane, the current traveling through the ground wires and PC
board can cause an error. Therefore, use separate analog and
digital ground planes. Only at one point, star ground, should
analog and digital ground meet.

The output voltage of the AD8253 develops with respect to the
potential on the reference terminal. Take care to tie REF to the
appropriate local analog ground or to connect it to a voltage that
is referenced to the local analog ground.

Coupling Noise

To prevent coupling noise onto the AD8253, follow these
guidelines:

 Do not run digital lines under the device.
 Run the analog ground plane under the AD8253.
 Shield fast-switching signals with digital ground to avoid

radiating noise to other sections of the board, and never
run them near analog signal paths.

 Avoid crossover of digital and analog signals.
 Connect digital and analog ground at one point only

(typically under the ADC).

 Power supply lines should use large traces to ensure a low

impedance path. Decoupling is necessary; follow the
guidelines listed in the Power Supply Regulation and
Bypassing section.

Common-Mode Rejection

The AD8253 has high CMRR over frequency, giving it greater
immunity to disturbances, such as line noise and its associated
harmonics, in contrast to typical in amps whose CMRR falls off
around 200 Hz. They often need common-mode filters at the
inputs to compensate for this shortcoming. The AD8253 is able
to reject CMRR over a greater frequency range, reducing the
need for input common-mode filtering.

Careful board layout maximizes system performance. To maintain
high CMRR over frequency, lay out the input traces symmetrically.
Ensure that the traces maintain resistive and capacitive balance;
this holds for additional PCB metal layers under the input pins
and traces. Source resistance and capacitance should be placed
as close to the inputs as possible. Should a trace cross the inputs
(from another layer), it should be routed perpendicular to the
input traces.

RF INTERFERENCE

RF rectification is often a problem when amplifiers are used in
applications where there are strong RF signals. The disturbance
can appear as a small dc offset voltage. High frequency signals
can be filtered with a low-pass RC network placed at the input
of the instrumentation amplifier, as shown in Figure 58. The
filter limits the input signal bandwidth according to the following
relationship:

1

RC

1

2π2

D

C

)CC(R



C

FilterFreq

FilterFreqπ2

where C

≥ 10 CC.

D

DIFF

CM



Rev. B | Page 19 of 24

AD8253 Data Sheet

V

V

–

C

R

R

C

C

D

C

C

0.1µF

+IN

0.1µF

–IN

+15

AD8253

–15V

REF

10µF

10µF

V

OUT

6983-057

Figure 58. RFI Suppression

Val u es o f R a nd CC should be chosen to minimize RFI.
Mismatch between the R × C

at negative input degrades the CMRR of the AD8253.

R × C

C

By using a value of C

, the effect of the mismatch is reduced and performance is

C

C

D

at the positive input and the

C

that is 10 times larger than the value of

improved.

DRIVING AN ANALOG-TO-DIGITAL CONVERTER

An instrumentation amplifier is often used in front of an analog­to-digital converter to provide CMRR. Usually, instrumentation
amplifiers require a buffer to drive an ADC. However, the low
output noise, low distortion, and low settle time of the AD8253
make it an excellent ADC driver.

In this example, a 1 nF capacitor and a 49.9 Ω resistor create an
antialiasing filter for the AD7612. The 1 nF capacitor also serves
to store and deliver necessary charge to the switched capacitor
input of the ADC. The 49.9  series resistor reduces the burden
of the 1 nF load from the amplifier and isolates it from the kickback
current injected from the switched capacitor input of the AD7612.
Selecting too small a resistor improves the correlation between
the voltage at the output of the AD8253 and the voltage at the
input of the AD7612 but may destabilize the AD8253. A trade­off must be made between selecting a resistor small enough to
maintain accuracy and large enough to maintain stability.

+15

10F0.1µF

+IN

IN

10F0.1µF

WR

A1

A0

AD8253

REF

–15V

Figure 59. Driving an ADC

49.9

1nF

DGNDDGND

+12V –12V

0.1F

AD7612

+5V

ADR435

0.1F

06983-058

Rev. B | Page 20 of 24

Data Sheet AD8253

V

–

V

V

APPLICATIONS INFORMATION

DIFFERENTIAL OUTPUT

In certain applications, it is necessary to create a differential
signal. High resolution analog-to-digital converters often require a
differential input. In other cases, transmission over a long distance
can require differential signals for better immunity to interference.

Figure 61 shows how to configure the AD8253 to output a
differential signal. An op amp, the AD8675, is used in an
inverting topology to create a differential voltage. V
output midpoint according to the equation shown in the figure.
Errors from the op amp are common to both outputs and are
thus common mode. Likewise, errors from using mismatched
resistors cause a common-mode dc offset error. Such errors are
rejected in differential signal processing by differential input
ADCs or instrumentation amplifiers.

When using this circuit to drive a differential ADC, V
set using a resistor divider from the ADC reference to make the
output ratiometric with the ADC.

0.1F

AMPLITUDE

+5

–5V

+IN

V

IN

REF

+15

WR

+

AD8253

G = 1

–

sets the

can be

REF

A1

A0

REF

4.99k

SETTING GAINS WITH A MICROCONTROLLER

+15

V

OUT

10F0.1µF

+IN

IN

10F0.1µF

Figure 60. Programming Gain Using a Microcontroller

A = VIN + V

2

AMPLITUDE

REF

+2.5V

–2.5V

+

AD8253

–

–15V

0V

WR

A1

A0

CONTROLL ER

REF

DGNDDGND

TIME

MICRO-

06983-059

+15V

10F

–15V

0.1F

DGND

–15V

4.99k

10F

DGND

–15V

56pF

0.1µF

Figure 61. Differential Output with Level Shift

AD8675

B = –VIN + V

V

OUT

0.1µF

+–

+15V

2

V
0V

AMPLITUDE

REF

REF

+2.5V

–2.5V

0V

0V

TIME

06983-060

Rev. B | Page 21 of 24

AD8253 Data Sheet

DATA ACQUISITION

The AD8253 makes an excellent instrumentation amplifier
for use in data acquisition systems. Its wide bandwidth, low
distortion, low settling time, and low noise enable it to
condition signals in front of a variety of 16-bit ADCs.

Figure 63 shows the AD825x as part of a total data acquisition
system. The quick slew rate of the AD8253 allows it to condition
rapidly changing signals from the multiplexed inputs. An FPGA
controls the AD7612, AD8253, and ADG1209. In addition,
mechanical switches and jumpers allow users to pin strap the
gains when in transparent gain mode.

This system achieved −116 dB of THD at 1 kHz and a signal-to­noise ratio of 91 dB during testing, as shown in Figure 62.

+CH1

+CH2

+CH3

+CH4

–CH4

–CH3

–CH2

–CH1

806
806

806

806

806

806
806

806

0.1µF

0.1µF

+12V

14

V

DD

4

S1A

5

S2A

6

S3A

S4A

7

ADG1209

10

S4B

11

S3B

12

S2B

13

S1B

V

SS

3

–12V

EN

A1

2

GND

16

DA

DB

A0

1

+12V

8

9

15

JMP

+

10µF 10µF

DGND

0

0

+5V

2k

0

0

GND

–12V

+

DGND

DGND

C

C

+IN

10

C

D

–IN

1

C

C

C3

0.1µF

2

6

WR

+

AD8253

–

+V

S

8

+12V –12V

0
–10
–20

–30
–40
–50
–60
–70
–80

–90

–100
–110

AMPLITUDE (dB)

–120
–130
–140

–150
–160
–170

050

5 1015202530354045

FREQUENCY (kHz)

06983-062

Figure 62. FFT of the AD825x in a Total Data Acquisition System

Using the AD8253 1 kHz Signal

JMP

JMP

+5V

+5V

7

DGND

2k

DGND

VOUT

0 49.9

JMP

5

4

A1

A0

REF

9

–V

S

3

C4

0.1µF

2k

–V

S

ALTERA

EPF6010ATC144-3

+IN

AD7612

1nF

ADR435

DGND

JMP

+5V

R8
2k

DGND

06983-067

Figure 63. Schematic of ADG1209, AD8253, and AD7612 Used with the AD825x in a Total Data Acquisition System

Rev. B | Page 22 of 24

Data Sheet AD8253

OUTLINE DIMENSIONS

3.10

3.00

2.90

10

6

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

1

0.50 BSC

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 64. 10-Lead Mini Small Outline Package [MSOP]

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option Branding

AD8253ARMZ –40°C to +85°C 10-Lead MSOP RM-10 Y0K
AD8253ARMZ-RL –40°C to +85°C 10-Lead MSOP RM-10 Y0K
AD8253ARMZ-R7 –40°C to +85°C 10-Lead MSOP RM-10 Y0K
AD8253-EVALZ Evaluation Board

1

Z = RoHS Compliant Part.

5.15

4.90

4.65

5

15° MAX

6°
0°

0.23

0.13

0.30

0.15

1.10 MAX

(RM-10)

Dimensions shown in millimeters

0.70

0.55

0.40

091709-A

Rev. B | Page 23 of 24

AD8253 Data Sheet

NOTES

©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06983-0-10/12(B)

Rev. B | Page 24 of 24