Page 1
Low Power, FET-Input Op Amp
Data Sheet
AD824
1
2
14
13
5
6
7
10
9
8
3
4
12
11
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
AD824
TOP VIEW
(Not to S cale)
00875-001
FEATURES
Single supply operation: 3 V to 30 V
Very low input bias current: 2 pA
Wide input voltage range
Rail-to-rail output swing
Low supply current per amplifier: 500 µA
Wide bandwidth: 2 MHz
Slew rate: 2 V/µs
No phase reversal
APPLICATIONS
Photo diode preamplifier
Battery powered instrumentation
Power supply control and protection
Medical instrumentation
Remote sensors
Low voltage strain gage amplifiers
DAC output amplifier
Single Supply, Rail-to-Rail
PIN CONFIGURATION
Figure 1. 14-Lead SOIC (R Suffix)
GENERAL DESCRIPTION
The AD824 is a quad, FET input, single supply amplifier,
featuring rail-to-rail outputs. The combination of FET inputs
and rail-to-rail outputs makes the AD824 useful in a wide
variety of low voltage applications where low input current is
a primary consideration.
The AD824 is guaranteed to operate from a 3 V single supply
up to ±15 V dual supplies. AD824AR-3V parametric
performance at 3 V is fully guaranteed.
Fabricated on Analog Devices, Inc., complementary bipolar
process, the AD824 has a unique input stage that allows the
input voltage to safely extend beyond the negative supply and
to the positive supply without any phase inversion or latch-up.
The output voltage swings to within 15 mV of the supplies.
Capacitive loads to 350 pF can be handled without oscillation.
The FET input combined with laser trimming provides an input
that has extremely low bias currents with guaranteed offsets
below 1 mV. This enables high accuracy designs even with high
source impedances. Precision is combined with low noise,
making the AD824 ideal for use in battery powered medical
equipment.
Applications for the AD824 include portable medical
equipment, photo diode preamplifiers, and high impedance
transducer amplifiers.
The ability of the output to swing rail-to-rail enables designers
to build multistage filters in single supply systems and maintain
high signal-to-noise ratios.
The AD824 is specified over the extended industrial (−40°C to
+85°C) temperature range and is available in narrow 14-lead
SOIC package.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsi bility is as sumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Anal og Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Page 2
AD824 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Configuration ............................................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Specifications ............................................................... 3
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 12
REVISION HISTORY
4/15—Rev. D to Rev. E
Change to Figure 1 Caption ............................................................ 1
5/14—Rev. C to Rev. D
Updated Format .................................................................. Universal
Removed 16-Lead SOIC Package (Throughout) .......................... 1
Deleted Wafer Test Limits Section ................................................. 5
Deleted AD824 SPICE Macro-model Section ............................ 15
Changes to Ordering Guide .......................................................... 16
2/03—Rev. B to Rev. C
Deleted N Package .............................................................. Universal
Edits to General Description ........................................................... 1
Edits to Absolute Maximum Ratings ............................................. 5
Edits to Ordering Guide .................................................................. 5
Edits to Figure 4 .............................................................................. 12
Edits to Figure 8 .............................................................................. 13
Updated Outline Dimensions ....................................................... 16
1/02—Rev. A to Rev. B
Edits to Electrical Specifications ................................................. 2, 3
Edits to Absolute Maximum Ratings ............................................. 5
Edits to Ordering Guide .................................................................. 5
Deleted Dice Characteristics ........................................................... 5
Input Characteristics .................................................................. 12
Output Characteristics............................................................... 12
Applications Information .............................................................. 13
Single Supply Voltage-to-Frequency Converter ..................... 13
Single Supply Programmable Gain Instrumentation
Amplifier ..................................................................................... 13
3 V, Single Supply Stereo Headphone Driver ......................... 14
Low Dropout Bipolar Bridge Driver ........................................ 14
A 3.3 V/5 V Precision Sample-and-Hold Amplifier .............. 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
Rev. E | Page 2 of 16
Page 3
Data Sheet AD824
RL = 10 kΩ
50
100 V/mV
T
to T
±10 mA
Phase Margin
φo
No load
50 Degrees
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
At VS = 5.0 V, VCM = 0 V, V
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage (AD824A) VOS 0.1 1.0 mV
T
Input Bias Current IB 2 12 pA
T
Input Offset Current IOS 2 10 pA
T
Input Voltage Range −0.2 +3.0 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 2 V 66 80 dB
VCM = 0 V to 3 V 60 74 dB
T
Input Impedance 1013||3.3 Ω||pF
Large Signal Voltage Gain AVO VO = 0.2 V to 4.0 V
RL = 2 kΩ 20 40 V/mV
= 0.2 V, TA = 25°C; unless otherwise noted.
OUT
MIN
MIN
MIN
MIN
to T
1.5 mV
MAX
to T
300 4000 pA
MAX
to T
300 pA
MAX
to T
60 dB
MAX
RL = 100 kΩ 250 1000 V/mV
T
MIN
to T
, RL = 100 kΩ 180 400 V/mV
MAX
Offset Voltage Drift ΔVOS/ΔT 2 µV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH I
T
I
T
Output Voltage Low VOL I
T
I
T
= 20 µA 4.975 4.988 V
SOURCE
to T
MIN
SOURCE
MIN
SINK
MIN
SINK
MIN
4.97 4.985 V
MAX
= 2.5 mA 4.80 4.85 V
to T
4.75 4.82 V
MAX
= 20 µA 15 25 mV
to T
20 30 mV
MAX
= 2.5 mA 120 150 mV
to T
140 200 mV
MAX
Short Circuit Limit ISC Sink/source ±12 mA
MIN
MAX
Open-Loop Impedance Z
f = 1 MHz, AV = 1 100 Ω
OUT
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 12 V 70 80 dB
T
Supply Current/Amplifier ISY T
MIN
MIN
to T
66 dB
MAX
to T
500 600 µA
MAX
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ, AV = 1 2 V/µs
Full-Power Bandwidth BWP 1% distortion, VO = 4 V p-p 150 kHz
Settling Time tS V
= 0.2 V to 4.5 V, to 0.01% 2.5 µs
OUT
Gain Bandwidth Product GBP 2 MHz
Channel Separation CS f = 1 kHz, RL = 2 kΩ –123 dB
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 2 µV p-p
Voltage Noise Density en f = 1 kHz 16 nV/√Hz
Current Noise Density in f = 1 kHz 0.8 fA/√Hz
Total Harmonic Distortion THD f = 10 kHz, RL = ∞, AV = +1 0.005 %
Rev. E | Page 3 of 16
Page 4
AD824 Data Sheet
Input Bias Current
IB
VCM = 0 V
4 35
pA
Input Voltage Range
−15 +13
V
T
to T
–14.98
–14.97
V
Slew Rate
SR
RL = 10 kΩ, AV = 1
2
V/µs
At VS = ±15.0 V, V
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage (AD824A) VOS 0.5 2.5 mV
T
= 0 V, TA = 25°C; unless otherwise noted.
OUT
to T
MIN
0.6 4.0 mV
MAX
T
MIN
to T
500 4000 pA
MAX
IB VCM = −10 V 25 pA
Input Offset Current IOS 3 20 pA
T
MIN
to T
500 pA
MAX
Common-Mode Rejection Ratio CMRR VCM = −15 V to 13 V 70 80 dB
T
MIN
to T
66 dB
MAX
Input Impedance 1013||3.3 Ω||pF
Large Signal Voltage Gain AVO VO = −10 V to +10 V;
RL = 2 kΩ 12 50 V/mV
RL = 10 kΩ 50 200 V/mV
RL = 100 kΩ 300 2000 V/mV
T
MIN
to T
, RL = 100 kΩ 200 1000 V/mV
MAX
Offset Voltage Drift ΔVOS/ΔT 2 µV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH I
T
I
T
Output Voltage Low VOL I
I
T
Short Circuit Limit ISC Sink/source, T
Open-Loop Impedance Z
f = 1 MHz, AV = 1 100 Ω
OUT
= 20 µA 14.975 14.988 V
SOURCE
to T
MIN
SOURCE
MIN
SINK
MIN
SINK
MIN
14.970 14.985 V
MAX
= 2.5 mA 14.80 14.85 V
to T
14.75 14.82 V
MAX
= 20 µA –14.985 –14.975 V
MAX
= 2.5 mA –14.88 –14.85 V
to T
–14.86 –14.8 V
MAX
to T
MIN
±8 ±20 mA
MAX
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 15 V 70 80 dB
T
MIN
to T
68 dB
MAX
Supply Current/Amplifier ISY VO = 0 V 560 625 µA
T
MIN
to T
675 µA
MAX
DYNAMIC PERFORMANCE
Full-Power Bandwidth BWP 1% distortion, VO = 20 V p-p 33 kHz
Settling Time tS V
Gain Bandwidth Product GBP 2 MHz
Phase Margin φo 50 Degrees
Channel Separation CS f = 1 kHz, RL = 2 kΩ –123 dB
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 2 µV p-p
Voltage Noise Density en f = 1 kHz 16 nV/√Hz
Current Noise Density in f = 1 kHz 1.1 fA/√Hz
Total Harmonic Distortion THD f =10 kHz, VO = 3 V rms, RL = 10 kΩ 0.005 %
= 0 V to 10 V, to 0.01% 6 µs
OUT
Rev. E | Page 4 of 16
Page 5
Data Sheet AD824
Input Bias Current
IB 2 12
pA
Common-Mode Rejection Ratio
CMRR
VCM = 0 V to 1 V
58
74 dB
Short Circuit Limit
I
Sink/source
±8 mA
At VS = 3.0 V, VCM = 0 V, V
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage (AD824A−3 V ) VOS 0.2 1.0 mV
T
= 0.2 V, TA = 25°C; unless otherwise noted.
OUT
to T
MIN
1.5 mV
MAX
T
MIN
to T
250 4000 pA
MAX
Input Offset Current IOS 2 10 pA
T
MIN
to T
250 pA
MAX
Input Voltage Range 0 1 V
T
MIN
to T
56 dB
MAX
Input Impedance 1013||3.3 Ω||pF
Large Signal Voltage Gain AVO VO = 0.2 V to 2.0 V;
RL = 2 kΩ 10 20 V/mV
RL = 10 kΩ 30 65 V/mV
RL = 100 kΩ 180 500 V/mV
T
MIN
to T
, RL = 100 kΩ 90 250 V/mV
MAX
Offset Voltage Drift ΔVOS/ΔT 2 µV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH I
T
I
T
Output Voltage Low VOL I
T
I
T
SC
ISC Sink/source, T
Open-Loop Impedance Z
f = 1 MHz, AV = 1 100 Ω
OUT
= 20 µA 2.975 2.988 V
SOURCE
to T
MIN
SOURCE
MIN
SINK
MIN
SINK
MIN
2.97 2.985 V
MAX
= 2.5 mA 2.8 2.85 V
to T
2.75 2.82 V
MAX
= 20 µA 15 25 mV
to T
20 30 mV
MAX
= 2.5 mA 120 150 mV
to T
140 200 mV
MAX
to T
MIN
±6 mA
MAX
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 12 V, 70 dB
T
Supply Current/Amplifier ISY VO = 0.2 V, T
MIN
to T
66 dB
MAX
to T
MIN
500 600 µA
MAX
DYNAMIC PERFORMANCE
Slew Rate SR RL =10 kΩ, AV = 1 2 V/µs
Full-Power Bandwidth BWP 1% distortion, VO = 2 V p-p 300 kHz
Settling Time tS V
= 0.2 V to 2.5 V, to 0.01% 2 µs
OUT
Gain Bandwidth Product GBP 2 MHz
Phase Margin φo 50 Degrees
Channel Separation CS f = 1 kHz, RL = 2 kΩ –123 dB
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 2 µV p-p
Voltage Noise Density en f = 1 kHz 16 nV/√Hz
Current Noise Density in 0.8 fA/√Hz
Total Harmonic Distortion THD f = 10 kHz, RL = ∞, AV = +1 0.01 %
Rev. E | Page 5 of 16
Page 6
AD824 Data Sheet
Lead Temperature Range (Soldering 60 sec)
300°C
R1 R2
J1 J2
+IN
R13
–IN
R15
Q4
Q5
Q6
R9
I5
V
CC
C3
Q7
C2
Q22
Q19
Q21
Q18 Q29
Q20
Q23
R7
C4
V
OUT
Q24
Q27
Q25
Q31
Q28
R17
Q26
C1
I4I3I2I1
R12 R14
Q2
Q8
Q3
V
EE
I6
00875-002
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter1 Rating
Supply Voltage ±18 V
Input Voltage −VS − 0.2 V to +VS
Differential Input Voltage ±30 V
Output Short Circuit Duration to GND Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +150°C
1
Absolute maximum ratings apply to packaged parts unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Table 5. Thermal Resistance
Package Type θ
14-Lead SOIC (R) 120 36 °C/W
1
θJA is specified for the worst case conditions, that is, θJA is specified for device
soldered in circuit board for SOIC package.
1
JA
θJC Unit
ESD CAUTION
Figure 2. Simplified Schematic of 1/4 AD824
Rev. E | Page 6 of 16
Page 7
Data Sheet AD824
0
20
180
90
135
45
40
60
80
100 10M1M100k10k1k
GAIN (dB)
PHASE (Degrees)
FREQUENCY ( Hz )
10
0%
100
90
1µs50mV
VS = ±15V
NO LOAD
00875-003
0
20
180
90
135
45
40
60
80
100 10M1M100k10k1k
GAIN (dB)
PHASE (Degrees)
FREQUENCY ( Hz )
VS = ±15V
C
L
= 100pF
10
0%
100
90
1µs50mV
00875-004
0
20
180
90
135
45
40
60
80
100 10M1M100k10k1k
GAIN (dB)
PHASE (Degrees)
FREQUENCY ( Hz )
VS = 5V
NO LOAD
0%
100
90
1µs50mV
00875-005
10
–20
0
180
90
135
45
20
40
60
1k 10M1M100k10k
GAIN (dB)
PHASE (Degrees)
FREQUENCY ( Hz )
VS = 5V
CL = 220pF
0%
100
90
1µs50mV
00875-006
10
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. Open-Loop Gain/Phase and Small Signal Response, VS = ±15 V,
No Load
Figure 5. Open-Loop Gain/Phase and Small Signal Response, VS = 5 V,
No Load
Figure 4. Open-Loop Gain/Phase and Small Signal Response, VS = ±15 V,
C
= 100 pF
L
Figure 6. Open-Loop Gain/Phase and Small Signal Response, VS = 5 V,
C
= 220 pF
L
Rev. E | Page 7 of 16
Page 8
AD824 Data Sheet
–20
0
180
90
135
45
20
40
60
1k 10M
1M
100k10k
GAIN (dB)
PHASE (Degrees)
FREQUENCY ( Hz )
V
S
= 3V
NO LOAD
0%
100
90
1µs
50mV
00875-007
10
–20
0
180
90
135
45
20
40
60
1k 10M1M100k10k
GAIN (dB)
PHASE (Degrees)
FREQUENCY ( Hz )
VS = 3V
CL = 220pF
0%
100
90
1µs50mV
00875-008
10
t
2µs5V
9.950µs
10
0%
100
90
t
10.810µs
2µs5V
10
0%
100
90
00875-009
10
0%
100
90
100µs
5V
V
OUT
00875-010
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1µ 10m5m1m500µ100µ50µ10µ5µ
OUTPUT TO RAIL (V)
LOAD CURRENT ( A)
SOURCE
SINK
00875-011
Figure 7. Open-Loop Gain/Phase and Small Signal Response, VS = 3 V,
No Load
Figure 8. Open-Loop Gain/Phase and Small Signal Response, VS = 3 V,
C
= 220 pF
L
Figure 9. Slew Rate, RL = 10 kΩ
Figure 10. Phase Reversal with Inputs Exceeding Supply by 1 V
Figure 11. Output Voltage to Supply Rail vs. Sink and Source Load Currents
Rev. E | Page 8 of 16
Page 9
Data Sheet AD824
5 10 15 20
60
40
20
3V ≤ VS ≤ ±15V
FREQUENCY ( kHz )
NOISE DENSITY (nV/√Hz)
00875-012
0.1
0.01
0.001
0.0001
20 100 1k 10k 20k
THD + N (%)
FREQUENCY ( Hz )
V
S
= +3V
V
S
= +5V
V
S
= ±15V
R
L
=
∞
A
V
= +1
00875-013
280
240
200
160
120
80
40
0
–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5
NUMBER OF UNI TS
OFFSET VOLTAGE (mV)
COUNT = 860
00875-014
14
12
10
8
6
4
2
0
–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5
NUMBER OF UNI TS
OFFSET VOLTAGE DRIFT (µV/°C)
COUNT = 60
00875-015
150
125
100
75
50
25
0
–25
–60 –40 –20 0
20 40 60
80 100 120
140
INPUT OFFSET CURRENT ( pA)
TEMPERATURE (°C)
VS = 5V, 0V
00875-016
100k
10k
1k
100
10
1
0.1
20 40 60 80 100 120 140
INPUT BIAS CURRE NT (pA)
TEMPERATURE (°C)
VS = 5V, 0V
00875-017
Figure 12. Voltage Noise Density
Figure 15. TC V
Distribution, −55°C to +125°C, VS = 5 V, 0 V
OS
Figure 13. Total Harmonic Distortion
Figure 14. Input Offset Distribution, VS = 5 V, 0 V
Figure 17. Input Bias Current vs. Temperature
Figure 16. Input Offset Current vs. Temperature
Rev. E | Page 9 of 16
Page 10
AD824 Data Sheet
120
100
80
60
40
20
0
10
100
1k
10k
100k
1M 10M
COMMON-M ODE REJECTIO N ( dB)
FREQUENCY ( Hz )
00875-018
–40
–60
–80
–100
–120
100 1k 10k 100k
THD (dB)
FREQUENCY ( Hz )
00875-019
100
80
60
40
20
–20
0
100
80
60
40
20
–20
0
10 100 1k 10k 100k 1M 10M
OPEN-LOOP GAIN (dB)
PHASE MARGIN (Degrees)
FREQUENCY ( Hz )
±15V
3V, 0V
00875-020
1k
100
10
1
1 10 100 1k 10k 100k
INPUT VOLTAGE NOISE (nV/√Hz)
FREQUENCY ( Hz )
00875-021
120
100
80
60
40
20
0
10 100 1k 10k 100k 1M 10M
POWER SUPPLY REJECTION (dB)
FREQUENCY ( Hz )
00875-022
30
25
20
15
10
5
0
1k 3k 10k 30k 100k 300k 1M
OUTPUT VOLTAGE (V)
INPUT FRE QUENCY (Hz)
00875-023
Figure 18. Common-Mode Rejection vs. Frequency
Figure 19. THD vs. Frequency, 3 V rms
Figure 21. Input Voltage Noise Spectral Density vs. Frequency
Figure 22. Power Supply Rejection vs. Frequency
Figure 20. Open-Loop Gain and Phase vs. Frequency
Figure 23. Large Signal Frequency Response
Rev. E | Page 10 of 16
Page 11
Data Sheet AD824
–80
–90
–100
–110
–120
–130
–140
10 100 1k 10k 100k
CROSSTAL K ( dB)
FREQUENCY ( Hz )
1 TO 4
1 TO 2
1 TO 3
00875-024
10k
1k
100
10
1
0.1
0.01
10 100 1k 10k 100k 1M
10M
OUTPUT IMPEDANCE (Ω)
FREQUENCY ( Hz )
00875-025
10
0%
100
90
500ns20mV
00875-026
10
0%
100
90
5µs5V
00875-027
2750
1000
1250
1500
1750
2000
2250
2500
–60 –40 –20 0 20 40 60 80 100 120 140
SUPPLY CURRENT (µA)
TEMPERATURE (°C)
VS = ±15V
V
S
= +3V, 0V
00875-028
1k
100
10
1
0.01 1010.1
OUTPUT SATURATION VOLTAGE (mV)
LOAD CURRENT ( mA)
V
OL
– V
S
VS = ±15V
V
S
= 3V, 0V
VS – V
OH
00875-029
Figure 24. Crosstalk vs. Frequency
Figure 25. Output Impedance vs. Frequency, Gain = +1
Figure 27. Large Signal Response
Figure 28. Supply Current vs. Temperature
Figure 26. Small Signal Response, Unity Gain Follower, 10 kΩ||100 pF Load
Figure 29. Output Saturation Voltage
Rev. E | Page 11 of 16
Page 12
10
0%
100
90
1V
1V
10µs1V
10
0%
100
90
1V
2µs
1V
GND
GND
+V
S
5V
R
P
V
OUT
V
IN
(b)
(a)
00875-030
1/4
AD824
8
4
V
IN
+V
S
–V
S
V
OUT
20pF
20kΩ
C
L
0.01µF
0.01µF
100Ω
00875-031
AD824 Data Sheet
THEORY OF OPERATION
INPUT CHARACTERISTICS
In the AD824, n-channel JFETs are used to provide a low offset,
low noise, high impedance input stage. Minimum input
common-mode voltage extends from 0.2 V below −V
less than +V
rail causes a loss of amplifier bandwidth.
The AD824 does not exhibit phase reversal for input voltages up
to and including +V
AD824 voltage follower to a 0 V to 5 V (+V
The input and output are superimposed. The output tracks the
input up to +V
above a 4 V input causes the rounding of the output waveform.
For input voltages greater than +V
noninverting input prevents phase reversal at the expense of
greater input voltage noise. This is illustrated in Figure 30b.
. Driving the input voltage closer to the positive
S
. Figure 30a shows the response of an
S
) square wave input.
S
without phase reversal. The reduced bandwidth
S
, a resistor in series with the
S
to 1 V
S
positive supply by more than 300 mV or if an input voltage will
be applied to the AD824 when ±V
= 0 V. The amplifier will be
S
damaged if left in that condition for more than 10 seconds. A
1 kΩ resistor allows the amplifier to withstand up to 10 V of
continuous overvoltage and increases the input voltage noise by
a negligible amount.
Input voltages less than −V
are a completely different story. The
S
amplifier can safely withstand input voltages 20 V below the
−V
as long as the total voltage from the +VS to the input termi-
S
nal is less than 36 V. In addition, the input stage typically maintains
picoamp level input currents across that input voltage range.
OUTPUT CHARACTERISTICS
The unique bipolar rail-to-rail output stage of the AD824
swings within 15 mV of the positive and negative supply
voltages. The approximate output saturation resistance of the
AD824 is 100 Ω for both sourcing and sinking. This can be used
to estimate output saturation voltage when driving heavier
current loads. For instance, the saturation voltage is 0.5 V from
either supply with a 5 mA current load.
For load resistances over 20 kΩ, the input error voltage of the
AD824 is virtually unchanged until the output voltage is driven
to 180 mV of either supply.
If the output of the AD824 is overdriven to saturate either of the
output devices, the amplifier will recover within 2 μs of its input
returning to the amplifier’s linear operating region.
Direct capacitive loads will interact with the amplifier’s effective
output impedance to form an additional pole in the amplifier’s
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. Worst case is when the amplifier is
used as a unity gain follower. Figure 6 and Figure 8 show the
pulse response of the AD824 as a unity gain follower driving
220 pF. Configurations with less loop gain, and as a result less
loop bandwidth, will be much less sensitive to capacitance load
effects. Noise gain is the inverse of the feedback attenuation
factor provided by the feedback network in use.
Figure 31 shows a method for extending capacitance load drive
capability for a unity gain follower. With these component
values, the circuit drives 5,000 pF with a 10% overshoot.
Figure 30. (a) Response with R
(b) V
= −200 V to + VS + 200 mV; V
IN
= 0; VIN from 0 V to +VS;
P
= 0 V to + VS; RP = 49.9 kΩ
OUT
Because the input stage uses n-channel JFETs, input current
during normal operation is positive; the current flows out from
the input terminals. If the input voltage is driven more positive
than +V
device junctions become forward biased. This is illustrated in
Figure 10.
Use a current-limiting resistor in series with the input of the
AD824 if there is a possibility of the input voltage exceeding the
− 0.4 V, the input current reverses direction as internal
S
Figure 31. Extending Unity Gain Follower Capacitive Load Capability
Beyond 350 pF
Rev. E | Page 12 of 16
Page 13
Data Sheet AD824
1/4
AD824
U4
REF02
R
SCALE
**
10kΩ
2
6
5
4
3
V
REF
= 5V
CMOS
74HCO4
4 3 2 1
U3B U3A
OUT2
OUT1
10V
U1
2
6
5
3
7
1
4 8
U2
CMOS 555
TR
THR
DIS
CV
OUT
R V+
GND
0V TO 2.5V
FULL SCALE
C3
0.1µF
C4
0.1µF
C6
390pF
5%
(NPO)
R2
499kΩ
1%
R3*
116kΩ
C2
0.01µF
2%
C1
0.01µF
2%
C5
0.1µF
R1
499kΩ
1%
NOTES
f
OUT
= V
IN
/(V
REF
× t1), t1 = 1.1 × R3 × C6 = 25kHz fS AS SHOWN.
* = 1% METAL FILM, <50ppm/°C TC
** = 10%, 20T FI LM, <100ppm/°C TC
t
1
= 33µs FOR f
OUT
= 20kHz @ VIN = 2.0V
00875-032
Common-Mode Voltage Range
−0.2 V to +2 V
−5.2 V to +4 V
10
0%
100
90
1V
5µs
00875-033
V
OUT
+V
S
0.1µF
R6
90kΩ
R5
9kΩ
R4
1kΩ
R3
1kΩ
R2
9kΩ
R1
90kΩ
G = 10 G = 10G = 100G = 100
OHMTEK
PART #1043
2
1
3
6
7
5
11
1/4
AD824
1/4
AD824
V
REF
V
IN1
R
P
1kΩ
R
P
1kΩ
V
IN2
(G = 10) V
OUT
= (V
IN1
– V
IN2
)(1 + ) + V
REF
R6
R4 + R5
FOR R1 = R6, R2 = R5 AND R3 = R4
(G = 10) V
OUT
= (V
IN1
– V
IN2
)(1 + ) + V
REF
R5 + R6
R4
00875-034
APPLICATIONS INFORMATION
SINGLE SUPPLY VOLTAGE-TO-FREQUENCY CONVERTER
The circuit shown in Figure 32 uses the AD824 to drive a low
power timer, which produces a stable pulse of width, t
positive going output pulse is integrated by R1 and C1 and used
as one input to the AD824, which is connected as a differential
integrator. The other input (nonloading) is the unknown
voltage, V
. The AD824 output drives the timer trigger input,
IN
closing the overall feedback loop.
. The
1
Table 6. AD824 In Amp Performance
Parameter VS = 3 V, 0 V VS = ±5 V
CMRR 74 dB 80 dB
3 dB BW
G = 10 180 kHz 180 kHz
G = 100 18 kHz 18 kHz
t
SET TLING
2 V Step (VS = 0 V, 3 V ) 2 μs
5 V ( VS = ± 5 V) 5 μs
Noise @ f = 1 kHz
G = 10 270 nV/√Hz 270 nV/√Hz
G = 100 2.2 μV/√Hz 2.2 μV/√Hz
Figure 32. Single Supply Voltage-to-Frequency Converter
Typ i cal AD824 bias currents of 2 pA allow MΩ range source
impedances with negligible dc errors. Linearity errors of 0.01%
full scale can be achieved with this circuit. This performance is
obtained with a 5 V single supply, which delivers less than 3 mA
to the entire circuit.
SINGLE SUPPLY PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER
The AD824 can be configured as a single supply instrumentation amplifier that is able to operate from single supplies down
to 5 V or dual supplies up to ±1 5 V. AD824 FET inputs bias
currents of 2 pA minimize offset errors caused by high
unbalanced source impedances.
An array of precision thin-film resistors sets the in amp gain to
be either 10 or 100. These resistors are laser-trimmed to ratio
match to 0.01% and have a maximum differential TC of
5 ppm/°C.
Figure 33. Pulse Response of In Amp to a 500 mV p-p Input Signal;
V
= 5 V, 0 V; Gain = 10
S
Figure 34. A Single Supply Programmable Instrumentation Amplifier
Rev. E | Page 13 of 16
Page 14
AD824 Data Sheet
L
R
HEADPHONES
32Ω IMPEDANCE
3V
CHANNEL 1
CHANNEL 2
500µF
500µF
1µF
MYLAR
1µF
MYLAR
95.3kΩ
47.5kΩ
47.5kΩ
95.3kΩ
10kΩ
0.1µF 0.1µF
10kΩ
4.99kΩ
4.99kΩ
1/4
AD824
1/4
AD824
00875-035
1
k
4.
49
+
Ω
=
G
R
G
V
REF
–V
S
+V
S
R
G
–4.5V
R1
20Ω
350Ω
26.4kΩ, 1%
49.9kΩ
350Ω
R2
20Ω
350Ω
350Ω
TO ADC
REFERENCE INP UT
AD589
+1.235V
+5V
GND
+V
S
–V
S
–5V
–V
S
+V
S
7
6
5
4
3
2
1/4
AD824
1/4
AD824
AD824
10kΩ
1%
10kΩ
1%
0.1µF 1µF
0.1µF 1µF
10kΩ
1%
00875-036
3 V, SINGLE SUPPLY STEREO HEADPHONE DRIVER
The AD824 exhibits good current drive and THD + N
performance, even at 3 V single supplies. At 1 kHz, total
harmonic distortion plus noise (THD + N) equals −62 dB
(0.079%) for a 300 mV p-p output signal. This is comparable
to other single supply op amps that consume more power and
cannot run on 3 V power supplies.
In Figure 35, each channel’s input signal is coupled via a 1 µF
Mylar capacitor. Resistor dividers set the dc voltage at the
noninverting inputs so that the output voltage is midway
between the power supplies (1.5 V). The gain is 1.5. Each half of
the AD824 can then be used to drive a headphone channel. A
5 Hz high-pass filter is realized by the 500 µF capacitors and the
headphones, which can be modeled as 32 Ω load resistors to
ground. This ensures that all signals in the audio frequency
range (20 Hz to 20 kHz) are delivered to the headphones.
LOW DROPOUT BIPOLAR BRIDGE DRIVER
The AD824 can be used for driving a 350 Ω Wheatstone bridge.
Figure 36 shows one half of the AD824 being used to buffer the
AD589—a 1.235 V low power reference. The output of 4.5 V
can be used to drive an ADC front end. The other half of the
AD824 is configured as a unity-gain inverter and generates the
other bridge input of –4.5 V. Resistors R1 and R2 provide a
constant current for bridge excitation. The AD620 low power
instrumentation amplifier is used to condition the differential
output voltage of the bridge. The gain of the AD620 is programmed using an external resistor R
and determined by:
G
Figure 35. 3 Volt Single Supply Stereo Headphone Driver
Figure 36. Low Dropout Bipolar Bridge Driver
Rev. E | Page 14 of 16
Page 15
3.3V/5V
3.3V/5V
3
2
4
1
11
0.1µF
FALSE GROUND (FG)
12
13
14
SAMPLE/
HOLD
10
9
8
5
6
7
15
14
16
10
9
11
AD824
3.3V/5V
ADG513
AD824
+
–
V
OUT
CH
500pF
C2
500pF
FG
4
5
8
6
7
2
3
1
AD824
AD824
FG
13
FG
A1
A2
A3
A4
R1
50kΩ
R2
50kΩ
R5
2kΩ
R4
2kΩ
SW2
SW3
SW1
SW4
00875-037
Data Sheet AD824
A 3.3 V/5 V PRECISION SAMPLE-AND-HOLD AMPLIFIER
In battery-powered applications, low supply voltage operational
amplifiers are required for low power consumption. Also, low
supply voltage applications limit the signal range in precision
analog circuitry. Circuits like the sample-and-hold circuit
shown in Figure 37 illustrate techniques for designing precision
analog circuitry in low supply voltage applications. To maintain
high signal-to-noise ratios (SNRs) in a low supply voltage
application requires the use of rail-to-rail, input/output
operational amplifiers. This design highlights the ability of the
AD824 to operate rail-to-rail from a single 3 V/5 V supply, with
the advantages of high input impedance. The AD824, a quad
JFET-input op amp, is well suited to sample-and-hold circuits
due to its low input bias currents (3 pA, typical) and high input
impedances (3 × 10
low supply currents so the total supply current in this circuit is
less than 2.5 mA.
In many single supply applications, the use of a false ground
generator is required. In this circuit, R1 and R2 divide the
supply voltage symmetrically, creating the false ground voltage
at one-half the supply. Amplifier A1 then buffers this voltage
creating a low impedance output drive. The sample-and-hold
Figure 37. 3.3 V/5.5 V Precision Sample-and-Hold Circuit
circuit is configured in an inverting topology centered around
this false ground level.
13
Ω, typical). The AD824 also exhibits very
Rev. E | Page 15 of 16
A design consideration in sample-and-hold circuits is voltage
droop at the output caused by op amp bias and switch leakage
currents. By choosing an JFET op amp and a low leakage CMOS
switch, this design minimizes droop rate error to better than
0.1 µV/µs in this circuit. Higher values of CH will yield a lower
droop rate. For best performance, CH and C2 should be
polystyrene, polypropylene or Teflon capacitors.
These types of capacitors exhibit low leakage and low dielectric
absorption. Additionally, 1% metal film resistors were used
throughout the design.
In the sample mode, SW1 and SW4 are closed, and the output is
V
= −VIN. The purpose of SW4, which operates in parallel
OUT
with SW1, is to reduce the pedestal, or hold step, error by
injecting the same amount of charge into the noninverting
input of A3 that SW1 injects into the inverting input of A3. This
creates a common-mode voltage across the inputs of A3 and is
then rejected by the CMR of A3; otherwise, the charge injection
from SW1 creates a differential voltage step error that appears at
V
. The pedestal error for this circuit is less than 2 mV over
OUT
the entire 0 V to 3.3 V/5 V signal range. Another method of
reducing pedestal error is to reduce the pulse amplitude applied
to the control pins. To control the ADG513, only 2.4 V are
required for the on state and 0.8 V for the off state. If possible,
use an input control signal whose amplitude ranges from 0.8 V
to 2.4 V instead of a full range 0 V to 3.3 V/5 V for minimum
pedestal error.
Other circuit features include an acquisition time of less than
3 µs to 1%; reducing CH and C2 will speed up the acquisition
time further, but an increased pedestal error will result. Settling
time is less than 300 ns to 1%, and the sample-mode signal BW
is 80 kHz.
The ADG513 was chosen for its ability to work with 3 V/5 V
supplies and for having normally open and normally closed
precision CMOS switches on a dielectrically isolated process.
SW2 is not required in this circuit; however, it was used in
parallel with SW3 to provide a lower R
analog switch.
ON
Page 16
AD824 Data Sheet
CONTROLLING DIMENSIONSARE IN MILLI M E TERS; INCH DIM ENS IONS
(IN
P
ARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ON
LY
AND
ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT T
O JEDEC S
TANDARDS MS-012-AB
060606-A
14
8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
45°
Model1
Temperature Range
Package Description
Package Option
AD824AR-14
−40°C to +85°C
14-Lead Standard Small Outline Package [SOIC_N]
R-14
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
OUTLINE DIMENSIONS
Figure 38. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
AD824AR-14-3V −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD824AR-14-3V-REEL −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD824AR-14-REEL −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD824AR-14-REEL7 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD824ARZ-14 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD824ARZ-14-3V −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD824ARZ-14-3V-RL −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD824ARZ-14-REEL −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
AD824ARZ-14-REEL7 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
1
Z = RoHS Compliant Part.
registered trademarks are the property of their respective owners.
D00875-0-4/15(E)
Rev. E | Page 16 of 16
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