ANALOG DEVICES AD8155 Service Manual

6.5 Gbps

FEATURES

Dual 2:1 mux/1:2 demux Optimized for dc to 6.5 Gbps NRZ data Per-lane P/N pair inversion for routing ease Programmable input equalization Compensates up to 40 inches of FR4 Loss-of-signal detection Programmable output preemphasis up to 12 dB Programmable output levels with squelch and disable Accepts ac-coupled or dc-coupled differential CML inputs 50 Ω on-chip termination 1:2 demux supports unicast or bicast operation Port-level loopback Port or single lane switching

1.8 V to 3.3 V flexible core supply User-settable I/O supply from V Low power, typically 2.0 W in basic configuration 64-lead LFCSP

−40°C to +85°C operating temperature range

APPLICATIONS

Low cost redundancy switch SONET OC48/SDH16 and lower data rates RXAUI, 4× Fibre Channel, Infiniband, and GbE over

backplane OIF CEI 6.25 Gbps over backplane Serial data-level shift 2-/4-/6-lane equalizers or redrivers

to 1.2 V

CC

Ix_A[1:0]

Ix_B[1:0]

Ox_A[1:0]

Ox_B[1:0]

SCL SDA

I2C_A[2:0]

Dual Buffer Mux/Demux

AD8155

FUNCTIONAL BLOCK DIAGRAM

RECEIVE

EQUALIZAT ION

EQ

TRANSMIT

PRE-

EMPHASIS

I2C

CONTROL

LOGIC

AD8155

2:1

1:2

DUAL

2:1

MULTIPLEXER/

1:2

DEMULTIPLEXER

Figure 1.

TRANSMIT

PRE-

EMPHASIS

EQ

RECEIVE

EQUALIZATION

CONTROL

LOGIC

Ox_C[1:0]

Ix_C[1:0]

LB_A LB_B LB_C PE_A PE_B PE_C EQ_A EQ_B EQ_C SEL[1:0] BICAST SEL4G RESET LOS_INT

08262-001

GENERAL DESCRIPTION

The AD8155 is an asynchronous, protocol-agnostic, dual-lane 2:1 switch with a total of six differential CML inputs and six differential CML outputs. The signal path supports NRZ signaling with data rates up to 6.5 Gbps per lane. Each lane offers programmable receive equalization, programmable output preemphasis, programmable output levels, and loss-ofsignal detection.

The nonblocking switch core of the AD8155 implements a 2:1 multiplexer and 1:2 demultiplexer per lane and supports independent lane switching through the two select pins, SEL[1:0]. Each port is a two-lane link. Every lane implements an asynchronous path supporting dc to 6.5 Gbps NRZ data, fully independent of other lanes. The AD8155 has low latency and very low lane-to-lane skew.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

The main application of the AD8155 is to support redundancy on both the backplane and the line interface sides of a serial link. The demultiplexing path implements unicast and bicast capability, allowing the part to support either 1 + 1 or 1:1 redundancy.

The AD8155 is also suited for testing high speed serial links because of its ability to duplicate incoming data. In a portmonitoring application, the AD8155 can maintain link connectivity with a pass-through connection from Port C to Port A while sending a duplicate copy of the data to test equipment on Port B.

The rich feature set of the AD8155 can be controlled either through external toggle pins or by setting on-chip control registers through the I

2

C® interface.

AD8155

REVISION HISTORY

7/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 36

AD8155

SPECIFICATIONS

VCC = V coupled inputs and outputs, differential input swing = 800 mV p-p, T

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

INPUT CHARACTERISTICS

OUTPUT CHARACTERISTICS

TERMINATION CHARACTERISTICS

LOS CHARACTERISTICS

POWER SUPPLY

= V

TTI

= 1.8 V, DVCC = 3.3 V, VEE = 0 V, RL = 50 Ω, basic configuration1, data rate = 6.5 Gbps, data pattern = PRBS7, ac-

TTO

= 25°C, unless otherwise noted.

A

Data Rate/Channel (NRZ) DC 6.5 Gbps

Deterministic Jitter (No

Data rate = 6.5 Gbps, EQ setting = 0 22 ps p-p

Channel) Random Jitter (No Channel) RMS, data rate = 6.5 Gbps 1 ps Residual Deterministic Jitter

with Receive Equalization

Residual Deterministic Jitter

with Transmit Preemphasis

Data rate 6.5 Gbps, 20 inch FR4 30 ps p-p Data rate 6.5 Gbps, 40 inch FR4 40 ps p-p Data rate 6.5 Gbps, 10 inch FR4 35 ps p-p

Data rate 6.5 Gbps, 30 inch FR4 42 ps p-p Propagation Delay 50% input to 50% output (maximum EQ) 700 ps Lane-to-Lane Skew

Signal path and switch architecture is balanced

90 ps

and symmetric (maximum EQ) Switching Time 50% logic switching to 50% output data 150 ns Output Rise/Fall Time 20% to 80% (PE = lowest setting) 62 ps

Differential Input Voltage

Swing

2

V

= VCC − 0.6 V, VCC = V

ICM

T

,

MAX

MIN

to V

MAX

, TA = T

MIN

to

200 2000

mV p-p diff

LOS control register = 0x05

Input Voltage Range Single-ended absolute voltage level, VL minimum VEE + 0.6 V Single-ended absolute voltage level, VH maximum VCC + 0.3 V

Output Voltage Swing Differential, PE = 0, default output level, @ dc 590 725 820

mV p-p diff

Output Voltage Range, Single-

TX_HEADROOM = 0, V

minimum VCC − 1.1 V

L

Ended Absolute Voltage Level TX_HEADROOM = 0, VH maximum VCC + 0.6 V TX_HEADROOM = 1, VL minimum VCC − 1.3 V TX_HEADROOM = 1, VH maximum VCC + 0.6 V Output Current Port A/B/C, PE_A/B/C = minimum 16 mA Port A/B/C, PE_A/B/C = 6 dB, VOD = 800 mV p-p 32 mA

Resistance Differential, VCC = V

DC Assert Level 50

MIN

to V

MAX

, TA = T

MIN

to T

90 100 110 Ω

MAX

mV p-p diff

DC Deassert Level 300

mV p-p diff

LOS to Output Squelch

LOS to Output Enable

LOS control = 0, V

= 1.8 V

V

CC

= 0 to 50% OP/ON settling,

ID

LOS control = 0, data present to first valid transition, V

= 1.8 V

CC

21 ns

67 ns

Operating Range

V

CC

VEE = 0 V, TX_HEADROOM = 0 1.6 1.8 to 3.3 3.6 V

VEE = 0 V, TX_HEADROOM = 1 2.2 3.3 3.6 V DVCC DVCC ≥ VCC, VEE = 0 V 1.6 1.8 to 3.3 3.6 V V

1.2 VCC + 0.3 V

TTI

V

1.2 VCC + 0.3 V

TTO

Rev. 0 | Page 3 of 36

AD8155

Parameter Conditions Min Typ Max Unit

Supply Current

ICC

VCC = 1.8 V LB_x = 0, PE = 0 dB on all ports, low power mode LB_x = 1, PE = 6 dB on all ports, low power mode LB_x = 0, PE = 0 dB on all ports, default 350 410 mA LB_x = 1, PE = 6 dB on all ports, default 690 800 mA VCC = 3.3 V LB_x = 0, PE = 0 dB on all ports, low power mode LB_x = 1, PE = 6 dB on all ports, low power mode LB_x = 0, PE = 0 dB on all ports, default 380 450 mA LB_x = 1, PE = 6 dB on all ports, default 735 850 mA

I

TTO

V

= 1.8 V LB_x = 0, PE = 0 dB on all ports, low power mode

TTO

LB_x = 1, PE = 6 dB on all ports, low power mode LB_x = 0, PE = 0 dB on all ports, default 66 82 mA LB_x = 1, PE = 6 dB on all ports, default 183 225 mA V

= 3.3 V LB_x = 0, PE = 0 dB on all ports, low power mode

TTO

LB_x = 1, PE = 6 dB on all ports, low power mode LB_x = 0, PE = 0 dB on all ports, default 69 84 mA LB_x = 1, PE = 6 dB on all ports, default 193 230 mA

I

10 20 mA

TTI

I

2 4 mA

DVCC

THERMAL CHARACTERISTICS

Operating Temperature Range −40 +85 °C θJA

θJC Still air; thermal resistance through exposed pad 1.1 °C/W Maximum Junction Temperature 125 °C

LOGIC CHARACTERISTICS

4

Input High (VIH) DV Input Low (VIL) DV Input High (VIH) DV Input Low (VIL) DV Output High (VOH) 2 kΩ pull-up resistor to DVCC DVCC V Output Low (VOL) IOL = +3 mA VEE 0.4 V

1

Bicast is off, loopback is off on all ports, preemphasis is set to minimum on all ports, and equalization is set to minimum on all ports.

2

V

is the input common-mode voltage.

ICM

3

Low power mode is obtained by following the steps identified in the Initialization Sequence for Low Power and LOS_INT Operation section.

4

EQ control pins (EQ_A, EQ_B, EQ_C) require 5 kΩ in series when DVCC > VCC.

3

233 270 mA

3

406 480 mA

3

254 300 mA

3

435 500 mA

3

66 82 mA

3

186 226 mA

3

69 85 mA

3

195 230 mA

Still air; JEDEC 4-layer test board, exposed pad

21.2 °C/W

soldered

I2C, SDA, SCL, control pins

= 3.3 V 0.7 × DVCC DVCC V

CC

= 3.3 V VEE 0.3 × DVCC V

CC

= 1.8 V 0.8 × DVCC DVCC V

CC

= 1.8 V VEE 0.2 × DVCC V

CC

Rev. 0 | Page 4 of 36

AD8155

A

I2C TIMING SPECIFICATIONS

SD

t

F

SCL

NOTES

1. S = START CONDITI ON.

2. Sr = REPEAT START.

3. P = STOP.

t

LOW

t

HD;STA

S Sr

t

R

t

HD;DAT

SU;DAT

t

HIGH

F

t

SU;STA

Figure 2. I

2

C Timing Diagram

t

HD;STA

Table 2. I2C Timing Parameters

Parameter Symbol Min Max Unit

SCL Clock Frequency f Hold Time for a Start Condition t Setup Time for a Repeated Start Condition t Low Period of the SCL Clock t High Period of the SCL Clock t Data Hold Time t Data Setup Time t Rise Time for Both SDA and SCL t Fall Time for Both SDA and SCL t Setup Time for Stop Condition t Bus Free Time Between a Stop and a Start Condition t

0 400+ kHz

SCL

HD;STA

SU;STA

LOW

HIGH

HD;DAT

SU;DAT

R

F

SU;STO

BUF

Bus Free Time After a Reset 1 μs Reset Pulse Width 10 ns Capacitance for Each I/O Pin C

i

t

SU;STO

t

R

t

BUF

SP

08262-002

0.6 μs

1.3 μs

0.6 μs 0 μs 10 ns 1 300 ns 1 300 ns

0.6 μs 1 μs

5 7 pF

Rev. 0 | Page 5 of 36

AD8155

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating VCC to VEE 3.7 V DVCC to VEE 3.7 V V

Lower of (VCC + 0.6 V) or 3.6 V

TTI

V

Lower of (VCC + 0.6 V) or 3.6 V

TTO

VCC to DVCC 0.6 V Internal Power Dissipation Differential Input Voltage 2.0 V Logic Input Voltage VEE − 0.3 V < VIN < VCC + 0.6 V Storage Temperature Range

Junction Temperature

4.85 W

−65°C to +125°C 125°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 6 of 36

AD8155

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CC

TTIVCC

IP_C1

IN_C1

V

PE_A

PE_B

PE_C

LOS_INTLB_A

BICAST

SEL0

SEL1

IP_C0

IN_C0

646362616059585756555453525150

V

LB_B

49

SEL4G

V

EE

V

TTO

ON_A1 OP_A1

V

CC

ON_A0 OP_A0

V

TTI

10

IN_A1

11

IP_A1

V

12

CC

13

IN_A0

14

IP_A0

V

15

EE

16

DV

CC

NC = NO CONNECT

NOTES

1. NC = NO CONNECT .

2. THE EXPO SED PAD ON THE BOTTOM OF THE PACKAGE MUST BE ELECTRICAL LY CONNECTE D TO V

PIN 1

1

INDICATOR

2 3 4 5 6 7 8 9

171819202122232425262728293031

SCL

SDA

I2C_A0

I2C_A1

I2C_A2

AD8155

TOP VIEW

(Not to Scale)

TTO

V

OP_B1

RESET

ON_B1

.

EE

CC

V

EQ_A

EQ_B

OP_B0

ON_B0

48

LB_C V

47

EE

46

OP_C0

45

ON_C0 V

44

CC

43

OP_C1

42

ON_C1 V

41

TTO

V

40

CC

39

IP_B0

38

IN_B0 V

37

CC

36

IP_B1

35

IN_B1 V

34

TTI

V

33

EE

32

EQ_C

08262-003

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Type Description

1 SEL4G Control Set Transmitter for Low Speed PE, Active High. 2, 15, 29, 33, 47, ePAD VEE Power

3, 23, 41 V

Power Port A, Port B, and Port C Output Termination Supply.

TTO

Negative Supply. The exposed pad on the bottom of the package must be electrically connected to V

EE

4 ON_A1 Output High Speed Output Complement. 5 OP_A1 Output High Speed Output. 6, 12, 26, 37, 40, 44, 55, 59 VCC Power Positive Supply. 7 ON_A0 Output High Speed Output Complement. 8 OP_A0 Output High Speed Output. 9, 34, 56 V

Power Port A, Port B, and Port C Input Termination Supply.

TTI

10 IN_A1 Input High Speed Input Complement. 11 IP_A1 Input High Speed Input. 13 IN_A0 Input High Speed Input Complement. 14 IP_A0 Input High Speed Input. 16 DVCC Power Digital Power Supply. 17 SCL Control I2C Clock Input. 18 SDA Control I2C Data Input/Output. 19 I2C_A0 Control I2C Address Input (LSB). 20 I2C_A1 Control I2C Address Input. 21 I2C_A2 Control I2C Address Input (MSB). 22

RESET

Control Device Reset, Active Low. 24 ON_B1 Output High Speed Output Complement. 25 OP_B1 Output High Speed Output. 27 ON_B0 Output High Speed Output Complement. 28 OP_B0 Output High Speed Output.

.

Rev. 0 | Page 7 of 36

AD8155

Pin No. Mnemonic Type Description

30 EQ_A Control Port A Equalizer Control Input. 31 EQ_B Control Port B Equalizer Control Input. 32 EQ_C Control Port C Equalizer Control Input. 35 IN_B1 Input High Speed Input Complement. 36 IP_B1 Input High Speed Input. 38 IN_B0 Input High Speed Input Complement. 39 IP_B0 Input High Speed Input. 42 ON_C1 Output High Speed Output Complement. 43 OP_C1 Output High Speed Output. 45 ON_C0 Output High Speed Output Complement. 46 OP_C0 Output High Speed Output. 48 LB_C Control Port A Loopback Control Input, Active High. 49 LB_B Control Port B Loopback Control Input, Active High. 50 LB_A Control Port C Loopback Control Input, Active High. 51 LOS_INT Interrupt

52 PE_C Control Port A Preemphasis Control Input, Active High. 53 PE_B Control Port B Preemphasis Control Input, Active High. 54 PE_A Control Port C Preemphasis Control Input, Active High. 57 IN_C1 Input High Speed Input Complement. 58 IP_C1 Input High Speed Input. 60 IN_C0 Input High Speed Input Complement. 61 IP_C0 Input High Speed Input. 62 SEL1 Control Lane 1 A/B Switch Control Input. 63 SEL0 Control Lane 0 A/B Switch Control Input. 64 BICAST Control Enable Bicast for Port A and Port B Outputs, Active High.

Loss of Signal Interrupt, Active High. Initialization sequence required; see the Applications Information section.

Rev. 0 | Page 8 of 36

AD8155

V

TYPICAL PERFORMANCE CHARACTERISTICS

DATA OUT

PATTERN

GENERATOR

2 2

INPUT PIN

AD8155

AC-COUPLED

EVALUATIO N

OUTPUT

BOARD

50Ω CABLES

Figure 4. Standard Test Circuit (No Channel)

50Ω CABLES

2 2

50Ω

TP2TP1

OSCILLOSCOPE

HIGH SPEED

SAMPLING

08262-004

200mV/DI

25ps/DIV

Figure 5. 6.5 Gbps Input Eye (TP1 from Figure 4)

08262-005

200mV/DI

25ps/DIV

Figure 6. 6.5 Gbps Output Eye, No Channel (TP2 from Figure 4)

08262-006

Rev. 0 | Page 9 of 36

AD8155

V

200mV/DI

25ps/DIV

REFERENCE EYE DI AGRAM AT TP1

DATA OUT

PATTERN

GENERATOR

50Ω CABLES

2 2

FR4 TEST BACKPLANE

DIFFERENTIAL STRIPLI NE TRACES

TP1

8mils WI DE, 8mils SPACE, 8mils DIEL ECTRIC HEI GHT

TRACE LENGTHS = 20 INCHES, 40 INCHES

Figure 7. Input Equalization Test Circuit

50Ω CABLES

2 2

TP2

INPUT

OUTPUT

AD8155

AC-COUPLED EVALUATIO N

BOARD

50Ω CABLES

2 2

50Ω

TP3

SAMPLING

OSCILLOSCOPE

HIGH

SPEED

08262-007

200mV/DI

25ps/DIV

08262-008

Figure 8. 6.5 Gbps Input Eye, 20 Inch FR4 Input Channel (TP2 from Figure 7)

200mV/DI

25ps/DIV

08262-009

Figure 9. 6.5 Gbps Input Eye, 40 Inch FR4 Input Channel (TP2 from Figure 7)

200mV/DI

25ps/DIV

08262-010

Figure 10. 6.5 Gbps Output Eye, 20 Inch FR4 Input Channel (TP3 from Figure 7)

200mV/DI

25ps/DIV

08262-011

Figure 11. 6.5 Gbps Output Eye, 40 Inch FR4 Input Channel (TP3 from Figure 7)

Rev. 0 | Page 10 of 36

AD8155

V

200mV/DI

25ps/DIV

REFERENCE EYE DI AGRAM AT TP1

DATA OUT

PATTERN

GENERATOR

50Ω CABLES

2 2

TP1

INPUT

OUTPUT

AD8155

AC-COUPLED EVALUATION

BOARD

50Ω CABLES

2 2

Figure 12. Output Preemphasis Test Circuit

FR4 TEST BACKPL ANE

DIFFERENTIAL STRIPLINE TRACES

TP2

8mils WIDE, 8mils SPACE, 8mils DIELECTRIC HEIGHT

TRACE LENGT HS = 20 INCHES, 30 INCHES

50Ω CABLES

2 2

TP3

50Ω

HIGH

SPEED

SAMPLING

OSCILLOSCOPE

08262-012

200mV/DI

25ps/DIV

Figure 13. 6.5 Gbps Output Eye, 20 Inch FR4 Input Channel, PE = 0

(TP3 from Figure 12)

200mV/DI

25ps/DIV

Figure 14. 6.5 Gbps Output Eye, 30 Inch FR4 Input Channel, PE = 0

(TP3 from Figure 12)

200mV/DI

08262-013

25ps/DIV

08262-015

Figure 15. 6.5 Gbps Output Eye, 20 Inch FR4 Input Channel, PE = Best Setting,

Default Output Level (TP3 from Figure 12)

100mV/DI

08262-014

25ps/DIV

08262-016

Figure 16. 6.5 Gbps Output Eye, 30 Inch FR4 Input Channel, PE = Best Setting,

200 mV Output Level (TP3 from Figure 12)

Rev. 0 | Page 11 of 36

ANALOG DEVICES AD8155 Service Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

I2C TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS