ANALOG DEVICES AD8151 Service Manual

33 × 17, 3.2 Gbps

www.BDTIC.com/ADI

FEATURES

Low cost
33 × 17, fully differential, nonblocking array

3.2 Gbps per port NRZ data rate
Wide power supply range: +3.3 V, –3.3 V
Low power
425 mA (outputs enabled)
35 mA (outputs disabled)
LV PECL- and LV ECL-compatible
CMOS/TTL-level control inputs: 3 V to 5 V
Low jitter
No heat sinks required
Drives a backplane directly
Programmable output current
Optimize termination impedance
User-controlled voltage at the load
Minimize power dissipation
Individual output disable for busing and reducing power
Double row latch
Buffered inputs
184-lead LQFP package

GENERAL DESCRIPTION

Digital Crosspoint Switch

AD8151

APPLICATIONS

High speed serial backplane routing to Sonet OC-48

applications with FEC
Fiber optic network switching
Fiber channel
LVDS

FUNCTIONAL BLOCK DIAGRAM

INP INN

CS

UPDATE

RESET

.

RE

7

D

5

A

WE

OUTPUT

ADDRESS

DECODER

FIRST
RANK

17

7-BIT

LATCH

×

SECOND

RANK

17

×

7-BIT

LATCH

Figure 1.

INPUT

DECODERS

33 33

33×17

DIFFERENTIAL

SWITCH
MATRIX

AD8151

17

OUTP

17

OUTN

02169-001

The AD81511 is a member of the Xstream line of products,
offering a breakthrough in digital switching and a large switch
array (33 × 17) on very little power—typically less than 1.5 W.
It also operates at data rates in excess of 3.2 Gbps per port,
making it suitable for Sonet OC-48 applications with
8/10-bit forward-error correction (FEC). Furthermore, the
price of the AD8151 makes it affordable enough to be used for
lower data rates. The AD8151’s flexible supply voltages allow
the user to operate with either emitter-coupled logic (ECL) or
positive emitter-coupled logic (PECL) data levels, and with 3.3
V for further power reduction. The control interface is CMOS­/TTL-compatible (3 V to 5 V).

Its fully differential signal path reduces jitter and crosstalk,
while al

lowing the use of smaller, single-ended voltage swings.
The AD8151 is offered in a 184-lead LQFP package that
operates over the extended commercial temperature range
of 0°C to 85°C.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

150mV/DIV

70ps/DIV

Figure 2. Eye Pattern, 3.2 Gbps, PRBS 23

1

Patent pending.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

02169-002

AD8151

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

Maximum Power Dissipation..................................................... 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Typical Performance Characteristics ............................................. 9

Control Interface Truth Tables...................................................... 13

Control Interface Timing Diagrams ............................................14

Control Interface Programming Example .............................. 16

Control Interface ............................................................................ 17

Control Pin Description............................................................ 17

Control Interface Translators.................................................... 18

Circuit Description......................................................................... 19

Applications..................................................................................... 23

Input and Output Busing .......................................................... 23

Evaluation Board........................................................................ 23

Power Supplies............................................................................ 24

Configuration Programming.................................................... 25

Software Installation.................................................................. 25

Software Operation.................................................................... 26

Outline Dimensions....................................................................... 38

Ordering Guide .......................................................................... 38

REVISION HISTORY

12/05—Rev. A to Rev. B

Changes to Table 1............................................................................ 3

Changes to Figure 4.......................................................................... 5

Changes to Table 3............................................................................ 6

Changes to Table 4.......................................................................... 13

Changes to Figure 51...................................................................... 35

Changes to Ordering Guide.......................................................... 38

9/05—Rev. 0 to Rev. A

Updated Format..............................................................Universal

hange to Figure 51 ................................................................... 34

C

Change to Ordering Guide........................................................ 37

4/01—Revision 0: Initial Version

Rev. B | Page 2 of 40

AD8151

www.BDTIC.com/ADI

SPECIFICATIONS

@ 25°C, VCC = 3.3 V to 5 V, VEE = 0 V, RL = 50 Ω (see Figure 26), I

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Max Data Rate/Channel (NRZ) 2.5 3.2 Gbps
Channel Jitter Data rate = 3.2 Gbps 52 ps p-p
RMS Channel Jitter 8 ps
Propagation Delay Input to output 650 ps
Propagation Delay Match See Figure 23 ±50 ±100 ps
Output Rise/Fall Time 20% to 80% 100 ps

INPUT CHARACTERISTICS

Input Voltage Swing Single-ended (see Figure 18) 200 1000 mV p-p
Input Bias Current 2 μA
Input Capacitance 2 pF
Input VIN High

Input VIN Low

OUTPUT CHARACTERISTICS

Output Voltage Swing Differential 800 mV p-p
Output Voltage Range (See Figure 19)

Output Current 5 25 mA
Output Capacitance 2 pF
Output V

Output V

POWER SUPPLY

Operating Range

PECL, VCC V
ECL, VEE V
VDD 3 5 V
VSS 0 V

Quiescent Current

VDD 2 mA

VEE All outputs enabled, I
T
All outputs disabled 35 mA
THERMAL CHARACTERISTICS

Operating Temperature Range 0 85 °C

θJA

LOGIC INPUT CHARACTERISTICS VDD = 3 V dc to 5 V dc

Input VIN High 1.9 VDD V
Input VIN Low 0 0.9 V

High

OUT

Low VCC V

OUT

= 0 V 3.0 5.25 V

EE

= 0 V –5.25 –3.0 V

CC

to T

MIN

30 °C/W

450 mA

MAX

= 16 mA, unless otherwise noted.

OUT

VCC − 1.2

VCC − 2.4

VCC − 1.8

VCC − 1.8

= 16 mA 425 mA

OUT

V

V

V

V

CC

VCC − 1.4

V

CC

V

Rev. B | Page 3 of 40

AD8151

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 2.

Parameter Rating

Supply Voltage

VDD − VEE
VCC − VEE

VDD − VSS

VSS − VEE

VSS − VCC

VDD − VCC

Internal Power Dissipation

184-Lead LQFP (ST-184) 4.2 W
Differential Input Voltage 2.0 V
Storage Temperature Range –65°C to +125°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature, θJA

10.5 V

5.5 V

5.5 V

5.5 V

5.5 V

5.5 V

30°C/W

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8151 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit may cause a shift in
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175°C for an extended period can result in device failure. To
ensure proper operation, it is necessary to observe the
maximum power derating curves shown in

6

5

4

Figure 3.

TJ = 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress

3

rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

MAXIMUM POWER DISSIPATION (W)

2

1

–10 9080706050403020100

AMBIENT TEMPERATURE (°C)

Figure 3.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

02169-003

Rev. B | Page 4 of 40

AD8151

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V
IN20P
IN20N

V
IN21P
IN21N

V
IN22P
IN22N

V
IN23P
IN23N

V
IN24P
IN24N

V
IN25P
IN25N

V
IN26P
IN26N

V
IN27P
IN27N

V
IN28P
IN28N

V
IN29P
IN29N

V
IN30P
IN30N

V
IN31P
IN31N

V
IN32P
IN32N

V

V

CC

V

OUT16N

OUT16P

VEEA16

V

EEVEEVEEVEEVEE

IN19N

IN19P

IN18N

IN18P

IN17N

179

178

177

IN17P

176

175

V

184

183

182

181

180

1

EE

2
3
4

EE

5
6
7

EE

8
9

10

EE

11
12
13

EE

14
15
16

EE

17
18
19

EE

20
21
22

EE

23
24
25

EE

26
27
28

EE

29
30
31

EE

32
33
34

EE

35
36
37

EE

38
39
40

EE

41
42

EE

43
44
45
46

EE

PIN 1
INDICATOR

IN16N

174

IN16P

173

CCVDD

V

RESETCSREWEUPDATEA0A1A2A3A4D0D1D2D3D4D5D6

171

170

169

168

167

166

165

164

163

172

162

161

160

AD8151

184L LQFP

TOP VIEW

(Not to Scale)

159

158

157

156

155

154

REF

SSVCCVEEVEEVEEVEE

EE

153

V

152

REF

151

V

150

149

148

IN15N

147

IN15P

146

145

IN14N

144

IN14P

143

142

IN13N

141

IN13P

140

139

138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93

V

EE

IN12N
IN12P
V

EE

IN11N
IN11P
V

EE

IN10N
IN10P
V

EE

IN09N
IN09P
V

EE

IN08N
IN08P
V

EE

IN07N
IN07P
V

EE

IN06N
IN06P
V

EE

IN05N
IN05P
V

EE

IN04N
IN04P
V

EE

IN03N
IN03P
V

EE

IN02N
IN02P
V

EE

IN01N
IN01P
V

EE

IN00N
IN00P
V

EE

V

CC

VEEA0
OUT00P
OUT00N
V

A1

EE

V

EE

4748495051525354555657

EE

V

A15

A14

A13

EE

EE

V

V

OUT13P

OUT13N

OUT15P

OUT15N

EE

V

OUT14P

OUT14N

596061626364656667

58

A12

A11

EE

EE

V

OUT12N

OUT12P

OUT11P

OUT11N

V

OUT10N

OUT10P

A10

EE

V

OUT09N

68

A9
V

OUT09P

697071

EE

OUT08N

A8
V

OUT08P

72

747576777873798081

A7

EE

EE

V

OUT07P

OUT07N

OUT06N

A6
V

OUT06P

EE

OUT05N

A5
V

OUT05P

EE

Figure 4. Pin Configuration

Rev. B | Page 5 of 40

82

OUT04P

OUT04N

A4
V

EE

848586

OUT03P

OUT03N

87838889909192

A3

A2

EE

EE

V

V

OUT02P

OUT02N

OUT01P

OUT01N

EE

V

02169-004

AD8151

www.BDTIC.com/ADI

Table 3. Pin Function Descriptions

Pin No. Mnemonic Type Description

V

1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31,
34, 37, 40, 42, 46, 47, 92, 93, 99,
102, 105, 108, 111, 114, 117, 120,
123, 126, 129, 132, 135, 138, 139,
142, 145, 148, 172, 175, 178, 181,
184

2 IN20P PECL/ECL High Speed Input
3 IN20N PECL/ECL High Speed Input Complement
5 IN21P PECL/ECL High Speed Input
6 IN21N PECL/ECL High Speed Input Complement
8 IN22P PECL/ECL High Speed Input
9 IN22N PECL/ECL High Speed Input Complement
11 IN23P PECL/ECL High Speed Input
12 IN23N PECL/ECL High Speed Input Complement
14 IN24P PECL/ECL High Speed Input
15 IN24N PECL/ECL High Speed Input Complement
17 IN25P PECL/ECL High Speed Input
18 IN25N PECL/ECL High Speed Input Complement
20 IN26P PECL/ECL High Speed Input
21 IN26N PECL/ECL High Speed Input Complement
23 IN27P PECL/ECL High Speed Input
24 IN27N PECL/ECL High Speed Input Complement
26 IN28P PECL/ECL High Speed Input
27 IN28N PECL/ECL High Speed Input Complement
29 IN29P PECL/ECL High Speed Input
30 IN29N PECL/ECL High Speed Input Complement
32 IN30P PECL/ECL High Speed Input
33 IN30N PECL/ECL High Speed Input Complement
35 IN31P PECL/ECL High Speed Input
36 IN31N PECL/ECL High Speed Input Complement
38 IN32P PECL/ECL High Speed Input
39 IN32N PECL/ECL High Speed Input Complement
41, 98, 149, 171 VCC Power Supply Most Positive PECL Supply (Common with Other Points Labeled VCC)
43 OUT16N PECL/ECL High Speed Output Complement
44 OUT16P PECL/ECL High Speed Output
45 VEEA16 Power Supply Most Negative PECL Supply (Unique to this Output)
48 OUT15N PECL/ECL High Speed Output Complement
49 OUT15P PECL/ECL High Speed Output
50 VEEA15 Power Supply Most Negative PECL Supply (Unique to this Output)
51 OUT14N PECL/ECL High Speed Output Complement
52 OUT14P PECL/ECL High Speed Output
53 VEEA14 Power Supply Most Negative PECL Supply (Unique to this Output)
54 OUT13N PECL/ECL High Speed Output Complement
55 OUT13P PECL/ECL High Speed Output
56 VEEA13 Power Supply Most Negative PECL Supply (Unique to this Output)
57 OUT12N PECL/ECL High Speed Output Complement
58 OUT12P PECL/ECL High Speed Output
59 VEEA12 Power Supply Most Negative PECL Supply (Unique to this Output)
60 OUT11N PECL/ECL High speed Output Complement
61 OUT11P PECL/ECL High speed Output
62 VEEA11 Power Supply Most Negative PECL Supply (Unique to this Output)
63 OUT10N PECL/ECL High Speed Output Complement

Power Supply

EE

Most Negative PECL Supply (Common with O

)

V

EE

ther Points Labeled

Rev. B | Page 6 of 40

AD8151

www.BDTIC.com/ADI

Pin No. Mnemonic Type Description

64 OUT10P PECL/ECL High Speed Output
65 VEEA10 Power Supply Most Negative PECL Supply (Unique to this Output)
66 OUT09N PECL/ECL High Speed Output Complement
67 OUT09P PECL/ECL High Speed Output
68 VEEA9 Power Supply Most Negative PECL Supply (Unique to this Output)
69 OUT08N PECL/ECL High speed Output Complement
70 OUT08P PECL/ECL High Speed Output
71 VEEA8 Power Supply Most Negative PECL Supply (Unique to this Output)
72 OUT07N PECL/ECL High Speed Output Complement
73 OUT07P PECL/ECL High Speed Output
74 VEEA7 Power Supply Most Negative PECL Supply (Unique to this Output)
75 OUT06N PECL/ECL High Speed Output Complement
76 OUT06P PECL/ECL High Speed Output
77 VEEA6 Power Supply Most Negative PECL Supply (Unique to this Output)
78 OUT05N PECL/ECL High Speed Output Complement
79 OUT05P PECL/ECL High Speed Output
80 VEEA5 Power Supply Most Negative PECL Supply (Unique to this Output)
81 OUT04N PECL/ECL High Speed Output Complement
82 OUT04P PECL/ECL High Speed Output
83 VEEA4 Power Supply Most Negative PECL Supply (Unique to this Output)
84 OUT03N PECL/ECL High Speed Output Complement
85 OUT03P PECL/ECL High Speed Output
86 VEEA3 Power Supply Most Negative PECL Supply (Unique to this Output)
87 OUT02N PECL/ECL High Speed Output Complement
88 OUT02P PECL/ECL High Speed Output
89 VEEA2 Power Supply Most Negative PECL Supply (Unique to this Output)
90 OUT01N PECL/ECL High Speed Output Complement
91 OUT01 P PECL/ECL High Speed Output
94 VEEA1 Power Supply Most Negative PECL Supply (Unique to this Output)
95 OUT00N PECL/ECL High Speed Output Complement
96 OUT00P PECL/ECL High Speed Output
97 VEEA0 Power Supply Most Negative PECL Supply (Unique to this Output)
100 IN00P PECL/ECL High Speed Input
101 IN00N PECL/ECL High Speed Input Complement
103 IN01P PECL/ECL High Speed Input
104 IN01N PECL/ECL High Speed Input Complement
106 IN02P PECL/ECL High Speed Input
107 IN02N PECL/ECL High Speed Input Complement
109 IN03P PECL/ECL High Speed Input
110 IN03N PECL/ECL High Speed Input Complement
112 IN04P PECL/ECL High Speed Input
113 IN04N PECL/ECL High Speed Input Complement
115 IN05P PECL/ECL High Speed Input
116 IN05N PECL/ECL High Speed Input Complement
118 IN06P PECL/ECL High Speed Input
119 IN06N PECL/ECL High Speed Input Complement
121 IN07P PECL/ECL High Speed Input
122 IN07N PECL/ECL High Speed Input Complement
124 IN08P PECL/ECL High Speed Input
125 IN08N PECL/ECL High Speed Input Complement
127 IN09P PECL/ECL High Speed Input
128 IN09N PECL/ECL High Speed Input Complement

Rev. B | Page 7 of 40

AD8151

www.BDTIC.com/ADI

Pin No. Mnemonic Type Description

130 IN10P PECL/ECL High Speed Input
131 IN10N PECL/ECL High Speed Input Complement
133 IN11P PECL/ECL High Speed Input
134 IN11N PECL/ECL High Speed Input Complement
136 IN12P PECL/ECL High Speed Input
137 IN12N PECL/ECL High Speed Input Complement
140 IN13P PECL/ECL High Speed Input
141 IN13N PECL/ECL High Speed Input Complement
143 IN14P PECL/ECL High Speed Input
144 IN14N PECL/ECL High Speed Input Complement
146 IN15P PECL/ECL High Speed Input
147 IN15N PECL/ECL High Speed Input Complement
150 VEEREF R Program

151 REF R Program Connection Point for Output Logic Pull-Down Programming Resistor
152 VSS Power Supply Most Negative Control Logic Supply
153 D6 TTL

154 D5 TTL Bit 32—MSB Input Select
155 D4 TTL Bit 16
156 D3 TTL Bit 8
157 D2 TTL Bit 4
158 D1 TTL Bit 2
159 D0 TTL Bit 1—LSB Input Select
160 A4 TTL Bit 16—MSB Output Select
161 A3 TTL Bit 8
162 A2 TTL Bit 4
163 A1 TTL Bit 2
164 A0 TTL Bit 1—LSB Output Select
165
166

167
168
169
170 VDD Power Supply Most Positive Control Logic Supply

173 IN16P PECL/ECL High Speed Input
174 IN16N PECL/ECL High Speed Input Complement
176 IN17P PECL/ECL High Speed Input
177 IN17N PECL/ECL High Speed Input Complement
179 IN18P PECL/ECL High Speed Input
180 IN18N PECL/ECL High Speed Input Complement
182 IN19P PECL/ECL High Speed Input
183 IN19N PECL/ECL High Speed Input Complement

UPDATE
WE
RE
CS
RESET

TTL Second Rank Program
TTL First Rank Program
TTL Enable Readback
TTL Enable Chip to Accept Programming
TTL Disable All Outputs (Hi-Z)

Connection Point for Output Logic Pull-Down Programming Resistor

t be Connected to V

(Mus

Enable/Disable

Output

)

EE

Rev. B | Page 8 of 40

AD8151

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

150mV/DIV

p-p = 43ps
STD DEV = 8ps

150mV/DIV

100ps/DIV

Figure 5. Eye Pattern 2.5 Gbps, PRBS 23

20ps/DIV

Figure 6. Jitter @ 2.5 Gbps, PRBS 23

02169-005

02169-006

150mV/DIV

p-p = 53ps
STD DEV = 8ps

150mV/DIV

70ps/DIV

Figure 8. Eye Pattern 3.2 Gbps, PRBS 23

20ps/DIV

Figure 9. Jitter @ 3.2 Gbps, PRBS 23

02169-008

02169-009

100

90

80

70

60

50

40

EYE WIDTH (%)

30

20

10

0

0.5 3.53.02.52.01.51.0

% EYE WIDTH =

(CLOCK PERIOD – JITTER p-p)

CLOCK PERIOD

DATA RATE (Gbps)

Figure 7. Eye Width vs. Data Rate, PRBS 23

×

100

02169-007

100

90

80

70

60

% EYE HEIGHT =

50

40

EYE HEIGHT (%)

30

20

10

0

0.5 3.53.02.52.01.51.0

Figure 10. Eye Height vs. Data Rate, PRBS 23

Rev. B | Page 9 of 40

@ DATA RATE)

(V

OUT

V

@ 0.5Gbps

OUT

DATA RATE (Gbps)

×

100

02169-010

AD8151

www.BDTIC.com/ADI

100

90

80

70

60

50

JITTER (ps)

40

30

20

10

STANDARD DEVIATION

0

1.0 3.53.02.52.01.5

p-p = 38ps
STD DEV = 7.7ps

PEAK-PEAK

JITTER

DATA RATE (Gbps)

Figure 11. Jitter vs. Data Rate, PRBS 23

02169-011

100

JITTER (ps)

90

80

70

60

50

40

30

20

10

0

098070605040302010

3.2Gbps STD DEV

TEMPERATURE (°C)

Figure 14. Jitter vs. Temperature, PRBS 23

3.2Gbps JITTER

2.5Gbps JITTER

2.5Gbps STD DEV

02169-014

0

150mV/DIV

100ps/DIV

Figure 12. Crosstalk, 2.5 Gbps, PRBS 23, Attack Signal Is Off

p-p = 70ps
STD DEV = 8ps

150mV/DIV

100ps/DIV

Figure 13. Crosstalk, 2.5 Gbps, PRBS 23, Attack Signal Is On

02169-012

02169-013

150mV/DIV

p-p = 32ps
STD DEV = 4.7ps

75ps/DIV

Figure 15. Crosstalk, 3.2 Gbps, PRBS 23, Attack Signal Is Off

150mV/DIV

p-p = 70ps
STD DEV = 9ps

75ps/DIV

Figure 16. Crosstalk, 3.2 Gbps, PRBS 23, Attack Signal Is On

02169-015

02169-016

Rev. B | Page 10 of 40

AD8151

www.BDTIC.com/ADI

p-p = 43ps
STD DEV = 8ps

150mV/DIV

1.4ns/DIV

Figure 17. Response, 2.5 Gbps,

3

2-Bit Pattern 1111 1111 0000 0000 0101 0101 0011 0011

100

90

80

70

60

50

40

30

3.2Gbps JITTER

PEAK-TO-PEAK JITTER (ps)

20

10

0

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Figure 18. Jitter vs. Single-Ended I

2.5Gbps JITTER

INPUT AMPLITUDE (V)

nput Amplitude, PRBS 23

02169-017

02169-018

p-p = 43ps
STD DEV = 8ps

150mV/DIV

1.1ns/DIV

Figure 20. Response, 3.2 Gbps,

3

2-Bit Pattern 1111 1111 0000 0000 0101 0101 0011 0011

100

90

80

70

60

50

40

30

PEAK-TO-PEAK JITTER (ps)

20

10

0
–5.0 –4.8 –4.6 –4.4 –4.2 –4.0 –3.8 –3.6 –3.4 –3.2 –3.0

3.2Gbps

2.5Gbps

VEE (V)

Figure 21. Jitter vs. Supply, PRBS 23

02169-020

02169-021

100

90

80

70

60

3.2Gbps

50

40

30

PEAK-TO-PEAK JITTER (ps)

20

10

0
–1.6 –1.4 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6

2.5Gbps

VIH (V)

Figure 19. Jitter vs. VIH, PRBS 23

02169-019

100

90

80

70

3.2Gbps

60

50

2.5Gbps

40

30

PEAK-TO-PEAK JITTER (ps)

20

10

0
–1.4 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2

Figure 22. Jitter vs. V

Rev. B | Page 11 of 40

VOH (V)

, PRBS 23, Output Amplitude = 0.4 V Single-Ended

OH

02169-022

AD8151

www.BDTIC.com/ADI

100

90

80

70

60

50

40

FREQUENCY

30

20

10

0

550 570 590 610 630 650 670 690 710 730

PROPAGATION DELAY (ps)

Figure 23. Variation in Channel-to-Channel Delay, All 561 Points

02169-023

200

150

100

50

0

–50

–100

PROPAGATION DELAY (ps)

–150

–200

–100 –80 –60 –40 –20 0 20 40 60 80 100

NORMALIZED TEMPERATURE (°C)

Figure 25. Propagation Delay, Normalized at 25°C vs. Temperature

02169-025

100

90

80

70

2.5Gbps

60

50

3.2Gbps

40

30

PEAK-TO-PEAK JITTER (ps)

20

10

0

5 1015202

OUTPUT CURRENT (mA)

Figure 24. Jitter vs. I

, PRBS 23

OUT

5

02169-024

PRBS

GENERATOR

DATA OUT

DATA OUT

VCC = 0V, VEE = –3.3V, VTT = –1.6V, VDD = 5V, VSS = 0V

= 1.54kΩ, I

R

SET

= 0.8V p-p EXCEPT AS NOTED

V

IN

V

CCVCCVTT

1.65kΩ

–6dB

–6dB

1.65kΩ

OUT

AD8151

P

P
IN OUT

105Ω

N

N

V

EE

V

EE

= 16mA, VOH = –0.8V, VOL = –1.2V

Figure 26. Test Circuit

49.9Ω

49.9Ω

V

TT

HIGH SPEED

SAMPLING

OSCILLOSCOPE

50Ω

50Ω

02169-026

Rev. B | Page 12 of 40