ANALOG DEVICES AD8134 Service Manual

Triple Differential Driver

–

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FEATURES

Triple high speed differential driver

225 MHz, −3 dB large signal bandwidth
450 MHz, −3 dB small signal bandwidth
Easily drives 1.4 V p-p video signal into doubly terminated

100 Ω UT
1600 V/μs slew rate
Fixed internal gain of 2

Internal common-mode feedback network

Output balance error −60 dB @ 50 MHz

On-chip sync-on-common-mode circuitry
Output pull-down feature for line isolation
Differential input and output
Differential-to-differential or single-ended-to-differential

oper

High isolation between amplifiers: 80 dB @ 10 MHz
Low distortion: 64 dB SFDR @ 10 MHz on 5 V supply,

R

L, dm

Low offset: 3 mV typical output-referred on 5 V supply
Low power: 26.5 mA @ 5 V for three drivers and sync circuitry
Wide supply voltage range: +5 V to ±5 V
Available in space-saving packaging: 4 mm × 4 mm LFCSP

APPLICATIONS

Keyboard-video-mouse (KVM) networking

GENERAL DESCRIPTION

The AD8134 is a major advancement beyond using discrete
op amps for driving differential RGB signals over twisted pair
cable. The AD8134 is a triple, low cost differential or single­ended input to differential output driver, and each amplifier has
a fixed gain of 2 to compensate for the attenuation of the line
termination resistors. The AD8134 is specifically designed for
RGB signals but can be used for any type of analog signals or
high speed data transmission. The AD8134 is capable of driving
either Category 5 (Cat-5) unshielded twisted pair (UTP) cable
or differential printed circuit board transmission lines with
minimal signal degradation.

A unique feature that allows the use
horizontal and vertical video sync signals over the three
common-mode channels with minimal electromagnetic
interference (EMI) radiation is included on-chip.

The outputs of the AD8134 can be set to a low voltage state that
al

lows easy differential multiplexing of multiple drivers on the

same twisted pair cable, when used with external series diodes.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

P cable

ation

= 200 Ω

r to transmit balanced

With Sync-On-Common-Mode

AD8134

FUNCTIONAL BLOCK DIAGRAM

(SYNC)

SYNC

S–

SYNC

VS+–IN G

24 23 22 21 20

AD8134

OPD

1

V

2

S–

–IN R

3

+IN R

4

V

S–

OUT R

0

ΔV

–10

ΔV

–20

–30

–40
–50
–60

–70

–80

OUTPUT BALANCE ERROR (dB)

–90

–100

1 10 100 500

R

5

6

7 8 9 10 11

+OUT R

= 2V p-p

OUT, dm

/ΔV

OUT, cm

S+

V

OUT, dm

Figure 2. Output Balance vs. Frequency

The AD8134 driver is a natural complement to the AD8143,

AD8129, and AD8130 differential receivers.

Manufactured on the Analog Devices next generation XFCB
b

ipolar process, the AD8134 has a large signal bandwidth of
225 MHz and a slew rate of 1600 V/μs. The AD8134 has an
internal common-mode feedback feature that provides output
gain and phase matching that is balanced to −60 dB at 50 MHz,
suppressing harmonics and reducing radiated EMI.

The AD8134 is available in a 24-lead LFCSP and can operate
o

ver the −40°C to +85°C extended industrial temperature range.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

V

+IN G

V

H

19

×2

G

B

12

S+

V

+OUT B

–OUT G

+OUT G

Figure 1.

VS = ±5V

FREQUENCY (MHz)

18

SYNC LEVEL

17

V

S+

16

–IN B
+IN B

15

V

14

S–

–OUT B

13

(SYNC)

VS = +5V

04770-001

04770-018

AD8134

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Driving a Capacitive Load......................................................... 13

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics............................................. 7

Theory of Operation ...................................................................... 12

Definition of Terms.................................................................... 12

Analyzing an Application Circuit.............................................12

Closed-Loop Gain...................................................................... 12

Calculating an Application Circuit’s Input Impedance ......... 13

Output Pull-Down (OPD) ........................................................ 13

Sync-On-Common-Mode......................................................... 14

Applications..................................................................................... 15

Driving RGB Video Over Cat-5 Cable .................................... 15

How to Apply the Output Pull-Down Feature ....................... 16

KVM Networks........................................................................... 16

Video Sync-On-Common-Mode............................................. 16

Level-Shifting Sync Pulses on ±5 V Supplies.......................... 17

Layout and Power Supply Decoupling Considerations......... 18

Amplifier-to-Amplifier Isolation ............................................. 18

Exposed Paddle (EP).................................................................. 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

Input Common-Mode Voltage Range in Single-Supply

Applications.................................................................................13

REVISION HISTORY

10/05—Rev. Sp0 to Rev. A

Changes to Features and General Description ............................. 1

Changes to Figure 32...................................................................... 14

Changes to Figure 33...................................................................... 15

Changes to Figure 34...................................................................... 17

Added Level-Shifting Sync Pulses on ±5 V Supplies Section ... 17

Changes to Ordering Guide.......................................................... 19

7/04—Revision Sp0: Initial Version

Rev. A | Page 2 of 20

AD8134

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SPECIFICATIONS

VS = ±5 V, H

Table 1.

Parameter Conditions Min Typ Max Unit

DIFFERENTIAL INPUT PERFORMANCE
DYNAMIC PERFORMANCE

−3 dB Small Signal Bandwidth VO = 0.2 V p-p 450 MHz

−3 dB Large Signal Bandwidth VO = 2 V p-p 225 MHz
Bandwidth for 0.1 dB Flatness VO = 0.2 V p-p 60 MHz
V
Slew Rate VO = 2 V p-p, 25% to 75% 1600 V/μs
Settling Time to 0.1% VO = 2 V step 15 ns
Isolation Between Amplifiers

DIFFERENTIAL INPUT CHARACTERISTICS

Input Common-Mode Voltage Range −5 to +5 V
Input Resistance Differential 1.5 kΩ
Single-ended input 1.13 kΩ
Input Capacitance Differential 1 pF
DC CMRR ΔV

DIFFERENTIAL OUTPUT CHARACTERISTICS

Differential Signal Gain ΔV
Output Voltage Swing Each single-ended output VS− + 1.9 VS+ − 1.6 V
Output Offset Voltage −24 +4 +24 mV
Output Offset Drift T
Output Balance Error f = 50 MHz −60 dB
DC −70 −54 dB
Output Voltage Noise (RTO) f = 1 MHz 25 nV/√Hz

Output Short-Circuit Current 90 mA
COMMON-MODE SYNC PERFORMANCE
SYNC DYNAMIC PERFORMANCE

Slew Rate V
H

AND V

SYNC

Input Low Voltage VS− to −2.75 V

Input High Voltage −2.25 to VS+ V
SYNC LEVEL INPUT

Input Voltage Range For linear operation V

Setting to Achieve 0.5 V Pulse Levels VS− + 0.5 V

Gain to Red Common-Mode Output ΔV

Gain to Green Common-Mode Output ΔV

Gain to Blue Common-Mode Output ΔV
POWER SUPPLY

Operating Range +4.5 ±6 V

Quiescent Current 31 33 mA

PSRR ΔV
OUTPUT PULL-DOWN PERFORMANCE

OPD Input Low Voltage VS− to VS+ − 4.15 V

OPD Input High Voltage VS+ − 3.15 to VS+ V

OPD Input Bias Current 67 90 μA

OPD Assert Time 100 ns

OPD De-Assert Time 100 ns

Output Voltage When OPD Asserted Each output, OPD input @ VS+ VS− + 0.86 VS− + 0.90 V

SYNC

and V

SYNC

= VS−, R

= 200 Ω @ 25°C, unless otherwise noted. T

L, dm

= 2 V p-p 55 MHz

O

f = 10 MHz, between Amplifier R and

MIN

to T

= −40°C to +85°C.

MAX

80 dB

Amplifier G

/ΔV

, ΔV

OUT, dm

OUT, dm

to T

MIN

OUT, cm

INPUTS

SYNC

O, cm

O, cm

O, cm

OUT, dm

IN, cm

/ΔV

IN, dm

MAX

= −1 V to +1 V; 25% to 75% 1000 V/μs

/ΔV

SYNC LEVEL

/ΔV

SYNC LEVEL

/ΔV

SYNC LEVEL

/ΔVS; ΔVS = ±1V −54 −48 dB

= ±1 V −48 dB

IN, cm

, ΔV

= ±1 V 1.920 1.955 2.000 V/V

IN, dm

±30 μV/°C

0.95 1.02 1.07 V/V

1.91 2.04 2.14 V/V

0.95 1.02 1.07 V/V

Rev. A | Page 3 of 20

AD8134

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VS+ = 5 V, VS− = 0 V, H

Table 2.

Parameter Conditions Min Typ Max Unit

DIFFERENTIAL INPUT PERFORMANCE
DYNAMIC PERFORMANCE

−3 dB Small Signal Bandwidth VO = 0.2 V p-p 400 MHz

−3 dB Large Signal Bandwidth VO = 2 V p-p 200 MHz
Bandwidth for 0.1 dB Flatness VO = 0.2 V p-p 50 MHz
Slew Rate VO = 2 V p-p, 25% to 75% 1400 V/μs
Settling Time to 0.1% VO = 2 V step 14 ns
Isolation Between Amplifiers

DIFFERENTIAL INPUT CHARACTERISTICS

Input Common-Mode Voltage Range 0 to 5 V
Input Resistance Differential 1.5 kΩ
Single-ended input 1.13 kΩ
Input Capacitance Differential 1 pF
DC CMRR ΔV

DIFFERENTIAL OUTPUT CHARACTERISTICS

Differential Signal Gain ΔV
Output Voltage Swing Each single-ended output VS− + 1.25 VS+ − 1.15 V
Output Offset Voltage −24 3 +24 mV
Output Offset Drift T
Output Balance Error f = 50 MHz −60 dB
DC −70 −54 dB
Output Voltage Noise f = 1 MHz 25 nV/√Hz

Output Short-Circuit Current 90 mA
COMMON-MODE SYNC PERFORMANCE
SYNC DYNAMIC PERFORMANCE

Slew Rate V
H

SYNC

AND V

INPUTS

SYNC

Input Low Voltage VS− to 1.10 V

Input High Voltage 1.40 to V
SYNC LEVEL INPUT

Input Voltage Range For linear operation V

Setting to Achieve 0.5 V Pulse Levels VS− + 0.5 V

Gain to Red Common-Mode Output ΔV

Gain to Green Common-Mode Output ΔV

Gain to Blue Common-Mode Output ΔV
POWER SUPPLY

Operating Range +4.5 ±6 V

Quiescent Current 26.5 27.5 mA

PSRR −54 −48 dB
OUTPUT PULL-DOWN PERFORMANCE

OPD Input Low Voltage VS− to VS+ − 3.85 V

OPD Input High Voltage VS+ − 2.85 to VS+ V

OPD Input Bias Current 63 80 μA

OPD Assert Time 100 ns

OPD De-Assert Time 100 ns

Output Voltage When OPD Asserted Each output, OPD input @ VS+ VS− + 0.79 VS− + 0.82 V

SYNC

and V

SYNC

= VS−, R

= 200 Ω @ 25°C, unless otherwise noted. T

L, dm

f = 10 MHz, between Amplifier R and

75 dB

MIN

to T

= −40°C to +85°C.

MAX

Amplifier G

/ΔV

, ΔV

OUT, dm

OUT, dm

MIN

OUT, cm

O, cm

O, cm

O, cm

IN, cm

/ΔV

IN, dm

to T

MAX

= −1 V to +1 V; 25% to 75% 700 V/μs

/ΔV

SYNC LEVEL

/ΔV

SYNC LEVEL

/ΔV

SYNC LEVEL

= ±1 V −48 dB

IN, cm

, ΔV

= ±1 V 1.920 1.955 2.000 V/V

IN, dm

±30 μV/°C

S+

0.97 1.02 1.06 V/V

1.94 2.03 2.10 V/V

0.96 1.02 1.05 V/V

V

Rev. A | Page 4 of 20

AD8134

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ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage 12 V
H

, V

SYNC

, Sync Level ±V

SYNC

S

Power Dissipation See Figure 3
Input Common-Mode Voltage ±V

S

Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered in a circuit board in still air.

Table 4. Thermal Resistance with the Underside Pad
Thermall

Package Type/PCB Type θ

24-Lead LFCSP/4-Layer 70 °C/W

Maximum Power Dissipation

The maximum safe power dissipation in the AD8134 package is
limited by the associated rise in junction temperature (T

y Connected to a Copper Plane

JA

Unit

) on

J

The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
quiescent current (I
and common-mode currents flowing to the loads, as well as
currents flowing through the internal differential and common­mode feedback loops. The internal resistor tap used in the
common-mode feedback loop places a 4 kΩ differential load on
the output. RMS output voltages should be considered when
dealing with ac signals.

Airflow reduces θ
with the package leads from metal traces, through holes,
ground, and power planes reduce the θ
the underside of the package must be soldered to a pad on the
PCB surface that is thermally connected to a PCB plane to
achieve the specified θ

Figure 3 shows the maximum safe power dissipation in the

ackage vs. the ambient temperature for the 24-lead LFCSP

p
(70°C/W) on a JEDEC standard 4-layer board with the
underside paddle soldered to a pad that is thermally connected
to a PCB plane. θ

4.0

3.5

3.0

2.5

the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8134. Exceeding a junction temperature
of 175°C for an extended period can result in changes in the
silicon devices potentially causing failure.

2.0

1.5

1.0

MAXIMUM POWER DISSIPATION (W)

0.5

0

–40 –20 0 20 40 60

Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

). The load current consists of differential

S

. In addition, more metal directly in contact

JA

.

JA

values are approximations.

JA

AMBIENT TEMPERATURE (°C)

) is the sum of the

D

) times the

S

. The exposed pad on

JA

LFCSP

80

04770-017

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 5 of 20

AD8134

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

(SYNC)

SYNC

S–

SYNC

+IN G

V

×2

G

–OUT G

+OUT G

AD8134

750Ω

V

H

19

18

SYNC LEVEL

(SYNC)

17

V

S+

16

–IN B
+IN B

15

B

S+

V

12

+OUT B

1.5kΩ

14

13

V

V

S–

–OUT B

+5V

S+

04770-001

0.1μF ON ALL
PINS

V

S+

VS+–IN G

24 23 22 21 20

AD8134

OPD

1

V

2

S–

–IN R

3

+IN R

4

V

OUT R

S–

R

5

6

7 8 9 10 11

V

+OUT R

S+

Figure 4. 24-Lead LFCSP

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 OPD Output Pull Down.
2, 5, 14, 21 V

S−

Negative Power Supply Voltage.
3 −IN R Inverting Input, Red Amplifier.
4 +IN R Noninverting Input, Red Amplifier.
6 −OUT R Negative Output, Red Amplifier.
7 +OUT R Positive Output, Red Amplifier.
8, 11, 17, 24 V

S+

Positive Power Supply Voltage.
9 +OUT G Positive Output, Green Amplifier.
10 −OUT G Negative Output, Green Amplifier.
12 +OUT B Positive Output, Blue Amplifier.
13 −OUT B Negative Output, Blue Amplifier.
15 +IN B Noninverting Input, Blue Amplifier.
16 −IN B Inverting Input, Blue Amplifier.
18 SYNC LEVEL

19 H
20 V

SYNC

SYNC

The voltage applied to this pin controls the amplitude of the sync pulses that are applied to

ommon-mode voltages.

the c

Horizontal Sync Pulse Input.

Vertical Sync Pulse Input.
22 +IN G Noninverting Input, Green Amplifier.
23 −IN G Inverting Input, Green Amplifier.

50Ω

V

TEST

TEST
SIGNAL
SOURCE

53.6Ω

53.6Ω

50Ω

750Ω

MIDSUPPLY

+

–

1.5kΩ

R

200Ω V

L, dm

V

S–

–5V

0.1μF ON ALL
V

PINS

S–

Figure 5. Basic Test Circuit

Rev. A | Page 6 of 20

–

OUT, dm

+

04770-034