ANALOG DEVICES AD8123 Service Manual
Triple Differential Receiver with
V
www.BDTIC.com/ADI
FEATURES
Compensates cables to 300 meters for wideband video
Fast rise and fall times
4.9 ns with 2 V step @ 150 meters of UTP cable
8.0 ns with 2 V step @ 300 meters of UTP cable
55 dB peak gain at 100 MHz
Two frequency response gain adjustment pins
High frequency peaking adjustment (V
Broadband flat gain adjustment (V
Pole location adjustment pin (V
POLE
)
Compensates for variations between cables
Can be optimized for either UTP or coaxial cable
DC output offset adjust (V
OFFSET
)
Low output offset voltage: 24 mV
Compensates both RGB and YPbPr
Two on-chip comparators with hysteresis
Can be used for common-mode sync extraction
Available in 40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
Keyboard-video-mouse (KVM)
Digital signage
RGB video over UTP cables
Professional video projection and distribution
HD video
Security video
GENERAL DESCRIPTION
The AD8123 is a triple, high speed, differential receiver and
equalizer that compensates for the transmission losses of UTP
and coaxial cables up to 300 meters in length. Various gain
stages are summed together to best approximate the inverse
frequency response of the cable. Logic circuitry inside the AD8123
controls the gain functions of the individual stages so that the
lowest noise can be achieved at short-to-medium cable lengths.
This technique optimizes its performance for low noise, shortto-medium range applications, while at the same time provides
the high gain bandwidth required for long cable equalization
(up to 300 meters). Each channel features a high impedance
differential input that is ideal for interfacing directly with the cable.
The AD8123 has three control pins for optimal cable
compensation, as well as an output offset adjust pin. Two
voltage-controlled pins are used to compensate for different
cable lengths; the V
peaking and the V
which compensates for the low frequency flat cable loss.
pin controls the amount of high frequency
PEAK
pin adjusts the broadband flat gain,
GAIN
GAIN
)
PEAK
)
Adjustable Line Equalization
AD8123
FUNCTIONAL BLOCK DIAGRAM
PEAKVPOLEVOFFSETVGAIN
AD8123
–IN
R
+IN
R
–IN
G
+IN
G
–
IN
B
+IN
B
–IN
CMP1
+IN
CMP1
–IN
CMP2
+IN
CMP2
Figure 1.
For added flexibility, an optional pole adjustment pin, V
allows movement of the pole locations, allowing for the
compensation of different gauges and types of cable as well
as variations between different cables and/or equalizers. The
V
pin allows the dc voltage at the output to be adjusted,
OFFSET
adding flexibility for dc-coupled systems.
The AD8123 is available in a 6 mm × 6 mm, 40-lead LFCSP
a
nd is rated to operate over the extended temperature range of
−40°C to +85°C.
UXGA RESOLUT ION IMAGE
AFTER 300 MET ER CAT-5 CABLE
BEFORE AD8123.
UXGA RESOLUTION IMAGE
AFTER 300 MET ER CAT-5 CABLE
AFTER AD8123.
Figure 2.
OUT
OUT
OUT
OUT
OUT
R
G
B
CMP1
CMP2
6814-001
POLE
,
06814-019
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
AD8123
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TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Description .............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Input Common-Mode Voltage Range Considerations .........10
Applications Information .............................................................. 11
Basic Operation ..........................................................................11
Comparators ............................................................................... 11
Sync Pulse Extraction Using Comparators............................. 12
Using the V
Using the AD8123 with Coaxial Cable.................................... 13
Driving 75 Ω Video Cable With the AD8123 ........................ 13
Driving a Capacitive Load......................................................... 13
Filtering the RGB Outputs........................................................ 13
Power Supply Filtering............................................................... 14
Layout and Power Supply Decoupling Considerations......... 14
Input Common-Mode Range ................................................... 15
Small Signal Frequency Response ............................................ 15
Power-Down ............................................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
PEAK
, V
POLE
, V
GAIN
, and V
Inputs ................... 12
OFFSET
REVISION HISTORY
11/07—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Ordering Guide.......................................................... 16
8/07—Revision 0: Initial Version
Rev. A | Page 2 of 16
AD8123
www.BDTIC.com/ADI
SPECIFICATIONS
TA = 25°C, VS = ±5 V, RL = 150 Ω, Belden Cable (BL-7987R), V
Figure 17, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
PEAKING PERFORMANCE (NO CABLE)
Peak Frequency V
V
Peak Gain V
V
PEAK
PEAK
PEAK
PEAK
= 2 V, V
= 2 V, V
= 2 V, V
= 2 V, V
DYNAMIC PERFORMANCE
10% to 90% Rise/Fall Time V
V
Settling Time to 2% V
V
–3 dB Large Signal Bandwidth V
V
V
V
= 2 V step, 150 meters Cat-5 4.9 ns
OUT
= 2 V step, 300 meters Cat-5 8.0 ns
OUT
= 2 V step, 150 meters Cat-5 36 ns
OUT
= 2 V step, 300 meters Cat-5 106 ns
OUT
= 1 V p-p, <10 meters Cat-5 120 MHz
OUT
= 2 V p-p, <10 meters Cat-5 110 MHz
OUT
= 2 V p-p, 150 meters Cat-5 78 MHz
OUT
= 2 V p-p, 300 meters Cat-5 43 MHz
OUT
Integrated Output Voltage Noise 150 meter setting, integrated to 160 MHz 2.5 mV rms
300 meter setting, integrated to 160 MHz 24 mV rms
INPUT DC PERFORMANCE
Input Voltage Range −IN and +IN ±3.0 V
Maximum Differential Voltage Swing 4 V p-p
Voltage Gain ΔVO/ΔVI, V
Common-Mode Rejection Ratio (CMRR) At dc, V
At dc, V
PEAK
PEAK
At 1 MHz, V
Input Resistance Common mode 4.4 MΩ
Differential 3.7 MΩ
Input Capacitance Common mode 1.0 pF
Differential 0.5 pF
Input Bias Current 2.4 μA
V
Pin Current 28.9 μA
OFFSET
V
Pin Current 0.5 μA
GAIN
V
Pin Current 0.4 μA
PEAK
V
Pin Current 0.4 μA
POLE
ADJUSTMENT PINS
V
Input Voltage Range Relative to GND 0 to 2 V
PEAK
V
Input Voltage Range Relative to GND 0 to 2 V
POLE
V
Input Voltage Range Relative to GND 0 to 2 V
GAIN
V
to OUT Gain OUT/V
OFFSET
Maximum Flat Gain V
OFFSET
= 2 V 2 dB
GAIN
OUTPUT CHARACTERISTICS
Output Voltage Swing 150 Ω load −3.75 to +3.69 V
1 kΩ load −3.66 to +3.69 V
Output Offset Voltage Referred to output, V
Referred to output, V
Output Offset Voltage Drift Referred to output 33 μV/°C
= 0 V, V
OFFSET
= 0.6 V, V
GAIN
= 0.6 V, V
GAIN
= 0.6 V, V
GAIN
= 0.6 V, V
GAIN
set for 0 meters of cable 1 V/V
GAIN
= V
= V
GAIN
POLE
= V
= V
GAIN
POLE
= V
GAIN
= V
PEAK
, V
GAIN
, and V
PEAK
= 1 V 100 MHz
POLE
= 2 V 105 MHz
POLE
= 1 V 45 dB
POLE
= 2 V 55 dB
POLE
are set to recommended settings shown in
POLE
= 0 V −86 dB
= 2 V −67 dB
= 2 V −52 dB
POLE
, range limited by output swing 1 V/V
= V
= V
PEAK
PEAK
= V
GAIN
GAIN
= 0 V 24 mV
POLE
= V
= 2 V 32 mV
POLE
Rev. A | Page 3 of 16
AD8123
www.BDTIC.com/ADI
Parameter Conditions Min Typ Max Unit
POWER SUPPLY
Operating Voltage Range ±4.5 ±5.5 V
Positive Quiescent Supply Current 132 mA
Negative Quiescent Supply Current 126 mA
Supply Current Drift, ICC/I
Positive Power Supply Rejection Ratio DC, referred to output −51 dB
Negative Power Supply Rejection Ratio DC, referred to output −63 dB
Power Down, VIH (Minimum) Minimum Logic 1 voltage 1.1 V
Power Down, VIL (Maximum) Maximum Logic 0 voltage 0.8 V
Positive Supply Current, Powered Down V
Negative Supply Current, Powered Down V
COMPARATORS
Output Voltage Levels VOH/V
Hysteresis V
Propagation Delay t
Rise/Fall Times t
Output Resistance 0.03 Ω
OPERATING TEMPERATURE RANGE −40 +85 °C
EE
80 μA/°C
= V
= V
PEAK
GAIN
= V
PEAK
GAIN
OL
HYST
PD, LH/tPD, HL
RISE/tFAL L
= 0 V 1.1 μA
POLE
= V
= 0 V 0.7 μA
POLE
3.33/0.043 V
70 mV
17.5/10.0 ns
9.3/9.3 ns
Rev. A | Page 4 of 16
AD8123
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ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage 11 V
Power Dissipation See Figure 3
Input Voltage (Any Input) VS− − 0.3 V to VS+ + 0.3 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered in a circuit board in still air.
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
quiescent current (I
current is calculated by multiplying the load current by the
voltage difference between the associated power supply and the
output voltage. The total power dissipation due to load currents
is then obtained by taking the sum of the individual power
dissipations. RMS output voltages must be used when dealing
with ac signals.
Airflow reduces θ
with the package leads from metal traces, through holes, ground,
and power planes reduces the θ
underside of the package must be soldered to a pad on the PCB
surface that is thermally connected to a solid plane (usually the
ground plane) to achieve the specified θ
Figure 3 shows the maximum safe power dissipation in the
p
(29°C/W) on a JEDEC standard 4-layer board with the underside
Table 3. Thermal Resistance with the Underside Pad
Connected to t
Package Type/PCB Type θ
40-Lead LFCSP/4-Layer 29 °C/W
he Plane
JA
Unit
paddle soldered to a pad that is thermally connected to a PCB
plane. θ
Maximum Power Dissipation
The maximum safe power dissipation in the AD8123 package
is limited by the associated rise in junction temperature (T
) on
J
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8123. Exceeding a junction temperature
of 175°C for an extended time can result in changes in the
silicon devices, potentially causing failure.
). The power dissipation due to each load
S
. In addition, more metal directly in contact
JA
JA
ackage vs. the ambient temperature for the 40-lead LFCSP
values are approximations.
JA
7
6
5
4
3
2
MAXIMUM POWER DISSIPATION (W)
1
0
–40 –20 0 20 40 60 80
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
) is the sum of the
D
) times the
S
. The exposed paddle on the
.
JA
06814-025
ESD CAUTION
Rev. A | Page 5 of 16
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