Analog Devices AD7946 prd Datasheet

14-Bit, 500 kSPS PulSAR™

Preliminary Technical Data

FEATURES

14-bit resolution with no missing codes
Throughput: 500 kSPS
INL: ±0.4 LSB typ, ±1 LSB max (±0.0061 % of FSR)
S/(N + D): 85 dB @ 20 kHz
THD: −100 dB @ 20 kHz
Pseudo-differential analog input range

0 V to V

with V

REF

No pipeline delay
Single-supply 5V operation with

1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI®/QSPI™/µWire/DSP compatible
Daisy chain multiple ADCs and BUSY indicator
Power dissipation

3.3 mW @ 5 V/100 kSPS,

3.3 µW @ 5 V/100 SPS
Stand-by current: 1 nA
10-lead package: MSOP (MSOP-8 size) and

QFN (LFCSP), 3 mm × 3 mm same space as SOT-23

Pin-for-pin compatible with the 16-Bit AD7686

APPLICATIONS

Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process control

Table 1. MSOP, QFN (LFCSP)/SOT-23 14 and16-Bit ADC

Type 100 kSPS 250 kSPS 500 kSPS

16-Bit True
Differential

16-Bit Pseudo
Differential/Unipolar

16-Bit Unipolar AD7680
14-Bit Pseudo

Differential/Unipolar
14-Bit Unipolar AD7940

up to VDD

REF

AD7684 AD7687 AD7688

AD7683

AD7685
AD7694

AD7942

AD7686

AD7946

ADC in MSOP/QFN

AD7946

APPLICATION DIAGRAM

0.5 TO 5V 5V

0 TO VREF

IN+
IN–

REF

AD7946

GND

VDD

Figure 1.

VIO

SDI
SCK
SDO
CNV

GENERAL DESCRIPTION

The AD7946 is a 14-bit, charge redistribution successive
approximation, analog-to-digital converter (ADC) that operates
from a single 5V power supply, VDD. It contains a low power,
high speed, 14-bit sampling ADC with no missing codes, an
internal conversion clock, and a versatile serial interface port.
The part also contains a low noise, wide bandwidth, short
aperture delay track-and-hold circuit. On the CNV rising edge,
it samples an analog input IN+ between 0 V to REF with respect
to a ground sense IN−. The reference voltage, REF, is applied
externally and can be set up to the supply voltage.

Its power scales linearly with throughput.

The SPI compatible serial interface also features the ability,
using the SDI input, to daisy chain several ADCs on a single 3­wire bus and provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate
supply VIO.

The AD7946 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.

1.8 TO VDD

3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)

Rev Pr D

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD7946 Preliminary Technical Data

TABLE OF CONTENTS

Specifications..................................................................................... 3

Converter Operation.................................................................. 12

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Terminology ...................................................................................... 8

Typical Performance Characteristics ............................................. 9

Circuit Information.................................................................... 12

REVISION HISTORY

5/04—Revision D: Preliminary

Typical Connection Diagram ................................................... 13

Digital Interface.......................................................................... 17

Application Hints ........................................................................... 24

Layout .......................................................................................... 24

Evaluating the AD7946’s Performance.................................... 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 26

Rev Pr D | Page 2 of 27

Preliminary Technical Data AD7946

SPECIFICATIONS

VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 2.

Parameter Conditions Min Typ Max Unit

RESOLUTION 14 Bits
ANALOG INPUT

Voltage Range IN+ − IN− 0 V
Absolute Input Voltage IN+ −0.1 VDD + 0.1 V
IN− −0.1 0.1 V
Analog Input CMRR fIN = 250 kHz 65 dB
Leakage Current at 25°C Acquisition Phase 1 nA
Input Impedance

ACCURACY

No Missing Codes 14 Bits
Differential Linearity Error −0.7 ±0.25 +0.7 LSB1
Integral Linearity Error −1 ±0.4 +1 LSB
Transition Noise REF = VDD = 5 V 0.33 LSB
Gain Error2, T

MIN

to T

±TBD ±TBD LSB

MAX

Gain Error Temperature Drift ±TBD ppm/°C
Offset Error2, T

MIN

to T

±TBD ±TBD mV

MAX

Offset Temperature Drift ±TBD ppm/°C
Power Supply Sensitivity

VDD = 5V ± 5%

THROUGHPUT

Conversion Rate 0 500 kSPS
Transient Response Full-Scale Step 400 ns

AC ACCURACY

Signal-to-Noise fIN = 20 kHz, V
Spurious-Free Dynamic Range fIN = 20 kHz −100 dB
Total Harmonic Distortion fIN = 20 kHz −100 dB
Signal-to-(Noise + Distortion) fIN = 20 kHz, V

f

IN

Input

Intermodulation Distortion4 TBD dB

= VDD, TA = –40°C to +85°C, unless otherwise noted.

REF

±TBD LSB

= 5 V 83 85 dB3

REF

= 5 V 83 85 dB

REF

= 20 kHz, V

= 5 V, −60 dB

REF

25 dB

V

REF

1

LSB means least significant bit. With the 5 V input range, one LSB is 305.2 µV.

2

See Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.

3

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

4

f

= 21.4 kHz, f

IN1

= 18.9 kHz, each tone at −7 dB below full-scale.

IN2

Rev Pr D | Page 3 of 27

AD7946 Preliminary Technical Data

VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 3.

Parameter Conditions Min Typ Max Unit

REFERENCE

Voltage Range 0.5 VDD + 0.3 V

Load Current 500 kSPS, REF = 5 V TBD µA
SAMPLING DYNAMICS

−3 dB Input Bandwidth 9 MHz

Aperture Delay VDD = 5 V 2.5 ns
DIGITAL INPUTS

Logic Levels

VIL –0.3 0.3 × VIO V
VIH 0.7 × VIO VIO + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA

DIGITAL OUTPUTS

Data Format Serial 14 Bits Straight Binary

Pipeline Delay

VOL I
VOH I

= +500 µA 0.4 V

SINK

= −500 µA VIO − 0.3 V

SOURCE

POWER SUPPLIES

VDD Specified Performance 4.5 5.5 V

VIO Specified Performance 2.3 VDD + 0.3 V

VIO Range 1.8 VDD + 0.3 V

Standby Current

1, 2

VDD and VIO = 5 V, 25°C 1 50 nA

Power Dissipation VDD = 5 V, 100 SPS Throughput 3.3 µW
VDD = 5 V, 100 kSPS Throughput 3.3 5 mW
VDD = 5 V, 500 kSPS Throughput 25 mW
TEMPERATURE RANGE3

Specified Performance T

MIN

to T

= VDD, TA = –40°C to +85°C, unless otherwise noted.

REF

Conversion Results Available Immediately
after Completed Conversion

−40 +85 °C

MAX

1

With all digital inputs forced to VIO or GND as required.

2

During acquisition phase.

3

Contact Analog Devices for extended temperature range.

Rev Pr D | Page 4 of 27

Preliminary Technical Data AD7946

TIMING SPECIFICATIONS

−40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.

Table 4.

Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time between Conversions t

CNV Pulse Width ( CS Mode )
SCK Period ( CS Mode )

SCK Period ( Chain Mode ) t

SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t

CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)

SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
SDI High to SDO High (Chain Mode with BUSY indicator) t
VIO above 4.5 V 15 ns
VIO above 2.3 V 26 ns

1

0.5 1.6 µs

CONV

400 ns

ACQ

2 µs

CYC

10 ns

t

CNVH

t

15 ns

SCK

SCK

VIO above 4.5 V 19 ns
VIO above 3 V 20 ns
VIO above 2.7 V 21 ns
VIO above 2.3 V 22 ns

7 ns

SCKL

7 ns

SCKH

5 ns

HSDO

DSDO

VIO above 4.5 V 14 ns
VIO above 3 V 15 ns
VIO above 2.7 V 16 ns
VIO above 2.3 V 17 ns

tEN

VIO above 4.5 V 15 ns
VIO above 2.7 V 18 ns
VIO above 2.3 V 22 ns

t

25 ns

DIS

t

15 ns

SSDICNV

t

0 ns

HSDICNV

5 ns

SSCKCNV

5 ns

HSCKCNV

5 ns

SSDISCK

4 ns

HSDISCK

DSDOSDI

1

See Figure 2 and Figure 3 for load conditions.

Rev Pr D | Page 5 of 27

AD7946 Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs
IN+1, IN−1, REF

GND − 0.3 V to VDD + 0.3 V

or ±130 mA
Supply Voltages
VDD, VIO to GND −0.3 V to +7 V
VDD to VIO ±7 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 200°C/W (MSOP-10)
θJC Thermal Impedance 44°C/W (MSOP-10)
Lead Temperature Range

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

1

See the Analog Input section.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

500µAI

TO SDO

Figure 2. Load Circuit for Digital Interface Timing

50pF

C

L

500µAI

30% VIO

t

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

NOTES

1. 2V IF VIO ABOVE 2.5V, VIO– 0.5V IF VIO BELOW 2.5V.

2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.

Figure 3. Voltage Reference Levels for Timing

OL

1.4V

OH

70% VIO

1

2

02968-PrH-002

t

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

1

2

02968-PrH-003

Rev Pr D | Page 6 of 27

Preliminary Technical Data AD7946

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

REF

2

VDD

3

IN+

AD7946

4

IN–

5

GND

Figure 4.10-Lead MSOP and QFN (LFCSP) Pin Configuration

10

VIO

9

SDI

8

SCK

7

SDO

6

CNV

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1 Function

1 REF AI

Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should

be decoupled closely to the pin with a 10 µF capacitor.
2 VDD P Power Supply.
3 IN+ AI

Analog Input. It is referred to in IN−. The voltage range, i.e., the difference between IN+ and IN−, is 0 V to

.

V

REF

4 IN− AI Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground.
5 GND P Power Supply Ground.
6 CNV DI

Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and

CS

selects the interface mode of the part, chain or

mode. In CS mode, it enables the SDO pin when low. In

chain mode, the data should be read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:

Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to

daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on

SDI is output on SDO with a delay of 14 SCK cycles.

CS

mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY
indicator feature is enabled.

10 VIO P

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,
or 5 V).

1

AI = Analog Input, DI = Digital Input, DO = Digital Output, and P = Power

Rev Pr D | Page 7 of 27

AD7946 Preliminary Technical Data

[

(

)

−+=

TERMINOLOGY

Integral Nonlinearity Error (INL)

Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line
(Figure 21).

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.

Offset Error

The first transition should occur at a level 1/2 LSB above analog
ground (152.6 µV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.

Gain Error

The last transition (from 111 . . . 10 to 111 . . . 11) should occur
for an analog voltage 1 1/2 LSB below the nominal full scale
(4.999542 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the ideal
level after the offset has been adjusted out.

Spurious-Free Dynamic Range (SFDR)

The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula

]

DNSENOB

dB

and is expressed in bits.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.

Signal-to-(Noise + Distortion) Ratio (S/[N+D])

S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in dB.

Aperture Delay

Aperture delay is a measure of the acquisition performance and
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.

Transi e nt Resp o n s e

The time required for the ADC to accurately acquire its input
after a full-scale step function was applied.

)02.6/76.1/

Rev Pr D | Page 8 of 27

Preliminary Technical Data AD7946

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. Integral Nonlinearity vs. Code

Figure 6. Histogram of a DC Input at the Code Center

Figure 8. Differential Nonlinearity vs. Code

Figure 9. Histogram of a DC Input at the Code Center

Figure 7. FFT Plot

Rev Pr D | Page 9 of 27

Figure 10. S/[N + D] vs. Freq uency