Analog Devices AD7942 Datasheet
14-Bit, 250 kSPS PulSAR
Pseudo Differential ADC in MSOP/QFN
FEATURES
14-bit resolution with no missing codes
Throughput: 250 kSPS
INL: ±0.4 LSB typ, ±1 LSB max (±0.0061% of FSR)
SINAD: 85 dB @ 20 kHz
THD: −100 dB @ 20 kHz
Pseudo differential analog input range
0 V to V
with V
REF
No pipeline delay
Single-supply 2.3 V to 5.5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI®-/QSPI
DSP-compatible
Daisy-chaining for multiple ADCs and busy indicator
Power dissipation
1.25 mW @ 2.5 V/100 kSPS, 3.6 mW @ 5 V/100 kSPS
1.25 µW @ 2.5 V/100 SPS
Standby current: 1 nA
10-lead package: MSOP (MSOP-8 size) and
3 mm × 3 mm QFN
Pin-for-pin compatible with the 16-bit AD7685
APPLICATIONS
Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process control
GENERAL DESCRIPTION
The AD7942 is a 14-bit, charge redistribution, successive appro-
ximation PulSAR
supply, VDD, between 2.3 V to 5.5 V. It contains a low power,
high speed, 14-bit sampling ADC with no missing codes, an
internal conversion clock, and a versatile serial interface port.
The part also contains a low noise, wide bandwidth, short
aperture delay track-and-hold circuit. On the CNV rising edge,
it samples an analog input IN+ between 0 V to V
to a ground sense IN−. The reference voltage, V
externally and can be set up to be the supply voltage. Its power
scales linearly with the throughput.
up to VDD
REF
™-/MICROWIRE™-/
1
(LFCSP) (SOT-23 size)
® ADC that operates from a single power
with respect
REF
, is applied
REF
AD7942
APPLICATION DIAGRAM
0.5V TO 5V 2.5V TO 5V
0 TO V
REF
IN+
IN–
REF
AD7942
GND
VDD
VIO
SDI
SCK
SDO
CNV
Figure 1.
Table 1. MSOP, QFN1 (LFCSP)/SOT-23, 14 and 16-Bit ADCs
Type 100 kSPS 250 kSPS 500 kSPS
16-Bit True
AD7684 AD7687 AD7688
Differential
16-Bit Pseudo
AD7683
Differential/Unipolar
16-Bit Unipolar AD7680
14-Bit Pseudo
Differential/Unipolar
14-Bit Unipolar AD7940
1
QFN package in development. Contact sales for samples and availability.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single
3-wire bus and provides an optional busy indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate
supply VIO.
The AD7942 is housed in a 10-lead MSOP or a 10-lead
1
(LFCSP) package with operation specified from −40°C
QFN
to +85°C.
1.8V TO VDD
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
AD7685
AD7694
AD7942
AD7686
AD7946
04657-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
www.analog.com
AD7942
TABLE OF CONTENTS
Specifications..................................................................................... 3
Converter Operation.................................................................. 13
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Te r m in o l o g y ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Circuit Information.................................................................... 13
REVISION HISTORY
3/05—Revision 0: Initial Version
Typical C o n n e ction D i a g r am ................................................... 14
Digital Interface.......................................................................... 16
Application Hints ........................................................................... 23
Layout .......................................................................................... 23
Evaluating the AD7942’s Performance.................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Rev. 0 | Page 2 of 24
AD7942
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V
Table 2.
Parameter Conditions Min Typ Max Unit
RESOLUTION 14 Bits
ANALOG INPUT
Voltage Range IN+ − IN− 0 V
Absolute Input Voltage IN+ −0.1 VDD + 0.1 V
IN− −0.1 0.1 V
Analog Input CMRR fIN = 250 kHz 65 dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance See the Analog Input section
ACCURACY
No Missing Codes 14 Bits
Differential Linearity Error −0.7 ±0.3 +0.7 LSB
Integral Linearity Error −1 ±0.4 +1 LSB
Transition Noise V
Gain Error2, T
MIN
to T
MAX
±0.7 ±6 LSB
Gain Error Temperature Drift ±1 ppm/°C
Offset Error2, T
MIN
to T
MAX
VDD = 4.5 V to 5.5 V ±0.45 ±3 mV
VDD = 2.3 V to 4.5 V ±0.75 ±4.5 mV
Offset Temperature Drift ±2.5 ppm/°C
Power Supply Sensitivity
VDD = 5 V ± 5%
THROUGHPUT
Conversion Rate VDD = 4.5 V to 5.5 V 0 250 kSPS
VDD = 2.3 V to 4.5 V 0 200 kSPS
Transient Response Full-scale step 1.8 µs
AC ACCURACY
Signal-to-Noise fIN = 20 kHz, V
f
Spurious-Free Dynamic Range fIN = 20 kHz −100 dB
Total Harmonic Distortion fIN = 20 kHz −100 dB
Signal-to-Noise and Distortion fIN = 20 kHz, V
(SINAD)
f
−60 dB input
f
1
LSB means least significant bit. With a 5 V input range, one LSB is 305.2 µV.
2
See the section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. Terminology
3
All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
= VDD, TA = –40°C to +85°C, unless otherwise noted.
REF
REF
= VDD = 5 V 0.33 LSB
REF
±0.1 LSB
= 5 V 84.5 85 dB
REF
= 20 kHz, V
IN
= 20 kHz, V
IN
= 20 kHz, V
IN
= 2.5 V 84 dB
REF
= 5 V 83 85 dB
REF
= 5 V,
REF
= 2.5 V 84 dB
REF
25 dB
V
1
3
Rev. 0 | Page 3 of 24
AD7942
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V
Table 3.
Parameter Conditions Min Typ Max Unit
REFERENCE
Voltage Range 0.5 VDD + 0.3 V
Load Current 250 kSPS, V
SAMPLING DYNAMICS
−3 dB Input Bandwidth 2 MHz
Aperture Delay VDD = 5 V 2.5 ns
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
–0.3 0.3 × VIO V
0.7 × VIO VIO + 0.3 V
−1 +1 µA
−1 +1 µA
DIGITAL OUTPUTS
Data Format Serial 14 bits straight binary
Pipeline Delay
V
OL
V
OH
I
= +500 µA 0.4 V
SINK
I
= −500 µA VIO − 0.3 V
SOURCE
POWER SUPPLIES
VDD Specified performance 2.3 5.5 V
VIO Specified performance 2.3 VDD + 0.3 V
VIO Range 1.8 VDD + 0.3 V
Standby Current
1, 2
VDD and VIO = 5 V, @ 25°C 1 50 nA
Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.25 µW
VDD = 2.5 V, 100 kSPS throughput 1.25 2 mW
VDD = 2.5 V, 200 kSPS throughput 2.5 4 mW
VDD = 5 V, 100 kSPS throughput 3.6 5 mW
VDD = 5 V, 250 kSPS throughput 12.5 mW
TEMPERATURE RANGE
Specified Performance T
3
to T
MIN
1
With all digital inputs forced to VIO or GND as required.
2
During acquisition phase.
3
Contact Analog Devices for extended temperature range.
= VDD, TA = –40°C to +85°C, unless otherwise noted.
REF
= 5 V 50 µA
REF
Conversion results available immediately
after completed conversion
MAX
−40 +85 °C
Rev. 0 | Page 4 of 24
AD7942
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V1, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated, TA = −40°C to +85°C.
Table 4.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time Between Conversions t
CNV Pulse Width ( CS Mode)
SCK Period ( CS Mode)
SCK Period ( Chain Mode) t
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data-Valid Delay t
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
SDI High to SDO High (Chain Mode with Busy Indicator) t
1
0.5 2.2 µs
1.8 µs
4 µs
10 ns
15 ns
t
t
CONV
ACQ
CYC
CNVH
SCK
SCK
VIO above 4.5 V 17 ns
VIO above 3 V 18 ns
VIO above 2.7 V 19 ns
VIO above 2.3 V 20 ns
SCKL
SCKH
HSDO
DSDO
7 ns
7 ns
5 ns
VIO above 4.5 V 14 ns
VIO above 3 V 15 ns
VIO above 2.7 V 16 ns
VIO above 2.3 V 17 ns
t
EN
VIO above 4.5 V 15 ns
VIO above 2.7 V 18 ns
VIO above 2.3 V 22 ns
25 ns
15 ns
0 ns
5 ns
5 ns
3 ns
4 ns
CS Mode)
(
t
DIS
t
SSDICNV
t
HSDICNV
SSCKCNV
HSCKCNV
SSDISCK
HSDISCK
DSDOSDI
VIO above 4.5 V 15 ns
VIO above 2.3 V 26 ns
See and for load conditions. Figure 2 Figure 3
Rev. 0 | Page 5 of 24
AD7942
VDD = 2.3 V to 4.5 V1, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated, TA = −40°C to +85°C.
Table 5.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time Between Conversions t
CNV Pulse Width ( CS Mode)
SCK Period ( CS Mode)
SCK Period ( Chain Mode) t
t
t
CONV
ACQ
CYC
CNVH
SCK
SCK
VIO Above 3 V 29 ns
VIO Above 2.7 V 35 ns
VIO Above 2.3 V 40 ns
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t
SCKL
SCKH
HSDO
DSDO
VIO Above 3 V 24 ns
VIO Above 2.7 V 30 ns
VIO Above 2.3 V 35 ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
t
EN
VIO Above 2.7 V 18 ns
VIO Above 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
SDI High to SDO High (Chain Mode with Busy Indicator) t
t
DIS
t
SSDICNV
t
HSDICNV
SSCKCNV
HSCKCNV
SSDISCK
HSDISCK
DSDOSDI
1
See and for load conditions. Figure 2 Figure 3
0.7 3.2 µs
1.8 µs
5 µs
10 ns
25 ns
12 ns
12 ns
5 ns
25 ns
30 ns
0 ns
5 ns
8 ns
5 ns
4 ns
36 ns
Rev. 0 | Page 6 of 24
AD7942
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Analog Inputs
IN+1, IN−1
GND − 0.3 V to VDD + 0.3 V
or ±130 mA
REF GND − 0.3 V to VDD + 0.3 V
Supply Voltages
VDD, VIO to GND −0.3 V to +7 V
VDD to VIO ±7 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 200°C/W (MSOP-10)
θJC Thermal Impedance 44°C/W (MSOP-10)
Lead Temperature Range
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1
See the Analog Input section.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
500µAI
TO SDO
50pF
C
L
500µAI
Figure 2. Load Circuit for Digital Interface Timing
30% VIO
t
DELAY
2V OR VIO – 0.5V
0.8V OR 0.5V
NOTES
1
2V IF VIO ABOVE 2.5V, VIO– 0.5V IF VIO BELOW 2.5V.
2
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 3. Voltage Reference Levels for Timing
OL
1.4V
OH
70% VIO
1
2
04657-002
t
DELAY
2V OR VIO – 0.5V
0.8V OR 0.5V
1
2
04657-003
Rev. 0 | Page 7 of 24
AD7942
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
REF
2
VDD
IN+
3
AD7942
IN–
4
GND
5
Figure 4.10-Lead MSOP and QFN
10
VIO
9
SDI
SCK
8
SDO
7
CNV
6
1
(LFCSP) Pin Configuration
04657-004
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type2Function
1 REF AI
Reference Input Voltage. The V
range is from 0.5 V to VDD. It is referred to the GND pin. This pin should
REF
be decoupled closely to the pin with a 10 µF capacitor.
2 VDD P Power Supply.
3 IN+ AI
Analog Input. It is referred to IN−. The voltage range, i.e., the difference between IN+ and IN−, is 0 V
to V
.
REF
4 IN− AI Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground.
5 GND P Power Supply Ground.
6 CNV DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode of the part, chain or
CS mode. In CS mode, it enables the SDO pin when low. In
chain mode, the data should be read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9 SDI DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 14 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the busy
indicator feature is enabled.
10 VIO P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,
or 5 V).
1
QFN package in development. Contact sales for samples and availability.
2
AI = Analog Input, DI = Digital Input, DO = Digital Output, and P = Power.
Rev. 0 | Page 8 of 24
Loading...