Analog Devices AD7938 9 Datasheet

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8-Channel, 1.5 MSPS, 12-Bit and 10-Bit

FEATURES

Fast throughput rate: 1.5 MSPS Specified for V Low power

6 mW max at 1.5 MSPS with 3 V supplies

13.5 mW max at 1.5 MSPS with 5 V supplies 8 analog input channels with a sequencer Software configurable analog inputs

8-channel single-ended inputs 4-channel fully differential inputs 4-channel pseudo-differential inputs

7-channel pseudo-differential inputs Accurate on-chip 2.5 V reference ±0.2% max @ 25°C, 25 ppm/°C max 70 dB SINAD at 50 kHz input frequency No pipeline delays High speed parallel interface—word/byte modes Full shutdown mode: 2 µA max 32-lead LFCSP and TQFP package

GENERAL DESCRIPTION

The AD7938/AD7939 are 12-bit and 10-bit, high speed, low power, successive approximation (SAR) ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1.5 MSPS. The parts contain a low noise, wide bandwidth, differential track-and-hold amplifier that can handle input frequencies up to 50 MHz.

The AD7938/AD7939 feature eight analog input channels with a channel sequencer that allow a preprogrammed selection of channels to be converted sequentially. These parts can operate with either single-ended, fully differential, or pseudodifferential analog inputs.

The conversion process and data acquisition are controlled using standard control inputs that allow easy interfacing with microprocessors and DSPs. The input signal is sampled on the falling edge of

this point.

The AD7938/AD7939 have an accurate on-chip 2.5 V reference that can be used as the reference source for the analog-to-digital conversion. Alternatively, this pin can be overdriven to provide an external reference.

of 2.7 V to 5.25 V

CONVST

and the conversion is also initiated at

Parallel ADCs with a Sequencer

AD7938/AD7939

FUNCTIONAL BLOCK DIAGRAM

AGND

REFIN/

REFOUT

VIN0

VIN7

SEQUENCER

PARALLEL INTERFACE/CONTROL REGISTER

DB0 DB11

I/P

MUX

2.5V

VREF

T/H

Figure 1.

These parts use advanced design techniques to achieve very low power dissipation at high throughput rates. They also feature flexible power management options. An on-chip control register allows the user to set up different operating conditions, including analog input range and configuration, output coding, power management, and channel sequencing.

PRODUCT HIGHLIGHTS

1. High throughput with low power consumption.

2. Eight analog inputs with a channel sequencer.

3. Accurate on-chip 2.5 V reference.

4. Software configurable analog inputs. Single-ended, pseudo-

differential, or fully differential analog inputs that are software selectable.

5. Single-supply operation with V

function allows the parallel interface to connect directly to 3 V, or 5 V processor systems independent of V

6. No pipeline delay.

7. Accurate control of the sampling instant via a

input and once off conversion control.

AD7938/AD7939

12-/10-BIT SAR ADC

AND

CONTROL

CS DGNDRD WR W/B

function. The V

DRIVE

CLKIN CONVST BUSY

DRIVE

CONVST

03715-0-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

AD7938/AD7939

AD7938—Specifications.................................................................. 3

Typical C o n nect i o n D iagram ................................................... 18

AD7939—Specifications.................................................................. 5

Timing Specifications....................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Description .............................. 9

Te r m in o l o g y .................................................................................... 11

Typical Performance Characteristics........................................... 13

On-Chip Registers.......................................................................... 15

Control Register.......................................................................... 15

Sequencer Operation .................................................................16

Shadow Register.......................................................................... 16

Circuit Information........................................................................ 17

Converter Operation.................................................................. 17

ADC Transfer Function............................................................. 17

Analog Input Structure.............................................................. 18

Analog Inputs.............................................................................. 19

Analog Input Selection.............................................................. 21

Reference Section ....................................................................... 22

Parallel Interface ......................................................................... 24

Power Modes of Operation ....................................................... 27

Power vs. Throughput Rate ....................................................... 28

Microprocessor Interfacing....................................................... 28

Application Hints ........................................................................... 30

Grounding and Layout .............................................................. 30

PCB Design Guidelines for Chip Scale Package .................... 30

Evaluating the AD7938/AD7939 Performance...................... 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 32

REVISION HISTORY

10/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD7938/AD7939

AD7938—SPECIFICATIONS

VDD = V T

MAX

Table 1.

Parameter B Version

DYNAMIC PERFORMANCE FIN = 50 kHz sine wave

Signal-to-Noise + Distortion (SINAD) 68 dB min Single-ended mode Signal-to-Noise Ratio (SNR)2 71 dB min Differential mode 69 dB min Single-ended mode Total Harmonic Distortion (THD)2 −73 dB max −85 dB typ, differential mode

−70 dB max −80 dB typ, single-ended mode Peak Harmonic or Spurious Noise (SFDR)2 −73 dB max −82 dB typ Intermodulation Distortion (IMD)2 fa = 30 kHz, fb = 50 kHz

Channel-to-Channel Isolation −85 dB typ FIN = 50 kHz, F Aperture Delay2 5 ns typ Aperture Jitter2 72 ps typ

Full Power Bandwidth2 50 MHz typ @ 3 dB 10 MHz typ @ 0.1 dB DC ACCURACY

Resolution 12 Bits

Integral Nonlinearity2 ±1 LSB max Differential mode

±1.5 LSB max Single-ended mode

Differential Nonlinearity2

Single-Ended and Pseudo-Differential Input Straight binary output coding

Fully Differential Input Twos complement output coding

ANALOG INPUT

Single-Ended Input Range 0 to V

Pseudo-Differential Input Range: V

Fully Differential Input Range: V

DC Leakage Current

Input Capacitance 45 pF typ When in track

10 pF typ When in hold

= 2.7 V to 5.25 V, internal/external V

DRIVE

= 2.5 V, unless otherwise noted, F

REF

= 25.5 MHz, F

CLKIN

= 1.5 MSPS; TA = T

SAMPLE

, unless otherwise noted.

70 dB min Differential mode

Unit Test Conditions/Comments

Second-Order Terms −86 dB typ Third-Order Terms −90 dB typ

= 300 kHz

NOISE

Differential Mode ±0.95 LSB max Guaranteed no missed codes to 12 bits Single-Ended Mode −0.95/+1.5 LSB max Guaranteed no missed codes to 12 bits

Offset Error2 ±6 LSB max Offset Error Match2 ±1 LSB max Gain Error2 ±3 LSB max Gain Error Match2 ±1 LSB max

Positive Gain Error3 ±3 LSB max Positive Gain Error Match2 ±1 LSB max Zero-Code Error2 ±6 LSB max Zero-Code Error Match2 ±1 LSB max Negative Gain Error2 ±3 LSB max Negative Gain Error Match2 ±1 LSB max

or 0 to 2 × V

REF

0 to V

IN+

IN−

or 2 × V

REF

−0.3 to +0.7 V typ VDD = 3 V

V RANGE bit = 0, or RANGE bit =1, respectively

REF

V RANGE bit = 0, or RANGE bit =1, respectively

−0.3 to +1.8 V typ VDD = 5 V and V

IN+

and V

IN+

IN−

VCM ± V VCM ± V

/2 V VCM = common-mode voltage3 = V

REF

V VCM = V

±1 µA max

REF

, V

IN+

or V

must remain within GND/V

IN−

REF

MIN

Rev. 0 | Page 3 of 32

AD7938/AD7939

Parameter B Version

Unit Test Conditions/Comments

REFERENCE INPUT/OUTPUT

Input Voltage

REF

2.5 V ±1% for specified performance DC Leakage Current ±1 µA max V

Input Impedance 10 kΩ typ

REF

Output Voltage 2.5 V ±0.2% max @ 25°C

REFOUT

Temperature Coefficient 25 ppm/°C max 5 ppm/°C typ

REFOUT

Noise 10 µV typ 0.1 Hz to 10 Hz bandwidth

REF

130 µV typ 0.1 Hz to 1 MHz bandwidth V

Output Impedance 10 Ω typ

REF

Input Capacitance 15 pF typ When in track

REF

25 pF typ When in hold

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

INH

INL

2.4 V min

0.8 V max Input Current, IIN ±5 µA max Typically 10 nA, VIN = 0 V or V Input Capacitance, C

10 pF max

LOGIC OUTPUTS

Output High Voltage, V

Output Low Voltage, VOL 0.4 V max I

2.4 V min I

SOURCE

= 200 µA

SINK

= 200 µA

Floating-State Leakage Current ±3 µA max Floating-State Output Capacitance4 10 pF max Output Coding CODING bit = 0

Straight (Natural) Binary

Twos Complement

CODING bit = 1

CONVERSION RATE

Conversion Time t2 + 13 t

CLK

ns Track-and-Hold Acquisition Time 125 ns max Full-scale step input Throughput Rate 1.5 MSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 V min/max V

2.7/5.25 V min/max

DRIVE

Digital I/PS = 0 V or V

DRIVE

Normal Mode (Static) 0.8 mA typ VDD = 2.7 V to 5.25 V, SCLK on or off Normal Mode (Operational) 2.7 mA max VDD = 4.75 V to 5.25 V

2.0 mA max VDD = 2.7 V to 3.6 V

Autostandby Mode 0.3 mA typ F

= 100 kSPS, VDD = 5 V

SAMPLE

160 µA typ (Static) Full/Autoshutdown Mode (Static) 2 µA max SCLK on or off

Power Dissipation

Normal Mode (Operational) 13.5 mW max VDD = 5 V 6 mW max VDD = 3 V Autostandby Mode (Static) 800 µW typ VDD = 5 V 480 µW typ VDD = 3 V Full/Autoshutdown Mode (Static) 10/6 µW max VDD = 5 V/3 V

Temperature ranges as follows: B Versions: −40°C to +85°C.

See the Terminology section.

For full common-mode range, see Fi and . gure 25 Figure 26

Sample tested during initial release to ensure compliance.

This device is operational with an external reference in the range 0.1 V to VDD. See the Reference Section for more information.

Measured with a midscale dc analog input.

DRIVE

Rev. 0 | Page 4 of 32

AD7938/AD7939

AD7939—SPECIFICATIONS

VDD = V T

MAX

Table 2.

Parameter B Version

DYNAMIC PERFORMANCE FIN = 50 kHz sine wave

Signal-to-Noise + Distortion (SINAD) 60 dB min Single-ended mode Total Harmonic Distortion (THD)2 −70 dB max Peak Harmonic or Spurious Noise (SFDR)2 −72 dB max Intermodulation Distortion (IMD)2 fa = 30 kHz, fb = 50 kHz

Channel-to-Channel Isolation −75 dB typ FIN = 50 kHz, F Aperture Delay2 5 ns typ Aperture Jitter2 72 ps typ

Full Power Bandwidth2 50 MHz typ @ 3 dB 10 MHz typ @ 0.1 dB DC ACCURACY

Resolution 10 Bits

Integral Nonlinearity2 ±0.5 LSB max

Differential Nonlinearity2 ±0.5 LSB max Guaranteed no missed codes to 10 bits

Single-Ended and Pseudo-Differential Input Straight binary output coding

Fully Differential Input Twos complement output coding

ANALOG INPUT

Single-Ended Input Range 0 to V

Pseudo-Differential Input Range: V

Fully Differential Input Range: V

DC Leakage Current

Input Capacitance 45 pF typ When in track

10 pF typ When in hold REFERENCE INPUT/OUTPUT

REF

DC Leakage Current4 ±1 µA max

REFOUT

REF

130 µV typ 0.1 Hz to 1 MHz bandwidth

REF

= 2.7 V to 5.25 V, internal/external V

DRIVE

= 2.5V, unless otherwise noted, F

REF

= 25.5 MHz, F

CLKIN

= 1.5 MSPS; TA = T

SAMPLE

, unless otherwise noted.

61 dB min Differential mode

Unit Test Conditions/Comments

Second-Order Terms −86 dB typ Third-Order Terms −90 dB typ

= 300 kHz

NOISE

Offset Error2 ±2 LSB max Offset Error Match2 ±0.5 LSB max Gain Error2 ±1.5 LSB max Gain Error Match2 ±0.5 LSB max

Positive Gain Error2 ±1.5 LSB max Positive Gain Error Match2 ±0.5 LSB max Zero-Code Error2 ±2 LSB max Zero-Code Error Match2 ±0.5 LSB max Negative Gain Error2 ±1.5 LSB max Negative Gain Error Match2 ±0.5 LSB max

or 0 to 2 × V

REF

0 to V

IN+

IN−

or 2 × V

REF

−0.3 to +0.7 V typ VDD = 3 V

V RANGE bit = 0, or RANGE bit =1, respectively

REF

V RANGE bit = 0, or RANGE bit =1, respectively

−0.3 to +1.8 V typ VDD = 5 V

Input Voltage

and V

IN+

and V

IN+

IN−

VCM ± V VCM ± V

/2 V VCM = common-mode voltage3 = V

REF

V VCM = V

REF

, V

or V

IN+

±1 µA max

2.5 V ±1% for specified performance

must remain within GND/V

IN−

Output Voltage 2.5 V ±0.2% max @ 25°C Temperature Coefficient 40 ppm/°C typ

Noise 10 µV typ 0.1 Hz to 10 Hz bandwidth

Output Impedance 10 Ω typ

REF

MIN

Rev. 0 | Page 5 of 32

AD7938/AD7939

Parameter B Version

Input Capacitance 15 pF typ When in track

REF

Unit Test Conditions/Comments

25 pF typ When in hold

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

INH

INL

2.4 V min

0.8 V max Input Current, IIN ±5 µA max Typically 10 nA, VIN = 0 V or V Input Capacitance, C

10 pF max

LOGIC OUTPUTS

Output High Voltage, V

Output Low Voltage, VOL 0.4 V max I

2.4 V min I

= 200 µA

SOURCE

= 200 µA

SINK

Floating-State Leakage Current ±3 µA max Floating-State Output Capacitance4 10 pF max Output Coding CODING bit = 0

Straight (Natural) Binary

Twos Complement

CODING bit =1

CONVERSION RATE

Conversion Time t2 + 13 t

CLK

Track-and-Hold Acquisition Time 125 ns max Full-scale step input Throughput Rate 1.5 MSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 V min/max V

2.7/5.25 V min/max

DRIVE

Digital I/PS = 0 V or V

DRIVE

Normal Mode (Static) 0.8 mA typ VDD = 2.7 V to 5.25 V, SCLK on or off Normal Mode (Operational) 2.7 mA max VDD = 4.75 V to 5.25 V

2.0 mA max VDD = 2.7 V to 3.6 V Autostandby Mode 0.3 mA typ F

= 100 kSPS, VDD = 5 V

SAMPLE

160 µA typ (Static) Full/Autoshutdown Mode (Static) 2 µA max SCLK on or off

Power Dissipation

Normal Mode (Operational) 13.5 mW max VDD = 5 V 6 mW max VDD = 3 V Autostandby Mode (Static) 800 µW typ VDD = 5 V 480 µW typ VDD = 3 V Full/Autoshutdown Mode (Static) 10/6 µW max VDD = 5 V/3 V

Temperature ranges as follows: B Versions: −40°C to +85°C.

See the Terminology section.

For full common-mode range see Fig and . ure 25 Figure 26

Sample tested during initial release to ensure compliance.

This device is operational with an external reference in the range 0.1 V to VDD. See the Reference Section for more details.

Measured with a midscale dc analog input.

DRIVE

Rev. 0 | Page 6 of 32

AD7938/AD7939

TIMING SPECIFICATIONS

VDD = V T

MAX

Table 3.

Limit at T Parameter AD7938 AD7939 Unit Description

CLKIN

25.5 25.5 MHz max t

QUIET

50 50 ns max t

Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. All timing specifications given above are with a 25 pF load capacitance (see , Figure 36, Figure 37, and ).

The time required for the output to cross 0.4 V or 2.4 V.

t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or

discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.

= 2.7 V to 5.25 V, internal/external V

DRIVE

, unless otherwise noted.

, T

MIN

50 50 kHz min

30 30 ns min

10 10 ns min 15 15 ns min 50 50 ns min CLKIN Falling Edge to BUSY Rising Edge.

0 0 ns min 0 0 ns min 10 10 ns min 10 10 ns min 10 10 ns min 10 10 ns min New Data Valid before Falling Edge of BUSY. 0 0 ns min 0 0 ns min 30 30 ns min 30 30 ns max 3 3 ns min

0 0 ns min 0 0 ns min 10 10 ns min Minimum Time between Reads/Writes. 0 0 ns min 10 10 ns min 40 40 ns max CLKIN Falling Edge to BUSY Falling Edge.

15.7 15.7 ns min CLKIN Low Pulse Width.

7.8 7.8 ns min CLKIN High Pulse Width.

MAX

= 2.5 V, unless otherwise noted; F

REF

= 25.5 MHz, F

CLKIN

= 1.5 MSPS; TA = T

SAMPLE

Minimum time between end of read and start of next conversion, i.e., time from when the data bus goes into three-state until the next falling edge of

CONVST. CONVST Pulse Width. CONVST Falling Edge to CLKIN Falling Edge Setup Time.

CS to WR Setup Time. CS to WR Hold Time. WR Pulse Width. Data Setup Time before Data Hold after

WR.

CS to RD Setup Time. CS to RD Hold Time. RD Pulse Width. Data Access Time after Bus Relinquish Time after Bus Relinquish Time after HBEN to HBEN to

HBEN to HBEN to

RD Setup Time. RD Hold Time.

WR Setup Time. WR Hold Time.

Figure 35 Figure 38

RD.

RD. RD.

MIN

Rev. 0 | Page 7 of 32

AD7938/AD7939

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to AGND/DGND −0.3 V to +7 V V

to AGND/DGND −0.3 V to VDD +0.3 V

DRIVE

Analog Input Voltage to AGND −0.3 V to VDD + 0.3 V Digital Input Voltage to DGND −0.3 V to +7 V V

to V

DRIVE

Digital Output Voltage to DGND −0.3 V to V V

to AGND −0.3 V to VDD + 0.3 V

REFIN

−0.3 V to VDD + 0.3 V + 0.3 V

DRIVE

AGND to DGND −0.3 V to + 0.3 V Input Current to Any

Pin Except Supplies

±10 mA

Operating Temperature Range

Commercial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 108.2°C/W (LFCSP) 121°C/W (TQFP) θJC Thermal Impedance 32.71°C/W (LFCSP) 45°C/W (TQFP) Lead Temperature, Soldering

Reflow Temperature

255°C

(10 sec to 30 sec)

ESD 1.5 kV

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 8 of 32

AD7938/AD7939

PIN CONFIGURATION AND FUNCTION DESCRIPTION

VIN1

VIN0

REFIN/VREFOUT

AGND

RD WR

CONVST

BUSY

CLKIN

03715-0-006

CS, RD, and WR. The logic high/low

input. When reading from the AD7939, the two LSBs

DRIVE

CS, RD, and WR.

input.

DRIVE

rising edge of SCLK, see Figure 35.

. The frequency of the master clock input therefore determines the

CONVST is used to power-up the

RD read while CS is low.

Table 5. Pin Function Description

Pin No Mnemonic Function

1 to 8 DB0 to DB7

Data Bits 0 to 7. Three-state parallel digital I/O pins that provide the conversion result and also allow the control and shadow registers to be programmed. These pins are controlled by voltage levels for these pins are determined by the V (DB0 and DB1) are always 0 and the LSB of the conversion result is available on DB2.

9 V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the AD7938/AD7939 operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at V

10 DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7938/AD7939. This pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

11 DB8/HBEN

Data Bit 8/High Byte Enable. When W/

CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte

by of data being written to or read from the AD7938/AD7939 is on DB0 to DB7. When HBEN is high, the top four

bits of the data being written to or read from the AD7938/AD7939 are on DB0 to DB3. When reading from the device, DB4 to DB6 of the high byte contains the ID of the channel to which the conversion result corresponds (see the channel address bits in Table 9). When writing to the device, DB4 to DB7 of the high byte must be all 0s. Note that when reading from the AD7939, the two LSBs of the low byte are 0s, and the remaining 6 bits, conversion data.

12 to 14 DB9 to DB11

Data Bits 9 to 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the control and shadow registers to be programmed in word mode. These pins are controlled by The logic high/low voltage levels for these pins are determined by the V

15 BUSY

Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the falling edge of the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just prior to the falling edge of BUSY on the 13

16 CLKIN

Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the AD7938/AD7939 takes 13 clock cycles + t conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock.

CONVST Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track

to hold mode on the falling edge of down, when operating in autoshutdown or autostandby modes, a rising edge on device.

18 19

WR Write Input. Active low logic input used in conjunction with CS to write data to the internal registers. RD Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion

result is placed on the data bus following the falling edge of

TOP VIEW

(Not to Scale)

DB9

DB1013DB11

DB8/HBEN

DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7

W/B32V

PIN 1

IDENTIFIER

AD7938/AD7939

DRIVE

DGND

Figure 2. Pin Configuration

but should never exceed VDD by more than 0.3 V.

B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled

CONVST and stays high for the duration of the conversion. Once the conversion is complete and

CONVST and the conversion process is initiated at this point. Following power-

Rev. 0 | Page 9 of 32

AD7938/AD7939

Pin No Mnemonic Function

21 AGND

22 V

23 to 30 VIN0 to VIN7

31 VDD

CS Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data

to the internal registers. Analog Ground. This is the ground reference point for all analog circuitry on the AD7938/AD7939. All analog

input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

REFIN/VREFOUT

Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC. The nominal internal reference voltage is 2.5 V and this appears at this pin. This pin can be overdriven by an external reference. The input voltage range for the external reference is 0.1 V to V taken to ensure that the analog input range does not exceed V

Analog Input 0 to Analog Input 7. Eight analog input channels that are multiplexed into the on-chip track-andhold. The analog inputs can be programmed to be eight single-ended inputs, four fully differential pairs, four pseudo-differential pairs, or seven pseudo-differential inputs by setting the MODE bits in the control register appropriately (see Table 9). The analog input channel to be converted can either be selected by writing to the address bits (ADD2 to ADD0) in the control register prior to the conversion or the on-chip sequencer can be used. The SEQ and SHDW bits in conjunction with the address bits in the control register allow the shadow register to be programmed. The input range for all input channels can either be 0 V to V the coding can be binary or twos complement, depending on the states of the RANGE and CODING bits in the control register. Any unused input channels should be connected to AGND to avoid noise pickup.

Power Supply Input. The V to AGND with a 0.1 µF capacitor and a 10 µF tantalum capacitor.

B Word/Byte Input. When this input is logic high, data is transferred to and from the AD7938/AD7939 in 12-bit/10-

bit words on Pins DB0/DB2 to DB11. When this pin is logic low, byte transfer mode is enabled. Data and the channel ID are transferred on Pins DB0 to DB7, and Pin DB8/HBEN assumes its HBEN functionality. Unused data lines when operating in byte transfer mode should be tied off to DGND.

; however, care must be

+ 0.3 V. See the Reference Section.

range for the AD7938/AD7939 is 2.7 V to 5.25 V. The supply should be decoupled

or 0 V to 2 × V

REF

, and

Rev. 0 | Page 10 of 32

AD7938/AD7939

TERMINOLOGY

Integral Nonlinearity

This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (00 . . .000) to (00 . . . 001) f rom the ideal, i.e., AGND + 1 LSB.

Offset Error Match

This is the difference in offset error between any two channels.

Gain Error

This is the deviation of the last code transition (111 . . .110) to (111 . . . 111) from the ideal (i.e., V

– 1 LSB) after the offset

REF

error has been adjusted out.

Gain Error Match

This is the difference in gain error between any two channels.

Zero-Code Error

This applies when using the twos complement output coding option, in particular to the 2 × V

biased about the V

REF

REFIN

input range with −V

REF

point. It is the deviation of the

mid scale transition (all 0s to all 1s) from the ideal V

REF

i.e., V

REF

voltage,

Zero-Code Error Match

This is the difference in zero-code error between any two channels.

Positive Gain Error

This applies when using the twos complement output coding option, in particular to the 2 × V

biased about the V

REF

point. It is the deviation of the last

REFIN

input range with −V

REF

code transition (011. . .110) to (011 .. . 111) from the ideal (i.e.,

− 1 LSB) after the zero-code error has been adjusted out.

REF

Positive Gain Error Match

This is the difference in positive gain error between any two channels.

Negative Gain Error

This applies when using the twos complement output coding option, in particular to the 2 × V

biased about the V

REF

point. It is the deviation of the first

REF

input range with −V

REF

code transition (100 . . . 000) to (100 . . . 001) from the ideal (i.e.,

+ 1 LSB) after the zero-code error has been adjusted

−V

REFIN

out.

Negative Gain Error Match

This is the difference in negative gain error between any two channels.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale sine wave signal to all seven nonselected input channels and applying a 50 kHz signal to the selected channel. The channel-to-channel isolation is defined as the ratio of the power of the 50 kHz signal on the selected channel to the power of the noise signal on the unselected channels that appears in the FFT of this channel. The noise frequency on the unselected channels varies from 40 kHz to 740 kHz. The noise amplitude is at 2 ×

, while the signal amplitude is at 1 × V

REF

Power Supply Rejection Ratio (PSRR)

PSRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC V

supply of frequency fS. The frequenc y

of the noise varies from 1 kHz to 1 MHz.

PSRR (dB) = 10 log (Pf/Pf

Pf is the power at frequency f in the ADC output; Pf

power at frequency f

in the ADC output.

)

is the

Common-Mode Rejection Ratio (CMRR)

CMRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the common-mode voltage of V frequency f

CMRR (dB) = 10log(Pf/Pf

)

IN+

and V

Pf is the power at frequency f in the ADC output; Pf power at frequency f

in the ADC output.

IN−

is the

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns to track mode at the end of conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1/2 LSB, after the end of conversion.

Rev. 0 | Page 11 of 32

AD7938/AD7939

Signal-to-(Noise + Distortion) Ratio (SINAD)

This is the measured ratio of signal-to-(noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

Thus, for a 12-bit converter, this is 74 dB, and for a 10-bit converter, this is 62 dB.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7938/ AD7939, it is defined as

()

THD

where V V

is the rms amplitude of the fundamental and V2, V3,

, V5, and V6 are the rms amplitudes of the second through the

20logdB

−=

sixth harmonics.

/2), excluding dc.

22222

VVVVV

++++

65432

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to f

/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

The AD7938/AD7939 are tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs.

Rev. 0 | Page 12 of 32

AD7938/AD7939

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise noted.

–60

100mV p-p SINE WAVE ON VDD AND/OR V NO DECOUPLING DIFFERENTIAL/SINGLE-ENDED MODE

–70

–80

–90

PSSR (dB)

–100

–110

–120

10 210 610410 810 1010

INT REF

EXT REF

SUPPLY RIPPLE FREQUENCY (kHz)

DRIVE

Figure 3. PSRR vs. Supply Ripple Frequency without Supply Decoupling

03715-0-007

0 –10 –20 –30 –40 –50

–60 –70 –80 –90

–100 –110

100

200

300

FREQUENCY (kHz)

Figure 6. AD7938 FFT @ V

4096 POINT FFT

= 5V

= 1.5MSPS

SAMPLE

= 49.62kHz

SINAD = 70.94dB THD = –90.09dB DIFFERENTIAL MODE

400

500

= 5 V

600

03715-0-009

700

–70

INTERNAL/EXTERNAL REFERENCE V

= 5V

–75

–80

–85

NOISE ISOLATION (dB)

–90

–195

0 100 400200 300 600500 800700

NOISE FREQUENCY (kHz)

03715-0-021

Figure 4. AD7938 Channel-to-Channel Isolation

SINAD (dB)

= 1.5MSPS

SAMPLE

RANGE = 0 TO V DIFFERENTIAL MODE

0 100 400200 300 600500 1000700 800 900

REF

FREQUENCY (kHz)

VDD = 5V

VDD = 3V

03715-0-008

Figure 5. AD7938 SINAD vs. Analog Input Frequency for Various Supply Voltages

1.0

0.8

0.6

0.4

0.2 0

–0.2

DNL ERROR (LSB)

–0.4

–0.6 –0.8 –1.0

0 500 20001000 1500 30002500 40003500

CODE

Figure 7. AD7938 Typical DNL @ V

1.0

0.8

0.6

0.4

0.2 0

–0.2

INL ERROR (LSB)

–0.4

–0.6 –0.8 –1.0

0 500 20001000 1500 30002500 40003500

CODE

Figure 8. AD7938 Typical INL @ V

VDD = 5V DIFFERENTIAL MODE

= 5 V

VDD = 5V DIFFERENTIAL MODE

= 5 V

03715-0-010

03715-0-011

Rev. 0 | Page 13 of 32

AD7938/AD7939

SINGLE-ENDED MODE

DNL (LSB)

–1

0.25 0.50 1.250.75 1.00 2.001.751.50 2.752.502.25

Figure 9. AD7938 DNL vs. V

EFFECTIVE NUMBER OF BITS

POSITIVE DNL

NEGATIVE DNL

(V)

REF

for VDD = 3 V

REF

DIFFERENTIAL MODE

SINGLE-ENDED MODE

VDD = 5V

VDD = 3V SINGLE-ENDED MODE

VDD = 3V DIFFERENTIAL MODE

03715-0-012

10000

DIFFERENTIAL MODE

9000

8000

7000

6000

5000

???

4000

3000

2000 1000

2046 2047 2048 2049 2050

9997

CODES

CODE

Figure 12. AD7938 Histogram of Codes for

10k Samples @ V

–60

DIFFERENTIAL MODE

–70

–80

–90

CMRR (dB)

–100

–110

= 5 V with the Internal Reference

3 CODES

INTERNAL

REF

03715-0-015

0 0.5 1.51.0 2.52.0 4.03.53.0

(V)

REF

Figure 10. AD7938 ENOB vs. V

04751-013

REF

–120

0 200 400 800600 12001000

RIPPLE FREQUENCY (kHz)

Figure 13. CMRR vs. Input Frequency with V

= 5 V and 3 V

03715-0-017

–0.5

–1.0

–1.5

–2.0

–2.5 –3.0

OFFSET (LSB)

–3.5

–4.0 –4.5 –5.0

0 0.5 1.51.0 2.52.0 3.53.0

VDD = 5V

VDD = 3V

(V)

REF

Figure 11. AD7938 Offset vs. V

SINGLE-ENDED MODE

REF

03715-0-014

Rev. 0 | Page 14 of 32

AD7938/AD7939

ON-CHIP REGISTERS

The AD7938/AD7939 have two on-chip registers that are necessary for the operation of the device. These are the control register, which is used to set up different operating conditions, and the shadow register, which is used to program the analog input channels to be converted.

CONTROL REGISTER

The control register on the AD7938/AD7939 is a 12-bit, write-only register. Data is written to this register using the CS and WR pins. The control register is shown below and the functions of the bits are described in Table 7. At power up, the default bit settings in the control

Table 6. Control Register Bits

MSB LSB DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

PM1 PM0 CODING REF ADD2 ADD1 ADD0 MODE1 MODE0 SHDW SEQ RANGE

Table 7. Control Register Bit Function Description

Bit No. Mnemonic Description

11, 10 PM1, PM0

9 CODING

8 REF

7 to 5

4, 3

2 SHDW

1 SEQ

0 RANGE

ADD2 to ADD0

MODE1, MODE0

Table 8. Power Mode Selection using the Power Management Bits in the Control Register

PM1 PM0 Mode Description

0 0 Normal Mode When operating in normal mode, all circuitry is fully powered up at all times. 0 1 Autoshutdown

1 0 Autostandby

1 1 Full Shutdown

Power Management Bits. These two bits are used to select the power mode of operation. The user can choose between either normal mode or various power-down modes of operation as shown in Table 8.

This bit selects the output coding of the conversion result. If this bit is set to 0, the output coding is straight (natural) binary. If this bit is set to 1, the output coding is twos complement.

This bit selects whether the internal or external reference is used to perform the conversion. If this bit is Logic 0, an external reference should be applied to the V the Reference Section).

These three address bits are used to either select which analog input channel is converted in the next conversion if the sequencer is not used, or to select the final channel in a consecutive sequence when the sequencer is used as described in Table 10. The selected input channel is decoded as shown in Table 9.

The two mode pins select the type of analog input on the eight V eight single-ended inputs, four fully differential inputs, four pseudo-differential inputs, or seven pseudodifferential inputs (see Table 9).

The SHDW bit in the control register is used in conjunction with the SEQ bit to control the sequencer function and access the SHDW register (see Table 10).

The SEQ bit in the control register is used in conjunction with the SHDW bit to control the sequencer function and access the SHDW register (see Table 10).

This bit selects the analog input range of the AD7938/AD7939. If it is set to 0, then the analog input range extends from 0 V to V selected, AV the analog input remains within the supply rails. See Analog Inputs section for more information.

. If it is set to 1, then the analog input range extends from 0 V to 2 × V

REF

must be 4.75 V to 5.25 V if a 2.5 V reference is used; otherwise, care must be taken to ensure that

When operating in autoshutdown mode, the AD7938/AD7939 enter full shutdown mode at the end of each conversion. In this mode, all circuitry is powered down.

When the AD7938/AD7939 enter this mode, all circuitry is powered down except for the reference and reference buffer. This mode is similar to autoshutdown mode, but it allows the part to power-up in 7 µs (or 600 ns if an external reference is used). See the Power Modes of Operation section for more information.

When the AD7938/AD7939 enter this mode, all circuitry is powered down. The information in the control register is retained.

pin, and if this bit is Logic 1, the internal reference is selected (see

REF

pins. The AD7938/AD7939 can have either

. When this range is

REF

Rev. 0 | Page 15 of 32

AD7938/AD7939

Table 9. Analog Input Type Selection

Channel Address MODE0 = 0, MODE1 = 0 MODE0 = 0, MODE1 = 1 MODE0 = 1, MODE1 = 0 MODE0 = 1, MODE1 = 1

ADD2 ADD1 ADD0 V

0 0 0 VIN0 AGND VIN0 VIN1 VIN0 VIN1 VIN0 VIN7 0 0 1 VIN1 AGND VIN1 VIN0 VIN1 VIN0 VIN1 VIN7 0 1 0 VIN2 AGND VIN2 VIN3 VIN2 VIN3 VIN2 VIN7 0 1 1 VIN3 AGND VIN3 VIN2 VIN3 VIN2 VIN3 VIN7 1 0 0 VIN4 AGND VIN4 VIN5 VIN4 VIN5 VIN4 VIN7 1 0 1 VIN5 AGND VIN5 VIN4 VIN5 VIN4 VIN5 VIN7 1 1 0 VIN6 AGND VIN6 VIN7 VIN6 VIN7 VIN6 VIN7 1 1 1 VIN7 AGND VIN7 VIN6 VIN7 VIN6 Not Allowed

SEQUENCER OPERATION

The configuration of the SEQ and SHDW bits in the control register allows the user to select a particular mode of operation of the sequencer function. Table 10 outlines the four modes of operation of the sequencer.

Table 10. Sequence Selection

SEQ SHDW Sequence Type

0 0

0 1

1 0

1 1

This configuration is selected when the sequence function is not used. The analog input channel selected on each individual conversion is determined by the contents of the channel address bits, ADD2 to ADD0, in each prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer function being used, where each write to the AD7938/AD7939 selects the next channel for conversion.

This configuration selects the shadow register for programming. The following write operation loads the data on DB0 to DB7 to the shadow register. This programs the sequence of channels to be converted continuously after each falling edge (see the shadow register description and Table 11).

If the SEQ and SHADOW bits are set in this way, the sequence function is not interrupted upon completion of the write operation. This allows other bits in the control register to be altered between conversions while in a sequence without terminating the cycle.

This configuration is used in conjunction with the channel address bits (ADD2 to ADD0) to program continuous conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by the channel address bits in the control register.

Eight Single-Ended I/P Channels

IN+

IN-

Four Fully Differential I/P Channels

IN+

IN-

Four Pseudo-Differential I/P Channels (Pseudo Mode 1)

IN+

IN-

Seven Pseudo-Differential I/P Channels (Pseudo Mode 2)

IN+

IN-

CONVST

SHADOW REGISTER

The shadow register on the AD7938/AD7939 is an 8-bit, write-only register. Data is loaded from DB0 to DB7 on the rising edge of WR. The eight LSBs load into the shadow register. The information is written into the shadow register provided that the SEQ and SHDW bits

in the control register were set to 0 and 1, respectively, in the previous write to the control register. Each bit represents an analog input from Channel 0 through Channel 7. A sequence of channels may be selected through which the AD7938/AD7939 cycles with each consecutive conversion after the write to the shadow register. To select a sequence of channels to be converted, if operating in singleended mode or Pseudo Mode 2, the associated channel bit in the shadow register must be set for each required analog input. When operating in differential mode or Pseudo Mode 1, the associated pair of channels’ bits must be set for each pair of analog inputs required in the sequence. With each consecutive

CONVST

selected channels in ascending order, beginning with the lowest channel. This continues until a write operation occurs with the SEQ and SHDW bits configured in any way except 1, 0 (see Table 10). When a sequence is set up in differential or Pseudo Mode 1, the ADC does not convert on the inverse pairs (i.e., VIN1, VIN0). The bit functions of the shadow register are outlined in Table 11. See the Analog Input Selection section for further information on using the sequencer.

Table 11. Shadow Register Bit Functions

VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7

pulse after the sequencer has been set up, the AD7938/AD7939 progress through the

Rev. 0 | Page 16 of 32

AD7938/AD7939

CIRCUIT INFORMATION

The AD7938/AD7939 are fast, 8-channel, 12-bit and 10-bit, single-supply, successive approximation analog-to-digital converters. The parts can operate from a 2.7 V to 5.25 V power supply and feature throughput rates up to 1.5 MSPS.

The AD7938/AD7939 provide the user with an on-chip trackand-hold, an accurate internal reference, an analog-to-digital converter, and a parallel interface housed in a 32-lead LFCSP or TQFP package.

The AD7938/AD7939 have eight analog input channels that can be configured to be eight single-ended inputs, four fully differential pairs, four pseudo-differential pairs, or seven pseudo-differential inputs with respect to one common input. There is an on-chip user-programmable channel sequencer that allows the user to select a sequence of channels through which the ADC can progress and cycle with each consecutive falling edge of

CONVST

The analog input range for the AD7938/AD7939 is 0 to V 0 to 2 × V

depending on the status of the RANGE bit in the

REF

control register. The output coding of the ADC can be either binary or twos complement, depending on the status of the CODING bit in the control register.

The AD7938/AD7939 provide flexible power management options to allow the user to achieve the best power performance for a given throughput rate. These options are selected by programming the power management bits, PM1 and PM0, in the control register.

CONVERTER OPERATION

The AD7938/AD7939 are successive approximation ADCs based around two capacitive DACs. Figure 14 and Figure 15 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC comprises of control logic, a SAR, and two capacitive DACs. Both figures show the operation of the ADC in differential/pseudo-differential mode. Single-ended mode operation is similar but V tied to AGND. In acquisition phase, SW3 is closed, SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input.

is internally

IN−

When the ADC starts a conversion (Figure 15), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC’s output code. The output impedances of the sources driving the V

+ and the V

IN−

pins must match; otherwise, the two inputs have different settling times, which result in errors.

CAPACITIVE

DAC

IN+

IN–

SW1

SW2

REF

SW3

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

03715-0-024

Figure 15. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding for the AD7938/AD7939 is either straight binary or twos complement, depending on the status of the CODING bit in the control register. The designed code transitions occur at successive LSB values (i.e., 1 LSB, 2 LSBs, and so on) and the LSB size is V V

/1024 for the AD7939. The ideal transfer characteristics

REF

of the AD7938/AD7939 for both straight binary and twos complement output coding are shown in Figure 16 and Figure 17, respectively.

111...111

111...110

111...000

011...111

ADC CODE

/4096 for the AD7938 and

REF

1 LSB = V 1 LSB = V

/4096 (AD7938)

REF

/1024 (AD7939)

REF

CAPACITIVE

DAC

IN+

IN–

SW1

SW2

REF

SW3

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

03715-0-023

000...010

000...001

000...000 1 LSB +V

NOTE: V

IS EITHER V

REF

ANALOG INPUT

REF

OR 2 × V

REF

Figure 16. AD7938/AD7939 Ideal Transfer Characteristic

with Straight Binary Output Coding

–1 LSB

03715-0-025

Figure 14. ADC Acquisition Phase

Rev. 0 | Page 17 of 32

AD7938/AD7939

1 LSB = 2

–V

REF

1 LSB = 2

+ 1 LSB V

011...111

011...110

000...001

000...000

111...111

ADC CODE

100...010

100...001

100...000

Figure 17. AD7938/AD7939 Ideal Transfer Characteristic

with Twos Complement Output Coding and 2 × V

TYPICAL CONNECTION DIAGRAM

Figure 18 shows a typical connection diagram for the AD7938/AD7939. The AGND and DGND pins are connected together at the device for good noise suppression. The V V

pin is decoupled to AGND with a 0.47 µF capacitor to

REFOUT

avoid noise pickup if the internal reference is used. Alternatively, V

REFIN/VREFOUT

and in this case, the reference pin should be decoupled with a

0.1 µF capacitor. In both cases, the analog input range can either be 0 V to V = 1). The analog input configuration can be either eight singleended inputs, four differential pairs, four pseudo-differential pairs, or seven pseudo-differential inputs (see Table 9). The V pin is connected to either a 3 V or 5 V supply. The voltage applied to the V interface and here, it is connected to the same 3 V supply of the microprocessor to allow a 3 V logic interface (see the Digital Inputs section).

0 TO V

0 TO 2 × V

2.5V

REF

can be connected to an external reference source,

(RANGE bit = 0) or 0 V to 2 × V

REF

input controls the voltage of the digital

DRIVE

0.1µF10µF

AD7938/AD7939

VIN0

REF

VIN7

AGND DGND

REFIN/VREFOUT

0.1µF EXTERNAL V

0.47µF INTERNAL V

Figure 18. Typical Connection Diagram

REF

DB11/DB9

3V/5V SUPPLY

CONVST

/4096 (AD7938) /1024 (AD7939)

REF

W/B

CLKIN

CS RD

BUSY

DB0

DRIVE

0.1µF

REF

– 1 LSB

REF

(RANGE bit

REF

Range

µC/µP

10µF

SUPPLY

REFIN

03715-0-026

03715-0-027

ANALOG INPUT STRUCTURE

Figure 19 shows the equivalent circuit of the analog input structure of the AD7938/AD7939 in differential/pseudo differential mode. In single-ended mode, V tied to AGND. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This causes these diodes to become forward-biased and starts conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part.

The C1 capacitors in Figure 19 are typically 4 pF and can primarily be attributed to pin capacitance. The resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 100 Ω. The C2 capacitors are the ADC’s sampling capacitors and have a capacitance of 40 pF typically.

For ac applications, removing high frequency components from the analog input signal is recommended by the use of an RC low-pass filter on the relevant analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application.

–

Figure 19. Equivalent Analog Input Circuit,

Conversion Phase—Switches Open, Track Phase—Switches Closed

When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of THD that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 20 and Figure 21 show a graph of the THD vs. source impedance with a 50 kHz input tone for both V

= 5 V and 3 V in single-ended mode and

differential mode, respectively.

IN−

R1 C2

is internally

03715-0-028

Rev. 0 | Page 18 of 32

AD7938/AD7939

–40

FIN = 50kHz

–45 –50

–55

–60

–65

THD (dB)

–70

–75 –80

–85 –90

10 100 1k 10k

SOURCE

VDD = 3V

VDD = 5V

(Ω)

Figure 20. THD vs. Source Impedance in Single-Ended Mode

–60

FIN = 50kHz

–65

–70

–75

–80

THD (dB)

–85

VDD = 3V

–90

–95

–100

10 100 1k 10k

VDD = 5V

SOURCE

(Ω)

Figure 21. THD vs. Source Impedance in Differential Mode

03715-0-018

03715-0-019

ANALOG INPUTS

The AD7938/AD7939 have software selectable analog input configurations. The user can choose either eight single-ended inputs, four fully differential pairs, four pseudo-differential pairs, or seven pseudo-differential inputs. The analog input configuration is chosen by setting the MODE0/MODE1 bits in the internal control register (see Table 9).

Single-Ended Mode

The AD7938/AD7939 can have eight single-ended analog input channels by setting the MODE0 and MODE1 bits in the control register to 0. In applications where the signal source has a high impedance, it is recommended to buffer the analog input before applying it to the ADC. The analog input range can be programmed to be either 0 to V

If the analog input signal to be sampled is bipolar, the internal reference of the ADC can be used to externally bias up this signal to make it the correct format for the ADC.

Figure 23 shows a typical connection diagram when operating the ADC in single-ended mode.

+1.25V

–1.25V

REF

or 0 to 2 × V

+2.5V

IN0

IN7

REF

AD7938/

AD7939*

REFOUT

0.47µF

Figure 22 shows a graph of the THD vs. the analog input frequency for various supplies while sampling at 1.5 MHz with an SCLK of 25.5 MHz. In this case, the source impedance is 10 Ω.

–50

VDD = 3V

–60

–70

–80

–90

THD (dB)

–100

–110

–120

0 100 400200 300 600500 700

Figure 22. THD vs. Analog Input Frequency for Various Supply Voltages

SINGLE-ENDED MODE

VDD = 5V/3V DIFFERENTIAL MODE

= 1.5MSPS

SAMPLE

RANGE = 0 TO V

VDD = 5V SINGLE-ENDED MODE

REF

INPUT FREQUENCY (kHz)

03715-0-020

Rev. 0 | Page 19 of 32

*ADDITIONAL PINS OMITTED FOR CLARITY

03715-0-031

Figure 23. Single-Ended Mode Connection Diagram

Differential Mode

The AD7938/AD7939 can have four differential analog input pairs by setting the MODE0 and MODE1 bits in the control register to 0 and 1, respectively.

Differential signals have some benefits over single-ended signals, including noise immunity based on the device’s common-mode rejection and improvements in distortion performance. Figure 24 defines the fully differential analog input of the AD7938/AD7939.

REF

p-p

REF

COMMON-MODE

VOLTAGE

p-p

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 24. Differential Input Definition

IN+

AD7938/

AD7939*

IN–

03715-0-032

AD7938/AD7939

The amplitude of the differential signal is the difference between the signals applied to the V differential pair (i.e., V

IN+

− V

IN−

simultaneously driven by two signals each of amplitude V 2 × V phase (assuming the 0 to V

depending on the range chosen) that are 180° out of

REF

range is selected). The amplitude

REF

of the differential signal is therefore −V peak (i.e., 2 × V

). This is regardless of the common mode

REF

). V

IN+

and V

REF

IN−

to +V

should be

pins in each

REF

peak-to-

REF

(or

(CM). The common mode is the average of the two signals, i.e. (V

+ V

IN+

)/2 and is therefore the voltage on which the two

IN−

inputs are centered. This results in the span of each input being CM ± V range varies with the reference value V

/2. This voltage has to be set up externally and its

REF

. As the value of V

REF

increases, the common-mode range decreases. When driving the inputs with an amplifier, the actual common-mode range is determined by the amplifier’s output voltage swing.

Figure 25 and Figure 26 show how the common-mode range typically varies with V V

range or 2 × V

REF

for a 5 V power supply using the 0 to

REF

range, respectively. The common mode

REF

must be in this range to guarantee the functionality of the AD7938/AD7939.

When a conversion takes place, the common mode is rejected, resulting in a virtually noise free signal of amplitude −V +V

corresponding to the digital codes of 0 to 4096 for the

REF

AD7938 and 0 to 1024 for the AD7939. If the 2 × V used then the input signal amplitude would extend from −2V to +2V

after conversion.

REF

3.5 TA = 25°C

3.0

2.5

2.0

1.5

1.0

COMMON-MODE RANGE (V)

0.5

0 0.5 1.51.0 2.0 2.5 3.0

(V)

REF

Figure 25. Input Common-Mode Range vs. V

REF

(0 to V

Range, VDD = 5 V)

REF

range is

REF

03715-0-033

4.5 TA = 25°C

4.0

3.5

3.0

2.5

2.0

1.5

COMMON-MODE RANGE (V)

1.0

0.5

0.1 0.6 1.61.1 2.1 2.6

Figure 26. Input Common-Mode Range vs. V

(V)

REF

(2 × V

REF

Range, VDD = 5 V)

REF

03715-0-034

Driving Differential Inputs

Differential operation requires that V

IN+

and V

IN−

be simultaneously driven with two equal signals that are 180° out of phase. The common mode must be set up externally and has a range that is determined by V

, the power supply, and the

REF

particular amplifier used to drive the analog inputs. Differential modes of operation with either an ac or dc input provide the best THD performance over a wide frequency range. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform single-ended-todifferential conversion.

Using an Op Amp Pair

An op amp pair can be used to directly couple a differential signal to one of the analog input pairs of the AD7938/AD7939. The circuit configurations shown in Figure 27 and Figure 28 show how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively.

The voltage applied to Point A sets up the common-mode voltage. In both diagrams, it is connected in some way to the reference, but any value in the common-mode range can be input here to set up the common mode. A suitable dual op amp that could be used in this configuration to provide differential drive to the AD7938/AD7939 is the AD8022.

Take care when choosing the op amp; the selection depends on the required power supply and system performance objectives. The driver circuits in Figure 27 and Figure 28 are optimized for dc coupling applications requiring best distortion performance.

The circuit configuration shown in Figure 27 converts a unipolar, single-ended signal into a differential signal.

The differential op amp driver circuit in Figure 28 is configured to convert and level shift a single-ended, ground-referenced (bipolar) signal to a differential signal centered at the V of the ADC.

Rev. 0 | Page 20 of 32

REF

level

AD7938/AD7939

REF

GND

2× V

REF

p-p

390Ω

220Ω

20kΩ

220Ω

V+

27Ω

V–

220Ω 220Ω

V+

10kΩ

27Ω

V–

3.75V

2.5V

1.25V

3.75V

2.5V

1.25V

IN+

AD7938/

AD7939

IN–

0.47µF

REF

Figure 27. Dual Op Amp Circuit to Convert a Single-Ended

Unipolar Signal into a Differential Signal

REF

GND

2× V

REF

p-p

390Ω

20kΩ

220Ω

V+

27Ω

V–

220Ω 220Ω

V+

10kΩ

27Ω

V–

3.75V

2.5V

1.25V

3.75V

2.5V

1.25V

IN+

AD7938/

AD7939

IN–

0.47µF

REF

Figure 28. Dual Op Amp Circuit to Convert a Single-Ended

Bipolar Signal into a Differential Unipolar Signal

Pseudo-Differential Mode

The AD7938/AD7939 can have four pseudo-differential pairs (Pseudo Mode 1) or seven pseudo differential inputs (Pseudo Mode 2) by setting the MODE0 and MODE1 bits in the control register to 1, 0 and 1, 1, respectively. In the case of the four pseudo-differential pairs, V which must have an amplitude of V

+ is connected to the signal source

(or 2 × V

REF

depending

REF

on the range chosen) to make use of the full dynamic range of the part. A dc input is applied to the V

pin. The voltage

IN−

applied to this input provides an offset from ground or a pseudo ground for the V

input. In the case of the seven pseudo-

IN+

differential inputs, the seven analog input signals inputs are referred to a dc voltage applied to V

7. The benefit of pseudo-

differential inputs is that they separate the analog input signal ground from the ADC’s ground allowing dc common-mode voltages to be cancelled. Typically, this range can extend to

−0.3 V to +0.7 V when V

= 3 V or −0.3 V to +1.8 V when VDD

= 5 V. Figure 29 shows a connection diagram for pseudodifferential mode.

03715-0-035

03715-0-036

p-p

REF

DC INPUT

VOLTAGE

*ADDITIONAL PINS OMITTED FOR CLARITY

IN+

AD7938/ AD7939*

IN–

REF

0.47µF

03715-0-037

Figure 29. Pseudo-Differential Mode Connection Diagram

ANALOG INPUT SELECTION

As shown in Table 9, the user can set up their analog input configuration by setting the values in the MODE0 and MODE1 bits in the control register. Assuming the configuration has been chosen, there are different ways of selecting the analog input to be converted depending on the state of the SEQ and SHDW bits in the control register.

Traditional Multichannel Operation (SEQ = SHDW = 0)

Any one of eight analog input channels or four pairs of channels may be selected for conversion in any order by setting the SEQ and SHDW bits in the control register to 0. The channel to be converted is selected by writing to the address bits, ADD2 to ADD0, in the control register to program the multiplexer prior to the conversion. This mode of operation is that of a traditional multichannel ADC where each data write selects the next channel for conversion. Figure 30 shows a flow chart of this mode of operation. The channel configurations are shown in Table 9.

POWER ON

WRITE TO THE CONTROL REGISTER TO

SET UP OPERATING MODE, ANALOG INPUT

AND OUTPUT CONFIGURATION

SET SEQ = SHDW = 0. SELECT THE DESIRED

CHANNEL TO CONVERT (ADD2 TO ADD0).

ISSUE CONVST PULSE TO INITIATE A CONVERSION

Figure 30. Traditional Multichannel Operation Flow Chart

Using the Sequencer: Programmable Sequence (SEQ = 0, SHDW = 1 )

The AD7938/AD7939 may be configured to automatically cycle through a number of selected channels using the on-chip programmable sequencer by setting SEQ = 0 and SHDW = 1 in the control register. The analog input channels to be converted are selected by setting the relevant bits in the shadow register to 1, see Table 11.

ON THE SELECTED CHANNEL.

INITIATE A READ CYCLE TO READ THE DATA

FROM THE SELECTED CHANNEL.

INITIATE A WRITE CYCLE TO SELECT THE NEXT

CHANNEL TO BE CONVERTED BY

CHANGING THE VALUES OF BITS ADD2 TO ADD0

IN THE CONTROL REGISTER. SEQ = SHDW = 0.

03715-0-038

Rev. 0 | Page 21 of 32

AD7938/AD7939

Once the shadow register has been programmed with the required sequence, the next conversion executed is on the lowest channel programmed in the SHDW register. The next conversion executed is on the next highest channel in the sequence and so on. When the last channel in the sequence is converted, the internal multiplexer returns to the first channel selected in the shadow register and commences the sequence again.

It is not necessary to write to the control register again once a sequencer operation has been initiated. The

kept high to ensure that the control register is not accidentally overwritten or that a sequence operation is not interrupted. If the control register is written to at any time during the sequence, then ensure that the SEQ and SHDW bits are set to 1, 0 to avoid interrupting the conversion sequence. The sequence program remains in force until such time as the AD7938/AD7939 is written to and the SEQ and SHDW bits are configured with any bit combination except 1, 0. Figure 31 shows a flow chart of the programmable sequence operation.

POWER ON

WRITE TO THE CONTROL REGISTER TO

SET UP OPERATING MODE, ANALOG INPUT

AND OUTPUT CONFIGURATION

SET SEQ = 0 SHDW = 1.

THIS WRITE CYCLE IS TO THE SHADOW REGISTER.

THE CHANNELS TO BE INCLUDED IN THE SEQUENCE.

CONTINUOUSLY CONVERT

CONSECUTIVE

CHANNELS SELECTED

IN THE SHADOW REGISTER

WITH EACH CONVST PULSE.

INITIATE A WRITE CYCLE.

SET RELEVANT BITS TO SELECT

WR = HIGH

SEQ BIT = 0

SHDW BIT = 1

SEQ BIT = 1 SHDW BIT = 0

CONTINUOUSLY CONVERT

WITH EACH CONVST PULSE

BUT ALLOWS THE RANGE,

CODING, ANALOG INPUT TYPE,

ETC BITS IN THE CONTROL

WITHOUT INTERRUPTING

CONSECUTIVE

CHANNELS SELECTED

THE SEQUENCE.

Figure 31. Programmable Sequence Flow Chart

Consecutive Sequence (SEQ = 1, SHDW = 1)

A sequence of consecutive channels can be converted beginning with Channel 0 and ending with a final channel selected by writing to the ADD2 to ADD0 bits in the control register. This is done by setting the SEQ and SHDW bits in the control register to 1. In this mode, the sequencer can be used without having to write to the shadow register. Once the control register is written to, to set this mode up, the next conversion is on Channel 0, then Channel 1, and so on until the channel selected by the address bits (ADD2 to ADD0) is reached. The cycle begins again provided the

input is tied high. If low, the SEQ

and SHDW bits must be set to 1, 0 to allow the ADC to continue its preprogrammed sequence uninterrupted. Figure 32 shows the flow chart of the consecutive sequence mode.

input must be

03715-0-039

POWER ON

WRITE TO THE CONTROL REGISTER TO

SET UP OPERATING MODE, ANALOG INPUT

AND OUTPUT CONFIGURATION SELECT

FINAL CHANNEL (ADD2 TO ADD0) IN

CONSECUTIVE SEQUENCE.

SET SEQ = 1 SHDW = 1.

CONTINUOUSLY CONVERT A CONSECUTIVE

SEQUENCE OF CHANNELS FROM CHANNEL 0

UP TO AND INCLUDING THE PREVIOUSLY

SELECTED FINAL CHANNEL ON ADD2 TO ADD0

WITH EACH CONVST PULSE.

SEQ BIT = 1 SHDW BIT = 0

CONTINUOUSLY CONVERT

CONSECUTIVE CHANNELS SELECTED

WITH EACH CONVST PULSE BUT

ALLOWS THE RANGE, CODING, ANALOG

INPUT TYPE, ETC BITS IN THE

CONTROL REGISTER TO BE CHANGED

WITHOUT INTERRUPTING

THE SEQUENCE.

03715-0-040

Figure 32. Consecutive Sequence Mode Flow Chart

REFERENCE SECTION

The AD7938/AD7939 can operate with either the on-chip or external reference. The internal reference is selected by setting the REF bit in the internal control register to 1. A block diagram of the internal reference circuitry is shown in Figure 33. The internal reference circuitry includes an on-chip 2.5 V band gap reference and a reference buffer. When using the internal reference, the V

REFIN/VREFOUT

with a 0.47 µF capacitor. This internal reference not only provides the reference for the analog-to-digital conversion, but it can also be used externally in the system. It is recommended that the reference output is buffered using an external precision op amp before applying it anywhere in the system.

REFIN

REFOUT

Figure 33. Internal Reference Circuit Block Diagram

Alternatively, an external reference can be applied to the V V

pin of the AD7938/AD7939. An external reference input

REFOUT

is selected by setting the REF bit in the internal control register to 0. The external reference input range is 0.1 V to V important to ensure that, when choosing the reference value, the maximum analog input range (V

+ 0.3 V to comply with the maximum ratings of the device.

For example, if operating in differential mode and the reference is sourced from V

, then the 0 to 2 × V

used. This is because the analog input signal range would now extend to 2 × V

, which would exceed the maximum rating

conditions. In the pseudo-differential modes, the user must ensure that V

REF

+ (V

or when using the 2 × V

pin should be decoupled to AGND

BUFFER

REFERENCE

AD7938/

ADC

AD7939

) is never greater than

IN MAX

range cannot be

REF

) ≤ VDD when using the 0 to V

IN−

range that 2 × V

REF

+(V

03715-0-041

REF

) ≤ VDD.

IN−

. It is

range,

REFIN

Rev. 0 | Page 22 of 32

AD7938/AD7939

In all cases, the specified reference is 2.5 V.

The performance of the part with different reference values is shown in Figure 9 to Figure 11. The value of the reference sets the analog input span and the common-mode voltage range. Errors in the reference source result in gain errors in the AD7938/AD7939 transfer function and add to specified fullscale errors on the part.

Table 12 lists examples of suitable voltage references that could be used that are available from Analog Devices and Figure 34 shows a typical connection diagram for an external reference.

Table 12. Examples of Suitable Voltage References

Reference

Output Voltage

Initial Accuracy (% Max)

Operating Current (µA)

AD780 2.5/3 0.04 1000 ADR421 2.5 0.04 500 ADR420 2.048 0.05 500

AD7938/ AD7939*

0.1µF

REF

0.1µF

10nF 0.1µF

O/PSELECT

TEMP

GND

NC = NO CONNECT

AD780

OUT

TRIM

2.5V

6 5

Digital Inputs

The digital inputs applied to the AD7938/AD7939 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied can go to 7 V and are not restricted by the AV

+ 0.3 V limit as on the analog inputs.

Another advantage of the digital inputs not being restricted by the AV

+ 0.3 V limit is the fact that power supply sequencing

issues are avoided. If any of these inputs are applied before AV

, then there is no risk of latch-up as there would be on the

analog inputs if a signal greater than 0.3 V was applied prior to AV

DD.

Input

DRIVE

The AD7938/AD7939 have a V voltage at which the parallel interface operates. V

DRIVE

feature. V

controls the

DRIVE

allows the

ADC to easily interface to 3 V and 5 V processors.

For example, if the AD7938/AD7939 are operated with an AV of 5 V and the V

pin is powered from a 3 V supply, the

DRIVE

AD7938/AD7939 have better dynamic performance with an AV

of 5V while still being able to interface directly to 3 V

processors. Care should be taken to ensure V exceed AV

by more than 0.3 V (see the Absolute Maximum

DRIVE

does not

Ratings section).

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 34. Typical V

REF

Connection Diagram

03715-0-042

Rev. 0 | Page 23 of 32

AD7938/AD7939

PARALLEL INTERFACE

The AD7938/AD7939 have a flexible, high speed, parallel interface. This interface is 12-bits (AD7938) or 10-bits (AD7939) wide and is capable of operating in either word (W/

tied high) or byte (W/B tied low) mode. The

CONVST

signal is used to initiate conversions and when operating in autoshutdown or autostandby mode, it is used to initiate power up.

A falling edge on the

CONVST

signal is used to initiate

conversions and it also puts the ADC track-and-hold into track. Once the

CONVST

signal goes low, the BUSY signal goes high

for the duration of the conversion. In between conversions, CONVST must happen after the 14

must be brought high for a minimum time of t1. This

falling edge of CLKIN; otherwise, the

conversion is aborted and the track-and-hold goes back into track. At the end of the conversion, BUSY goes low and can be used to activate an interrupt service routine. The

and RD

lines are then activated in parallel to read the 12- or 10- bits of conversion data. When power supplies are first applied to the device, a rising edge on

CONVST

is necessary to put the track-

and-hold into track. The acquisition time of 125 ns minimum must be allowed before

CONVST

is brought low to initiate a

conversion. The ADC then goes into hold on the falling edge of CONVST

and back into track on the 13th rising edge of CLKIN

after this (see Figure 35). When operating the device in autoshutdown or autostandby mode, where the ADC powers down at the end of each conversion, a rising edge on the CONVST

signal is used to power up the device.

CONVST

CLKIN

BUSY

INTERNAL

TRACK/HOLD

DB0 TO DB11

12345 121314

THREE-STATE

WITH CS AND RD TIED LOW

CONVERT

Figure 35. AD7938/AD7939 Parallel Interface—Conversion and Read Cycle in Word Mode (W/

DATA

DATAOLD DATADB0 TO DB11

AQUISITION

THREE-STATE

QUIET

= 1)

03715-0-004

Rev. 0 | Page 24 of 32

AD7938/AD7939

and RD signals are gated internally and level triggered

Reading Data from the AD7938/AD7939

With the W/B pin tied logic high, the AD7938/AD7939 interface operates in word mode. In this case, a single read

operation from the device accesses the conversion data-word on Pins DB0/DB2 to DB11. The DB8/HBEN pin assumes its DB8 function. With the W/

pin tied to logic low, the AD7938/

B AD7939 interface operates in byte mode. In this case, the DB8/HBEN pin assumes its HBEN function. Conversion data from the AD7938/ AD7939 must be accessed in two read operations with 8 bits of data provided on DB0 to DB7 for each of the read operations. The HBEN pin determines whether the read operation accesses the high byte or the low byte of the 12-or 10-bit word. For a low byte read, DB0 to DB7 provide the eight LSBs of the 12-bit word. For 10-bit operation, the two LSBs of the low byte are 0s and are followed by six bits of conversion data. For a high byte read, DB0 to DB3 provide the four MSBs of the 12-/10-bit word. DB5 to DB7 of the high byte provide the Channel ID. Figure 35 shows the read cycle timing diagram for a 12-/10-bit transfer. When operated in word mode, the HBEN input does not exist, and only the first read operation is required to access data from the device. When operated in byte mode, the two read cycles shown in Figure 36 are required

to access the full data-word from the device.

The

CS active low. In either word mode or byte mode, be tied together as the timing specifications for t

and RD may

and t11 are

0 ns minimum. This would mean the bus would be constantly driven by the AD7938/AD7939.

The data is placed onto the data bus a time t

go low. The RD rising edge can be used to latch data out of

RD the device. After a time, t

Alternatively,

and RD can be tied permanently low and the

, the data lines become three-stated.

conversion data is valid and placed onto the data bus a time, t

after both CS and

before the falling edge of BUSY.

Note that if

is pulsed during the conversion time then this

causes a degradation in linearity performance of approximately

0.25 LSB. Reading during conversion by way of tying

low does not cause any degradation.

and

HBEN/DB8

DB0 TO DB7

Figure 36. AD7938/AD7939 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/

LOW BYTE HIGH BYTE

03715-0-005

= 0)

Rev. 0 | Page 25 of 32

AD7938/AD7939

Writing Data to the AD7938/AD7939

With W/B tied logic high, a single write operation transfers the full data-word on DB0 to DB11 to the control register on the

AD7938/AD7939. The DB8/HBEN pin assumes its DB8 function. Data written to the AD7938/AD7939 should be provided on the DB0 to DB11 inputs with DB0 being the LSB of the data-word. With W/

requires two write operations to transfer a full 12-bit word. DB8/HBEN assumes its HBEN function. Data written to the AD7938/AD7939 should be provided on the DB0 to DB7 inputs. HBEN determines whether the byte written is high byte or low byte data. The low byte of the data-word should be written first with DB0 being the LSB of the full data-word. For the high byte write, HBEN should be high and the data on the DB0 input should be data Bit 8 of the 12-bit word. In both word and byte mode, a single write operation to the shadow register is always sufficient since it is only 8-bits wide.

tied logic low, the AD7938/AD7939

Figure 37 shows the write cycle timing diagram of the AD7938/AD7939. When operated in word mode, the HBEN input does not exist and only one write operation is required to write the word of data to the device. Data should be provided on DB0 to DB11. When operated in byte mode, the two write cycles shown in Figure 38 are required to write the full dataword to the AD7938/AD7939. In Figure 38, the first write transfers the lower eight bits of the data-word from DB0 to DB7, and the second write transfers the upper four bits of the data-word. When writing to the AD7938/AD7939, the top four bits in the high byte must be 0s.

The data is latched into the device on the rising edge of The data needs to be setup a time, t and held for a time, t signals are gated internally.

, after the WR rising edge. The CS and WR

the timing specifications for t

, before the WR rising edge

and WR may be tied together as

and t5 are 0 ns minimum

(assuming CS and RD have not already been tied together).

DB0 TO DB11

DATA

Figure 37. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/

03715-0-002

= 1)

HBEN/DB8

DB0 TO DB11

LOW BYTE HIGH BYTE

Figure 38. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Byte Mode Operation ( W/

03715-0-003

= 0)

Rev. 0 | Page 26 of 32

AD7938/AD7939

POWER MODES OF OPERATION

The AD7938/AD7939 have four different power modes of operation. These modes are designed to provide flexible power management options. Different options can be chosen to optimize the power dissipation/throughput rate ratio for differing applications. The mode of operation is selected by the power management bits, PM1 and PM0, in the control register, as detailed in Table 8. When power is first applied to the AD7938/AD7939 an on-chip, power-on reset circuit ensures that the default power-up condition is normal mode.

Note that, after power-on, the track-and-hold is in hold mode and the first rising edge of

CONVST

into track mode.

Normal Mode (PM1 = PM0 = 0)

This mode is intended for the fastest throughput rate performance because the user does not have to worry about any power-up times associated with the AD7938/AD7939 because it remains fully powered up at all times. At power-on reset, this mode is the default setting in the control register.

Autoshutdown (PM1 = 0; PM0 = 1)

In this mode of operation, the AD7938/AD7939 automatically enter full shutdown at the end of each conversion, which is shown at Point A in Figure 35 and Figure 39. In shutdown mode, all internal circuitry on the device is powered down. The parts retain information in the control register during shutdown. The track-and-hold also goes into hold at this point and remains in hold as long as the device is in shutdown. The AD7938/AD7939 remains in shutdown mode until the next rising edge of

CONVST

(see Point B in Figure 35 or Figure 39).

In order to keep the device in shutdown for as long as possible, CONVST

should idle low between conversions as shown in

Figure 39. On this rising edge, the part begins to power-up and the track-and-hold returns to track mode. The power-up time required is 10 ms minimum regardless of whether the user is operating with the internal or external reference. The user should ensure that the power-up time has elapsed before initiating a conversion.

places the track-and-hold

Autostandby (PM1 = 1; PM0 = 0)

In this mode of operation, the AD7938/AD7939 automatically enter standby mode at the end of each conversion, which is shown as Point A in Figure 35. When this mode is entered, all circuitry on the AD7938/AD7939 is powered down except for the reference and reference buffer. The track-and-hold goes into hold at this point also and remains in hold as long as the device is in standby. The parts remain in standby until the next rising edge of

CONVST

powers up the device. The power-up time

required depends on whether the internal or external reference is used. With an external reference, the power-up time required is a minimum of 600 ns, while when using the internal reference, the power-up time required is a minimum of 7 µs. The user should ensure this power-up time has elapsed before initiating another conversion as shown in Figure 39. This rising edge of

CONVST

also places the track-and-hold back

into track mode.

Full Shutdown Mode (PM1 =1; PM0 = 1)

When this mode is programmed, all circuitry on the AD7938/AD7939 is powered down upon completion of the write operation, i.e., on rising edge of

. The track-and-hold

enters hold mode at this point. The parts retain the information in the control register while the part is in shutdown. The AD7938/AD7939 remain in full shutdown mode and the trackand-hold in hold mode, until the power management bits (PM1 and PM0) in the control register are changed. If a write to the control register occurs while the part is in full shutdown mode, and the power management bits are changed to PM0 = PM1 = 0, i.e., normal mode, the part begins to power-up on the

rising edge and the track-and-hold returns to track. To ensure the part is fully powered up before a conversion is initiated, the power-up time of 10 ms minimum should be allowed before the next

CONVST

falling edge; otherwise, invalid data is read.

Note that all power-up times quoted apply with a 470 nF capacitor on the V

REFIN

pin.

POWER-UP

03715-0-049

CONVST

CLKIN

BUSY

1 114 14

Figure 39. Autoshutdown/Autostandby Mode

Rev. 0 | Page 27 of 32

AD7938/AD7939

POWER VS. THROUGHPUT RATE

A big advantage of powering the ADC down after a conversion is that the power consumption of the part is significantly reduced at lower throughput rates. When using the different power modes, the AD7933/AD7934 are only powered up for the duration of the conversion. Therefore, the average power consumption per cycle is significantly reduced. Figure 40 shows a plot of the power vs. the throughput rate when operating in autostandby mode for both V if the maximum CLKIN frequency of 25.5 MHz is used to minimize the conversion time, this accounts for only 0.525 µs of the overall cycle time while the AD7933/AD7934 remains in standby mode for the remainder of the cycle. If the devices run at a throughput rate of 10 kSPS, for example, then the overall cycle time would be 100 µs.

Figure 41 shows a plot of the power vs. the throughput rate when operating in normal mode for both V In both plots, the figures apply when using the internal reference. If an external reference is used, the power-up time reduces to 600 ns; therefore, the AD7933/AD7934 remains in standby for a greater time in every cycle. Additionally, the current consumption, when converting, should be lower than the specified maximum of 2.7 mA or 2.0 mA with V or 3 V, respectively.

1.8 TA = 25°C

1.6

1.4

1.2

1.0

0.8

POWER (mW)

0.6

0.4

0.2

0 20 40 60 80 100 120 140

Figure 40. Power vs. Throughput in

Autostandby Mode Using Internal Reference

= 5 V and 3 V. For example,

= 5 V and 3 V.

VDD = 5V

VDD = 3V

THROUGHPUT (kSPS)

= 5 V

03715-0-042

TA = 25°C

POWER (mW)

2 1 0

0 200 400 600 800 1000 1200 16001400

THROUGHPUT (kSPS)

VDD = 5V

VDD = 3V

03715-0-043

Figure 41. Power vs. Throughput in Normal Mode Using Internal Reference

MICROPROCESSOR INTERFACING

AD7938/AD7939 to ADSP-21xx Interface

Figure 42 shows the AD7938/AD7939 interfaced to the ADSP21xx series of DSPs as a memory mapped device. A single wait state may be necessary to interface the AD7938/AD7939 to the ADSP-21xx depending on the clock speed of the DSP. The wait state can be programmed via the data memory wait state control register of the ADSP-21xx (see the ADSP-21xx family User’s Manual for details). The following instruction reads from the AD7938/AD7939:

MR = DM (ADC)

where ADC is the address of the AD7938/AD7939.

OPTIONAL

A0 TO A15

ADSP-21xx*

DMS

IRQ2

D0 TO D23

*ADDITIONAL PINS OMITTED FOR CLARITY

ADDRESS BUS

ADDRESS DECODER

DATA BUS

Figure 42. Interfacing to the ADSP-21xx

CONVST

AD7938/ AD7939*

BUSY WR

DB0 TO DB11

03715-0-045

Rev. 0 | Page 28 of 32

AD7938/AD7939

AD7938/AD7939 to ADSP-21065L Interface

Figure 43 shows a typical interface between the AD7938/AD7939 and the ADSP-21065L SHARC® processor. This interface is an example of one of three DMA handshake modes. The

lines. Internal ADDR are then asserted as chip selects. The

control line is actually three memory select

are decoded into

25-24

DMAR

, these lines

3-0

(DMA request 1)

is used in this setup as the interrupt to signal the end of conversion. The rest of the interface is standard handshaking operation.

OPTIONAL

ADDR

TO ADDR

ADSP-21065L*

DMAR

D0 TO D31

ADDITIONAL PINS REMOVED FOR CLARIT

ADDRESS BUS

ADDRESS

LATCH

ADDRESS BUS

ADDRESS DECODER

DATA BUS

CONVST

AD7938/

AD7939*

BUSY RDRD

DB0 TO DB11

Figure 43. Interfacing to the ADSP-21065L

AD7938/AD7939 to TMS32020, TMS320C25, and TMS320C5x Interface

Parallel interfaces between the AD7938/AD7939 and the TMS32020, TMS320C25, and TMS320C5x family of DSPs are shown in Figure 44. The memory mapped address chosen for the AD7938/AD7939 should be chosen to fall in the I/O memory space of the DSPs. The parallel interface on the AD7938/AD7939 is fast enough to interface to the TMS32020 with no extra wait states. If high speed glue logic, such as 74AS devices, are used to drive the

and the WR lines when

interfacing to the TMS320C25, then again, no wait states are necessary. However, if slower logic is used, data accesses may be slowed sufficiently when reading from, and writing to, the part to require the insertion of one wait state. Extra wait states are necessary when using the TMS320C5x at their fastest clock speeds (see the TMS320C5x User’s Guide for details).

Data is read from the ADC using the following instruction

03715-0-046

OPTIONAL

AD7938/

AD7939*

CSEN

BUSY DB11 TO DB0DMD0 TO DMD15

CONVST

A0 TO A15

TMS32020/ TMS320C25/ TMS320C50*

READY

MSC

STRB

INT

*ADDITIONAL PINS OMITTED FOR CLARITY

R/W

ADDRESS BUS

ADDRESS DECODER

DATA BUS

TMS320C25

ONLY

Figure 44. Interfacing to the TMS32020/C25/C5x

AD7938/AD7939 to 80C186 Interface

Figure 45 shows the AD7938/AD7939 interfaced to the 80C186 microprocessor. The 80C186 DMA controller provides two independent high speed DMA channels where data transfer can occur between memory and I/O spaces. Each data transfer consumes two bus cycles, one cycle to fetch data and the other to store data. After the AD7938/AD7939 finish a conversion, the BUSY line generates a DMA request to Channel 1 (DRQ1). Because of the interrupt, the processor performs a DMA read operation that also resets the interrupt latch. Sufficient priority must be assigned to the DMA channel to ensure that the DMA request is serviced before the completion of the next conversion.

OPTIONAL

AD0 TO AD15

A16 TO A19

80C186*

ADDITIONAL PINS OMITTED FOR CLARIT

ALE

DRQ1

ADDRESS/DATA BUS

ADDRESS

LATCH

ADDRESS BUS

ADDRESS DECODER

Figure 45. Interfacing to the 80C186

DATA BUS

CONVST

AD7938/ AD7939*

BUSY RDRD

WR DB0 TO DB11

03715-0-047

03715-0-048

IN D, ADC

where D is the data memory address and ADC is the AD7938/AD7939 address.

Rev. 0 | Page 29 of 32

AD7938/AD7939

APPLICATION HINTS

GROUNDING AND LAYOUT

The printed circuit board that houses the AD7938/AD7939 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes since it gives the best shielding. Digital and analog ground planes should be joined in only one place, and the connection should be a star ground point established as close to the ground pins on the AD7938/AD7939 as possible. Avoid running digital lines under the device as this couples noise onto the die. The analog ground plane should be allowed to run under the AD7938/ AD7939 to avoid noise coupling. The power supply lines to the AD7938/AD7939 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line.

Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board.

In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side.

Good decoupling is also important. All analog supplies should be decoupled with 10 µF tantalum capacitors in parallel with

0.1 µF capacitors to GND. To achieve the best from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The

0.1 µF capacitors should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types or surface-mount types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE

The lands on the chip scale package (CP-32) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at

1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. The user should connect the printed circuit board thermal pad to AGND.

EVALUATING THE AD7938/AD7939 PERFORMANCE

The recommended layout for the AD7938/AD7939 is outlined in the evaluation board documentation. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the evaluation board controller. The evaluation board controller can be used in conjunction with the AD7938/ AD7939 evaluation board, as well as many other ADI evaluation boards ending in the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7938/AD7939.

The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7938/ AD7939. The software and documentation are on the CD that ships with the evaluation board.

Rev. 0 | Page 30 of 32

AD7938/AD7939

OUTLINE DIMENSIONS

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING PLANE

0.08

0.60 MAX

EXPOSED

PAD

(BOTTOM VIEW)

5.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

4.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARITY

Figure 46. 32-Lead Lead Frame Chip Scale Package [LFCSP]

5 mm × 5 mm Body (CP-32-3)

Dimensions shown in millimeters

1.20

0.75

0.60

0.45

MAX

9.00 SQ

PIN 1

TOP VIE W

(PINS DOWN)

3.50 REF

7.00 SQ

PIN 1 INDICATOR

3.45

3.30 SQ

3.15

0.25 MIN

1.05

1.00

0.95

0.15

0.05

ROTATED 90° CCW

VIEW A

0.20

0.09 7°

3.5° 0°

0.08 MAX COPLANARITY

0.80

BSC

SEATING PLANE

0° MIN

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026ABA

Figure 47. 32-Lead Thin Plastic Quad Flat Package [TQFP]

(SU-32-2)

Dimensions shown in millimeters

0.45

0.37

0.30

Rev. 0 | Page 31 of 32

AD7938/AD7939

ORDERING GUIDE

Model Temperature Range Linearity Error (LSB)

AD7938BCP –40°C to +85°C ±1 32-Lead LFCSP CP-32-3 AD7938BCP-REEL –40°C to +85°C ±1 32-Lead LFCSP CP-32-3 AD7938BCP-REEL7 –40°C to +85°C ±1 32-Lead LFCSP CP-32-3 AD7938BCPZ

–40°C to +85°C ±1 32-Lead LFCSP CP-32-3 AD7938BCPZ-REEL72 –40°C to +85°C ±1 32-Lead LFCSP CP-32-3 AD7938BSU –40°C to +85°C ±1 32-Lead TQFP SU-32-2 AD7938BSU-REEL –40°C to +85°C ±1 32-Lead TQFP SU-32-2 AD7938BSU-REEL7 –40°C to +85°C ±1 32-Lead TQFP SU-32-2 AD7938BSUZ2 –40°C to +85°C ±1 32-Lead TQFP SU-32-2 AD7938BSUZ-REEL72 –40°C to +85°C ±1 32-Lead TQFP SU-32-2 EVAL-AD7938CB

Evaluation Board AD7939BCP –40°C to +85°C ±1 32-Lead LFCSP CP-32-3 AD7939BCP-REEL –40°C to +85°C ±1 32-Lead LFCSP CP-32-3 AD7939BCP-REEL7 –40°C to +85°C ±1 32-Lead LFCSP CP-32-3 AD7939BCPZ2 –40°C to +85°C ±1 32-Lead LFCSP CP-32-3 AD7939BCPZ-REEL72 –40°C to +85°C ±1 32-Lead LFCSP CP-32-3 AD7939BSU –40°C to +85°C ±1 32-Lead TQFP SU-32-2 AD7939BSU-REEL –40°C to +85°C ±1 32-Lead TQFP SU-32-2 AD7939BSU-REEL7 –40°C to +85°C ±1 32-Lead TQFP SU-32-2 AD7939BSUZ2 –40°C to +85°C ±1 32-Lead TQFP SU-32-2 AD7939BSUZ-REEL72 –40°C to +85°C ±1 32-Lead TQFP SU-32-2 EVAL-AD7939CB3 Evaluation Board EVAL-CONTROL BRD2

Controller Board

Linearity error here refers to integral linearity error.

Z = Pb-free part.

This can be used as a standalone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes.

Evaluation Board Controller. This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB

designators. The following needs to be ordered to obtain a complete evaluation kit: the ADC Evaluation Board (e.g. EVAL AD7938CB), the EVAL-CONTROL BRD2 and a 12 V ac transformer. See relevant evaluation board technical note for more details.

Package Descriptions Package Option

D03715–0–10/04(0)

Rev. 0 | Page 32 of 32

Analog Devices AD7938 9 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

AD7938—SPECIFICATIONS

AD7939—SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTION

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

ON-CHIP REGISTERS

CONTROL REGISTER

SEQUENCER OPERATION

SHADOW REGISTER

CIRCUIT INFORMATION

CONVERTER OPERATION

ADC TRANSFER FUNCTION

TYPICAL CONNECTION DIAGRAM

ANALOG INPUT STRUCTURE

ANALOG INPUTS

Single-Ended Mode

Differential Mode

Driving Differential Inputs

Using an Op Amp Pair

Pseudo-Differential Mode

ANALOG INPUT SELECTION

Traditional Multichannel Operation (SEQ = SHDW = 0)

Consecutive Sequence (SEQ = 1, SHDW = 1)

REFERENCE SECTION

Digital Inputs

PARALLEL INTERFACE

Reading Data from the AD7938/AD7939

Writing Data to the AD7938/AD7939

POWER MODES OF OPERATION

Normal Mode (PM1 = PM0 = 0)

Autoshutdown (PM1 = 0; PM0 = 1)

Autostandby (PM1 = 1; PM0 = 0)

Full Shutdown Mode (PM1 =1; PM0 = 1)

POWER VS. THROUGHPUT RATE

MICROPROCESSOR INTERFACING

AD7938/AD7939 to ADSP-21xx Interface

AD7938/AD7939 to ADSP-21065L Interface

AD7938/AD7939 to 80C186 Interface

APPLICATION HINTS

GROUNDING AND LAYOUT

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE

EVALUATING THE AD7938/AD7939 PERFORMANCE

OUTLINE DIMENSIONS

ORDERING GUIDE