Analog Devices AD7938 9 Datasheet

V

8-Channel, 1.5 MSPS, 12-Bit and 10-Bit

FEATURES

Fast throughput rate: 1.5 MSPS
Specified for V
Low power

6 mW max at 1.5 MSPS with 3 V supplies

13.5 mW max at 1.5 MSPS with 5 V supplies
8 analog input channels with a sequencer
Software configurable analog inputs

8-channel single-ended inputs
4-channel fully differential inputs
4-channel pseudo-differential inputs

7-channel pseudo-differential inputs
Accurate on-chip 2.5 V reference
±0.2% max @ 25°C, 25 ppm/°C max
70 dB SINAD at 50 kHz input frequency
No pipeline delays
High speed parallel interface—word/byte modes
Full shutdown mode: 2 µA max
32-lead LFCSP and TQFP package

GENERAL DESCRIPTION

The AD7938/AD7939 are 12-bit and 10-bit, high speed, low
power, successive approximation (SAR) ADCs. The parts
operate from a single 2.7 V to 5.25 V power supply and feature
throughput rates up to 1.5 MSPS. The parts contain a low noise,
wide bandwidth, differential track-and-hold amplifier that can
handle input frequencies up to 50 MHz.

The AD7938/AD7939 feature eight analog input channels with
a channel sequencer that allow a preprogrammed selection of
channels to be converted sequentially. These parts can operate
with either single-ended, fully differential, or pseudo­differential analog inputs.

The conversion process and data acquisition are controlled
using standard control inputs that allow easy interfacing with
microprocessors and DSPs. The input signal is sampled on the
falling edge of

this point.

The AD7938/AD7939 have an accurate on-chip 2.5 V reference
that can be used as the reference source for the analog-to-digital
conversion. Alternatively, this pin can be overdriven to provide
an external reference.

of 2.7 V to 5.25 V

DD

CONVST

and the conversion is also initiated at

Parallel ADCs with a Sequencer

AD7938/AD7939

FUNCTIONAL BLOCK DIAGRAM

V

AGND

DD

V

REFIN/

REFOUT

VIN0

VIN7

SEQUENCER

PARALLEL INTERFACE/CONTROL REGISTER

DB0 DB11

I/P

MUX

2.5V

VREF

T/H

Figure 1.

These parts use advanced design techniques to achieve very
low power dissipation at high throughput rates. They also
feature flexible power management options. An on-chip control
register allows the user to set up different operating conditions,
including analog input range and configuration, output coding,
power management, and channel sequencing.

PRODUCT HIGHLIGHTS

1. High throughput with low power consumption.

2. Eight analog inputs with a channel sequencer.

3. Accurate on-chip 2.5 V reference.

4. Software configurable analog inputs. Single-ended, pseudo-

differential, or fully differential analog inputs that are
software selectable.

5. Single-supply operation with V

function allows the parallel interface to connect directly to
3 V, or 5 V processor systems independent of V

6. No pipeline delay.

7. Accurate control of the sampling instant via a

input and once off conversion control.

AD7938/AD7939

12-/10-BIT
SAR ADC

AND

CONTROL

CS DGNDRD WR W/B

function. The V

DRIVE

CLKIN
CONVST
BUSY

V

DRIVE

DRIVE

.

DD

CONVST

03715-0-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD7938/AD7939

TABLE OF CONTENTS

AD7938—Specifications.................................................................. 3

Typical C o n nect i o n D iagram ................................................... 18

AD7939—Specifications.................................................................. 5

Timing Specifications....................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Description .............................. 9

Te r m in o l o g y .................................................................................... 11

Typical Performance Characteristics........................................... 13

On-Chip Registers.......................................................................... 15

Control Register.......................................................................... 15

Sequencer Operation .................................................................16

Shadow Register.......................................................................... 16

Circuit Information........................................................................ 17

Converter Operation.................................................................. 17

ADC Transfer Function............................................................. 17

Analog Input Structure.............................................................. 18

Analog Inputs.............................................................................. 19

Analog Input Selection.............................................................. 21

Reference Section ....................................................................... 22

Parallel Interface ......................................................................... 24

Power Modes of Operation ....................................................... 27

Power vs. Throughput Rate ....................................................... 28

Microprocessor Interfacing....................................................... 28

Application Hints ........................................................................... 30

Grounding and Layout .............................................................. 30

PCB Design Guidelines for Chip Scale Package .................... 30

Evaluating the AD7938/AD7939 Performance...................... 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 32

REVISION HISTORY

10/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD7938/AD7939

AD7938—SPECIFICATIONS

VDD = V
T

MAX

Table 1.

Parameter B Version

DYNAMIC PERFORMANCE FIN = 50 kHz sine wave

Signal-to-Noise + Distortion (SINAD)
68 dB min Single-ended mode
Signal-to-Noise Ratio (SNR)2 71 dB min Differential mode
69 dB min Single-ended mode
Total Harmonic Distortion (THD)2 −73 dB max −85 dB typ, differential mode

−70 dB max −80 dB typ, single-ended mode
Peak Harmonic or Spurious Noise (SFDR)2 −73 dB max −82 dB typ
Intermodulation Distortion (IMD)2 fa = 30 kHz, fb = 50 kHz

Channel-to-Channel Isolation −85 dB typ FIN = 50 kHz, F
Aperture Delay2 5 ns typ
Aperture Jitter2 72 ps typ

Full Power Bandwidth2 50 MHz typ @ 3 dB
10 MHz typ @ 0.1 dB
DC ACCURACY

Resolution 12 Bits

Integral Nonlinearity2 ±1 LSB max Differential mode

±1.5 LSB max Single-ended mode

Differential Nonlinearity2

Single-Ended and Pseudo-Differential Input Straight binary output coding

Fully Differential Input Twos complement output coding

ANALOG INPUT

Single-Ended Input Range 0 to V

Pseudo-Differential Input Range: V

Fully Differential Input Range: V

DC Leakage Current

Input Capacitance 45 pF typ When in track

10 pF typ When in hold

= 2.7 V to 5.25 V, internal/external V

DRIVE

= 2.5 V, unless otherwise noted, F

REF

= 25.5 MHz, F

CLKIN

= 1.5 MSPS; TA = T

SAMPLE

, unless otherwise noted.

1

2

70 dB min Differential mode

Unit Test Conditions/Comments

Second-Order Terms −86 dB typ
Third-Order Terms −90 dB typ

= 300 kHz

NOISE

Differential Mode ±0.95 LSB max Guaranteed no missed codes to 12 bits
Single-Ended Mode −0.95/+1.5 LSB max Guaranteed no missed codes to 12 bits

Offset Error2 ±6 LSB max
Offset Error Match2 ±1 LSB max
Gain Error2 ±3 LSB max
Gain Error Match2 ±1 LSB max

Positive Gain Error3 ±3 LSB max
Positive Gain Error Match2 ±1 LSB max
Zero-Code Error2 ±6 LSB max
Zero-Code Error Match2 ±1 LSB max
Negative Gain Error2 ±3 LSB max
Negative Gain Error Match2 ±1 LSB max

or 0 to 2 × V

REF

0 to V

IN+

V

IN−

or 2 × V

REF

REF

−0.3 to +0.7 V typ VDD = 3 V

V RANGE bit = 0, or RANGE bit =1, respectively

REF

V RANGE bit = 0, or RANGE bit =1, respectively

−0.3 to +1.8 V typ VDD = 5 V
and V

IN+

V

and V

4

IN+

IN−

IN−

VCM ± V
VCM ± V

/2 V VCM = common-mode voltage3 = V

REF

REF

V VCM = V

±1 µA max

REF

, V

IN+

or V

must remain within GND/V

IN−

REF

/2

MIN

to

DD

Rev. 0 | Page 3 of 32

AD7938/AD7939

Parameter B Version

1

Unit Test Conditions/Comments

REFERENCE INPUT/OUTPUT

V

Input Voltage

REF

5

2.5 V ±1% for specified performance
DC Leakage Current ±1 µA max
V

Input Impedance 10 kΩ typ

REF

V

Output Voltage 2.5 V ±0.2% max @ 25°C

REFOUT

V

Temperature Coefficient 25 ppm/°C max 5 ppm/°C typ

REFOUT

V

Noise 10 µV typ 0.1 Hz to 10 Hz bandwidth

REF

130 µV typ 0.1 Hz to 1 MHz bandwidth
V

Output Impedance 10 Ω typ

REF

V

Input Capacitance 15 pF typ When in track

REF

25 pF typ When in hold

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V

INH

INL

2.4 V min

0.8 V max
Input Current, IIN ±5 µA max Typically 10 nA, VIN = 0 V or V
Input Capacitance, C

4

IN

10 pF max

LOGIC OUTPUTS

Output High Voltage, V

OH

Output Low Voltage, VOL 0.4 V max I

2.4 V min I

SOURCE

= 200 µA

SINK

= 200 µA

Floating-State Leakage Current ±3 µA max
Floating-State Output Capacitance4 10 pF max
Output Coding CODING bit = 0

Straight (Natural) Binary

Twos Complement

CODING bit = 1

CONVERSION RATE

Conversion Time t2 + 13 t

CLK

ns
Track-and-Hold Acquisition Time 125 ns max Full-scale step input
Throughput Rate 1.5 MSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 V min/max
V

2.7/5.25 V min/max

DRIVE

6

I

DD

Digital I/PS = 0 V or V

DRIVE

Normal Mode (Static) 0.8 mA typ VDD = 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) 2.7 mA max VDD = 4.75 V to 5.25 V

2.0 mA max VDD = 2.7 V to 3.6 V

Autostandby Mode 0.3 mA typ F

= 100 kSPS, VDD = 5 V

SAMPLE

160 µA typ (Static)
Full/Autoshutdown Mode (Static) 2 µA max SCLK on or off

Power Dissipation

Normal Mode (Operational) 13.5 mW max VDD = 5 V
6 mW max VDD = 3 V
Autostandby Mode (Static) 800 µW typ VDD = 5 V
480 µW typ VDD = 3 V
Full/Autoshutdown Mode (Static) 10/6 µW max VDD = 5 V/3 V

1

Temperature ranges as follows: B Versions: −40°C to +85°C.

2

See the Terminology section.

3

For full common-mode range, see Fi and . gure 25 Figure 26

4

Sample tested during initial release to ensure compliance.

5

This device is operational with an external reference in the range 0.1 V to VDD. See the Reference Section for more information.

6

Measured with a midscale dc analog input.

DRIVE

Rev. 0 | Page 4 of 32

AD7938/AD7939

AD7939—SPECIFICATIONS

VDD = V
T

MAX

Table 2.

Parameter B Version

DYNAMIC PERFORMANCE FIN = 50 kHz sine wave

Signal-to-Noise + Distortion (SINAD)
60 dB min Single-ended mode
Total Harmonic Distortion (THD)2 −70 dB max
Peak Harmonic or Spurious Noise (SFDR)2 −72 dB max
Intermodulation Distortion (IMD)2 fa = 30 kHz, fb = 50 kHz

Channel-to-Channel Isolation −75 dB typ FIN = 50 kHz, F
Aperture Delay2 5 ns typ
Aperture Jitter2 72 ps typ

Full Power Bandwidth2 50 MHz typ @ 3 dB
10 MHz typ @ 0.1 dB
DC ACCURACY

Resolution 10 Bits

Integral Nonlinearity2 ±0.5 LSB max

Differential Nonlinearity2 ±0.5 LSB max Guaranteed no missed codes to 10 bits

Single-Ended and Pseudo-Differential Input Straight binary output coding

Fully Differential Input Twos complement output coding

ANALOG INPUT

Single-Ended Input Range 0 to V

Pseudo-Differential Input Range: V

Fully Differential Input Range: V

DC Leakage Current

Input Capacitance 45 pF typ When in track

10 pF typ When in hold
REFERENCE INPUT/OUTPUT

V

REF

DC Leakage Current4 ±1 µA max

V

REFOUT

V

REFOUT

V

REF

130 µV typ 0.1 Hz to 1 MHz bandwidth

V

REF

= 2.7 V to 5.25 V, internal/external V

DRIVE

= 2.5V, unless otherwise noted, F

REF

= 25.5 MHz, F

CLKIN

= 1.5 MSPS; TA = T

SAMPLE

, unless otherwise noted.

1

2

61 dB min Differential mode

Unit Test Conditions/Comments

Second-Order Terms −86 dB typ
Third-Order Terms −90 dB typ

= 300 kHz

NOISE

Offset Error2 ±2 LSB max
Offset Error Match2 ±0.5 LSB max
Gain Error2 ±1.5 LSB max
Gain Error Match2 ±0.5 LSB max

Positive Gain Error2 ±1.5 LSB max
Positive Gain Error Match2 ±0.5 LSB max
Zero-Code Error2 ±2 LSB max
Zero-Code Error Match2 ±0.5 LSB max
Negative Gain Error2 ±1.5 LSB max
Negative Gain Error Match2 ±0.5 LSB max

or 0 to 2 × V

REF

0 to V

IN+

V

IN−

or 2 × V

REF

REF

−0.3 to +0.7 V typ VDD = 3 V

V RANGE bit = 0, or RANGE bit =1, respectively

REF

V RANGE bit = 0, or RANGE bit =1, respectively

−0.3 to +1.8 V typ VDD = 5 V

Input Voltage

and V

IN+

V

and V

4

5

IN+

IN−

IN−

VCM ± V
VCM ± V

/2 V VCM = common-mode voltage3 = V

REF

REF

V VCM = V

REF

, V

or V

IN+

±1 µA max

2.5 V ±1% for specified performance

must remain within GND/V

IN−

Output Voltage 2.5 V ±0.2% max @ 25°C
Temperature Coefficient 40 ppm/°C typ

Noise 10 µV typ 0.1 Hz to 10 Hz bandwidth

Output Impedance 10 Ω typ

REF

/2

MIN

to

DD

Rev. 0 | Page 5 of 32

AD7938/AD7939

Parameter B Version

V

Input Capacitance 15 pF typ When in track

REF

1

Unit Test Conditions/Comments

25 pF typ When in hold

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V

INH

INL

2.4 V min

0.8 V max
Input Current, IIN ±5 µA max Typically 10 nA, VIN = 0 V or V
Input Capacitance, C

4

IN

10 pF max

LOGIC OUTPUTS

Output High Voltage, V

OH

Output Low Voltage, VOL 0.4 V max I

2.4 V min I

= 200 µA

SOURCE

= 200 µA

SINK

Floating-State Leakage Current ±3 µA max
Floating-State Output Capacitance4 10 pF max
Output Coding CODING bit = 0

Straight (Natural) Binary

Twos Complement

CODING bit =1

CONVERSION RATE

Conversion Time t2 + 13 t

ns

CLK

Track-and-Hold Acquisition Time 125 ns max Full-scale step input
Throughput Rate 1.5 MSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 V min/max
V

2.7/5.25 V min/max

DRIVE

6

I

DD

Digital I/PS = 0 V or V

DRIVE

Normal Mode (Static) 0.8 mA typ VDD = 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) 2.7 mA max VDD = 4.75 V to 5.25 V

2.0 mA max VDD = 2.7 V to 3.6 V
Autostandby Mode 0.3 mA typ F

= 100 kSPS, VDD = 5 V

SAMPLE

160 µA typ (Static)
Full/Autoshutdown Mode (Static) 2 µA max SCLK on or off

Power Dissipation

Normal Mode (Operational) 13.5 mW max VDD = 5 V
6 mW max VDD = 3 V
Autostandby Mode (Static) 800 µW typ VDD = 5 V
480 µW typ VDD = 3 V
Full/Autoshutdown Mode (Static) 10/6 µW max VDD = 5 V/3 V

1

Temperature ranges as follows: B Versions: −40°C to +85°C.

2

See the Terminology section.

3

For full common-mode range see Fig and . ure 25 Figure 26

4

Sample tested during initial release to ensure compliance.

5

This device is operational with an external reference in the range 0.1 V to VDD. See the Reference Section for more details.

6

Measured with a midscale dc analog input.

DRIVE

Rev. 0 | Page 6 of 32

AD7938/AD7939

TIMING SPECIFICATIONS

VDD = V
T

MAX

Table 3.

Limit at T
Parameter AD7938 AD7939 Unit Description

f

CLKIN

25.5 25.5 MHz max
t

QUIET

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

2

t

13

3

t

14

50 50 ns max
t

15

t

16

t

17

t

18

t

19

t

20

t

21

t

22

1

Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given above are with a 25 pF load capacitance (see , Figure 36, Figure 37, and ).

2

The time required for the output to cross 0.4 V or 2.4 V.

3

t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or

discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.

= 2.7 V to 5.25 V, internal/external V

DRIVE

, unless otherwise noted.

, T

MIN

50 50 kHz min

30 30 ns min

10 10 ns min
15 15 ns min
50 50 ns min CLKIN Falling Edge to BUSY Rising Edge.

0 0 ns min
0 0 ns min
10 10 ns min
10 10 ns min
10 10 ns min
10 10 ns min New Data Valid before Falling Edge of BUSY.
0 0 ns min
0 0 ns min
30 30 ns min
30 30 ns max
3 3 ns min

0 0 ns min
0 0 ns min
10 10 ns min Minimum Time between Reads/Writes.
0 0 ns min
10 10 ns min
40 40 ns max CLKIN Falling Edge to BUSY Falling Edge.

15.7 15.7 ns min CLKIN Low Pulse Width.

7.8 7.8 ns min CLKIN High Pulse Width.

1

MAX

= 2.5 V, unless otherwise noted; F

REF

= 25.5 MHz, F

CLKIN

= 1.5 MSPS; TA = T

SAMPLE

Minimum time between end of read and start of next conversion, i.e., time from
when the data bus goes into three-state until the next falling edge of

CONVST.
CONVST Pulse Width.
CONVST Falling Edge to CLKIN Falling Edge Setup Time.

CS to WR Setup Time.
CS to WR Hold Time.
WR Pulse Width.
Data Setup Time before
Data Hold after

WR.

WR.

CS to RD Setup Time.
CS to RD Hold Time.
RD Pulse Width.
Data Access Time after
Bus Relinquish Time after
Bus Relinquish Time after
HBEN to
HBEN to

HBEN to
HBEN to

RD Setup Time.
RD Hold Time.

WR Setup Time.
WR Hold Time.

Figure 35 Figure 38

RD.

RD.
RD.

MIN

to

Rev. 0 | Page 7 of 32

AD7938/AD7939

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to AGND/DGND −0.3 V to +7 V
V

to AGND/DGND −0.3 V to VDD +0.3 V

DRIVE

Analog Input Voltage to AGND −0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to +7 V
V

to V

DRIVE

DD

Digital Output Voltage to DGND −0.3 V to V
V

to AGND −0.3 V to VDD + 0.3 V

REFIN

−0.3 V to VDD + 0.3 V
+ 0.3 V

DRIVE

AGND to DGND −0.3 V to + 0.3 V
Input Current to Any

Pin Except Supplies

1

±10 mA

Operating Temperature Range

Commercial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 108.2°C/W (LFCSP)
121°C/W (TQFP)
θJC Thermal Impedance 32.71°C/W (LFCSP)
45°C/W (TQFP)
Lead Temperature, Soldering

Reflow Temperature

255°C

(10 sec to 30 sec)

ESD 1.5 kV

1

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 8 of 32

AD7938/AD7939

PIN CONFIGURATION AND FUNCTION DESCRIPTION

7

6

5

4

3

2

IN

IN

IN

V

V

V

27

26

25

VIN1

24

VIN0

23

V

22

REFIN/VREFOUT

21

AGND

20

CS

19

RD
WR

18

17

CONVST

14

15

16

BUSY

CLKIN

03715-0-006

CS, RD, and WR. The logic high/low

input. When reading from the AD7939, the two LSBs

DRIVE

CS, RD, and WR.

input.

DRIVE

th

rising edge of SCLK, see Figure 35.

. The frequency of the master clock input therefore determines the

2

CONVST is used to power-up the

RD read while CS is low.

Table 5. Pin Function Description

Pin No Mnemonic Function

1 to 8 DB0 to DB7

Data Bits 0 to 7. Three-state parallel digital I/O pins that provide the conversion result and also allow the control
and shadow registers to be programmed. These pins are controlled by
voltage levels for these pins are determined by the V
(DB0 and DB1) are always 0 and the LSB of the conversion result is available on DB2.

9 V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of
the AD7938/AD7939 operates. This pin should be decoupled to DGND. The voltage at this pin may be different
to that at V

10 DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7938/AD7939. This pin
should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same
potential and must not be more than 0.3 V apart, even on a transient basis.

11 DB8/HBEN

Data Bit 8/High Byte Enable. When W/

CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte

by
of data being written to or read from the AD7938/AD7939 is on DB0 to DB7. When HBEN is high, the top four

bits of the data being written to or read from the AD7938/AD7939 are on DB0 to DB3. When reading from the
device, DB4 to DB6 of the high byte contains the ID of the channel to which the conversion result corresponds
(see the channel address bits in Table 9). When writing to the device, DB4 to DB7 of the high byte must be all 0s.
Note that when reading from the AD7939, the two LSBs of the low byte are 0s, and the remaining 6 bits,
conversion data.

12 to 14 DB9 to DB11

Data Bits 9 to 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the
control and shadow registers to be programmed in word mode. These pins are controlled by
The logic high/low voltage levels for these pins are determined by the V

15 BUSY

Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the
falling edge of
the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track
mode just prior to the falling edge of BUSY on the 13

16 CLKIN

Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7938/AD7939 takes 13 clock cycles + t
conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock.

17

CONVST Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track

to hold mode on the falling edge of
down, when operating in autoshutdown or autostandby modes, a rising edge on
device.

18
19

WR Write Input. Active low logic input used in conjunction with CS to write data to the internal registers.
RD Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion

result is placed on the data bus following the falling edge of

DD

IN

IN

IN

V

V

V

30

29

28

TOP VIEW

(Not to Scale)

11

12

DB9

DB1013DB11

DB8/HBEN

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

W/B32V

31

PIN 1

1

IDENTIFIER

2

3

4

5

6

7

8

AD7938/AD7939

9

10

DRIVE

DGND

V

Figure 2. Pin Configuration

but should never exceed VDD by more than 0.3 V.

DD

B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled

CONVST and stays high for the duration of the conversion. Once the conversion is complete and

CONVST and the conversion process is initiated at this point. Following power-

Rev. 0 | Page 9 of 32

AD7938/AD7939

Pin No Mnemonic Function

20

21 AGND

22 V

23 to 30 VIN0 to VIN7

31 VDD

32

CS Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data

to the internal registers.
Analog Ground. This is the ground reference point for all analog circuitry on the AD7938/AD7939. All analog

input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND
voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient
basis.

REFIN/VREFOUT

Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC.
The nominal internal reference voltage is 2.5 V and this appears at this pin. This pin can be overdriven by an
external reference. The input voltage range for the external reference is 0.1 V to V
taken to ensure that the analog input range does not exceed V

Analog Input 0 to Analog Input 7. Eight analog input channels that are multiplexed into the on-chip track-and­hold. The analog inputs can be programmed to be eight single-ended inputs, four fully differential pairs, four
pseudo-differential pairs, or seven pseudo-differential inputs by setting the MODE bits in the control register
appropriately (see Table 9). The analog input channel to be converted can either be selected by writing to the
address bits (ADD2 to ADD0) in the control register prior to the conversion or the on-chip sequencer can be
used. The SEQ and SHDW bits in conjunction with the address bits in the control register allow the shadow
register to be programmed. The input range for all input channels can either be 0 V to V
the coding can be binary or twos complement, depending on the states of the RANGE and CODING bits in the
control register. Any unused input channels should be connected to AGND to avoid noise pickup.

Power Supply Input. The V
to AGND with a 0.1 µF capacitor and a 10 µF tantalum capacitor.

B Word/Byte Input. When this input is logic high, data is transferred to and from the AD7938/AD7939 in 12-bit/10-

W/

bit words on Pins DB0/DB2 to DB11. When this pin is logic low, byte transfer mode is enabled. Data and the
channel ID are transferred on Pins DB0 to DB7, and Pin DB8/HBEN assumes its HBEN functionality. Unused data
lines when operating in byte transfer mode should be tied off to DGND.

; however, care must be

+ 0.3 V. See the Reference Section.

DD

range for the AD7938/AD7939 is 2.7 V to 5.25 V. The supply should be decoupled

DD

DD

or 0 V to 2 × V

REF

REF

, and

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