Analog Devices AD7938 6 Datasheet

V

8-Channel, 625 kSPS, 12-Bit

FEATURES

Fast throughput rate: 625 kSPS
Specified for V
Low power

3.6 mW max at 625 kSPS with 3 V supplies

7.5 mW max at 625 kSPS with 5 V supplies
8 analog input channels with a sequencer
Software configurable analog inputs

8-channel single-ended inputs
4-channel fully differential inputs
4-channel pseudo-differential inputs

7-channel pseudo-differential inputs
Accurate on-chip 2.5 V reference
±0.2% max @ 25°C, 25 ppm/°C max
70 dB SINAD at 50 kHz input frequency
No pipeline delays
High speed parallel interface—word/byte modes
Full shutdown mode: 2 µA max
32-lead LFCSP and TQFP package

GENERAL DESCRIPTION

The AD7938-6 is a 12-bit high speed, low power, successive
approximation (SAR) ADC. The part operates from a single

2.7 V to 5.25 V power supply and features throughput rates up
to 625 kSPS. The part contains a low noise, wide bandwidth,
differential track-and-hold amplifier that can handle input
frequencies up to 50 MHz.

The AD7938-6 features eight analog input channels with a
channel sequencer that allows a preprogrammed selection of
channels to be converted sequentially. The part can operate
with either single-ended, fully differential, or pseudo­differential analog inputs.

The conversion process and data acquisition are controlled
using standard control inputs that allow easy interfacing with
microprocessors and DSPs. The input signal is sampled on the
falling edge of

this point.

The AD7938-6 has an accurate on-chip 2.5 V reference that
can be used as the reference source for the analog-to-digital
conversion. Alternatively, this pin can be overdriven to provide
an external reference.

of 2.7 V to 5.25 V

DD

CONVST

and the conversion is also initiated at

Parallel ADCs with a Sequencer

AD7938-6

FUNCTIONAL BLOCK DIAGRAM

V

AGND

DD

V

REFIN/

REFOUT

VIN0

VIN7

SEQUENCER

PARALLEL INTERFACE/CONTROL REGISTER

DB0 DB11

I/P

MUX

2.5V

VREF

T/H

CS DGNDRD WR W/B

Figure 1.

The AD7938-6 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. The part also
features flexible power management options. An on-chip
control register allows the user to set up different operating
conditions, including analog input range and configuration,
output coding, power management, and channel sequencing.

PRODUCT HIGHLIGHTS

1. High throughput with low power consumption.

2. Eight analog inputs with a channel sequencer.

3. Accurate on-chip 2.5 V reference.

4. Software configurable analog inputs. Single-ended, pseudo-

differential, or fully differential analog inputs that are
software selectable.

5. Single-supply operation with V

function allows the parallel interface to connect directly to
3 V, or 5 V processor systems independent of V

6. No pipeline delay.

7. Accurate control of the sampling instant via a

input and once off conversion control.

AD7938-6

12-BIT

SAR ADC

AND

CONTROL

function. The V

DRIVE

CLKIN
CONVST
BUSY

V

DRIVE

DRIVE

.

DD

CONVST

04751-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD7938-6

TABLE OF CONTENTS

AD7938-6—Specifications .............................................................. 3

Analog Input Structure.............................................................. 16

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Function Description................................................................ 7

Terminology ...................................................................................... 9

Typical Performance Characteristics ...........................................11

On-Chip Registers.......................................................................... 13

Control Register.......................................................................... 13

Sequencer Operation ................................................................. 14

Shadow Register.......................................................................... 14

Circuit Information........................................................................ 15

Converter Operation.................................................................. 15

ADC Transfer Function............................................................. 15

Typical Connection Diagram ................................................... 16

Analog Inputs.............................................................................. 17

Analog Input Selection.............................................................. 19

Reference Section ....................................................................... 20

Parallel Interface ......................................................................... 22

Power Modes of Operation ....................................................... 25

Power vs. Throughput Rate....................................................... 26

Microprocessor Interfacing....................................................... 26

Application Hints ........................................................................... 28

Grounding and Layout .............................................................. 28

PCB Design Guidelines for Chip Scale Package .................... 28

Evaluating the AD7938-6 Performance................................... 28

Outline Dimensions....................................................................... 29

Ordering Guide .......................................................................... 30

REVISION HISTORY

10/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD7938-6

SPECIFICATIONS

VDD = V
T

MAX

Table 1.

Parameter B Version1 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE FIN = 50 kHz sine wave

Signal-to-Noise + Distortion (SINAD)2 70 dB min Differential mode

68 dB min Single-ended mode

Signal-to-Noise Ratio (SNR)2 71 dB min Differential mode

69 dB min Single-ended mode

Total Harmonic Distortion (THD)2 −73 dB max −85 dB typ, differential mode

−70 dB max −80 dB typ, single-ended mode

Peak Harmonic or Spurious Noise (SFDR)2 −73 dB max −82 dB typ

Intermodulation Distortion (IMD)2 fa = 30 kHz, fb = 50 kHz

Channel-to-Channel Isolation −85 dB typ FIN = 50 kHz, F

Aperture Delay2 5 ns typ

Aperture Jitter2 72 ps typ

Full Power Bandwidth2 50 MHz typ @ 3 dB
10 MHz typ @ 0.1 dB
DC ACCURACY

Resolution 12 Bits

Integral Nonlinearity2 ±1 LSB max Differential mode

±1.5 LSB max Single-ended mode

Differential Nonlinearity2

Single-Ended and Pseudo-Differential Input Straight binary output coding

Fully Differential Input Twos complement output coding

ANALOG INPUT

Single-Ended Input Range 0 to V

Pseudo-Differential Input Range: V

Fully Differential Input Range: V

DC Leakage Current4 ±1 µA max

Input Capacitance 45 pF typ When in track

10 pF typ When in hold

= 2.7 V to 5.25 V, internal/external V

DRIVE

= 2.5 V, unless otherwise noted, F

REF

= 10 MHz, F

CLKIN

= 625 kSPS; TA = T

SAMPLE

, unless otherwise noted.

Second-Order Terms −86 dB typ
Third-Order Terms −90 dB typ

= 300 kHz

NOISE

Differential Mode ±0.95 LSB max Guaranteed no missed codes to 12 bits
Single-Ended Mode −0.95/+1.5 LSB max Guaranteed no missed codes to 12 bits

Offset Error2 ±6 LSB max
Offset Error Match2 ±1 LSB max
Gain Error2 ±3 LSB max
Gain Error Match2 ±1 LSB max

Positive Gain Error2 ±3 LSB max
Positive Gain Error Match2 ±1 LSB max
Zero-Code Error2 ±6 LSB max
Zero-Code Error Match2 ±1 LSB max
Negative Gain Error2 ±3 LSB max
Negative Gain Error Match2 ±1 LSB max

or 0 to 2 × V

REF

0 to V

IN+

V

−0.3 to +0.7 V typ VDD = 3 V

IN−

or 2 × V

REF

V RANGE bit = 0, or RANGE bit = 1, respectively

REF

V RANGE bit = 0, or RANGE bit = 1, respectively

REF

−0.3 to +1.8 V typ VDD = 3 V

V

IN+

IN+

and V

and V

VCM ± V

IN−

VCM ± V

IN−

/2 V VCM = common-mode voltage3 = V

REF

V VCM = V

REF

REF

, V

IN+

or V

must remain within GND/VDD

IN−

REF

/2

MIN

to

Rev. 0 | Page 3 of 32

AD7938-6

Parameter B Version1 Unit Test Conditions/Comments

REFERENCE INPUT/OUTPUT

V

Input Voltage5 2.5 V ±1% for specified performance

REF

DC Leakage Current ±1 µA max
V

Output Voltage 2.5 V ±0.2% max @ 25°C

REFOUT

V

Temperature Coefficient 25 ppm/°C max 5 ppm/°C typ

REFOUT

V

Noise 10 µV typ 0.1 Hz to 10 Hz bandwidth

REF

130 µV typ 0.1 Hz to 1 MHz bandwidth
V

Output Impedance 10 Ω typ

REF

V

Input Capacitance 15 pF typ When in track

REF

25 pF typ When in hold

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, IIN ±5 µA max Typically 10 nA, VIN = 0 V or V
Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH 2.4 V min I
Output Low Voltage, VOL 0.4 V max I
Floating-State Leakage Current ±3 µA max
Floating-State Output Capacitance4 10 pF max
Output Coding CODING bit = 0

CONVERSION RATE

Conversion Time t2 + 13 t
Track-and-Hold Acquisition Time 125 ns max Full-scale step input
Throughput Rate 625 kSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 V min/max
V

2.7/5.25 V min/max

DRIVE

6

I

Digital I/PS = 0 V or V

DD

Normal Mode (Static) 0.8 mA typ VDD = 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) 1.5 mA max VDD = 4.75 V to 5.25 V

1.2 mA max VDD = 2.7 V to 3.6 V
Autostandby Mode 0.3 mA typ F
160 µA typ (Static)
Full/Autoshutdown Mode (Static) 2 µA max SCLK on or off

Power Dissipation

Normal Mode (Operational) 7.5 mW max VDD = 5 V

3.6 mW max VDD = 3 V
Autostandby Mode (Static) 800 µW typ VDD = 5 V
480 µW typ VDD = 3 V
Full/Autoshutdown Mode (Static) 10/6 µW max VDD = 5 V/3 V

1

Temperature ranges as follows: B Versions: −40°C to +85°C.

2

See the Terminology section.

3

For full common-mode range, see Fi and . gure 25 Figure 26

4

Sample tested during initial release to ensure compliance.

5

This device is operational with an external reference in the range 0.1 V to VDD. See the R for more information. eference Section

6

Measured with a midscale dc analog input.

2.4 V min

INH

0.8 V max

INL

4

10 pF max

IN

= 200 µA

SOURCE

= 200 µA

SINK

Straight (Natural) Binary

Twos Complement

ns

CLK

CODING bit = 1

= 100 kSPS, VDD = 5 V

SAMPLE

DRIVE

DRIVE

Rev. 0 | Page 4 of 32

AD7938-6

TIMING SPECIFICATIONS1

VDD = V
T

MAX

Table 2.

Limit at T
Parameter AD7938-6 Unit Description

f

50 kHz min

CLKIN

10 MHz max
t

QUIET

t1 10 ns min
t2 15 ns min
t3 50 ns min CLKIN Falling Edge to BUSY Rising Edge.

t4 0 ns min
t5 0 ns min
t6 10 ns min
t7 10 ns min
t8 10 ns min
t9 10 ns min New Data Valid before Falling Edge of BUSY.
t10 0 ns min
t11 0 ns min
t12 30 ns min

2

t

30 ns max

13

3

t

3 ns min

14

50 ns max
t15 0 ns min
t16 0 ns min
t17 10 ns min Minimum Time between Reads/Writes.

t18 0 ns min
t19 10 ns min
t20 40 ns max CLKIN Falling Edge to BUSY Falling Edge.

t21 15.7 ns min CLKIN Low Pulse Width.
t22 7.8 ns min CLKIN High Pulse Width.

1

Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given above are with a 25 pF load capacitance (see , , , and ).

2

The time required for the output to cross 0.4 V or 2.4 V.

3

t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or

discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.

= 2.7 V to 5.25 V, internal/external V

DRIVE

, unless otherwise noted.

, T

MIN

MAX

30 ns min

= 2.5 V, unless otherwise noted; F

REF

= 10MHz, F

CLKIN

= 625 kSPS; TA = T

SAMPLE

Minimum time between end of read and start of next conversion, i.e., time from
when the data bus goes into three-state until the next falling edge of

CONVST.
CONVST Pulse Width.
CONVST Falling Edge to CLKIN Falling Edge Setup Time.

CS to WR Setup Time.
CS to WR Hold Time.
WR Pulse Width.
Data Setup Time before
Data Hold after

WR.

WR.

CS to RD Setup Time.
CS to RD Hold Time.
RD Pulse Width.
Data Access Time after
Bus Relinquish Time after
Bus Relinquish Time after
HBEN to
HBEN to

HBEN to
HBEN to

RD Setup Time.
RD Hold Time.

WR Setup Time.
WR Hold Time.

RD.

RD.
RD.

Figure 35 Figure 36 Figure 37 Figure 38

MIN

to

Rev. 0 | Page 5 of 32

AD7938-6

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to AGND/DGND −0.3 V to +7 V
V

to AGND/DGND −0.3 V to VDD +0.3 V

DRIVE

Analog Input Voltage to AGND −0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to +7 V
V

to VDD −0.3 V to VDD + 0.3 V

DRIVE

Digital Output Voltage to DGND −0.3 V to V
V

to AGND −0.3 V to VDD + 0.3 V

REFIN

DRIVE

+ 0.3 V

AGND to DGND −0.3 V to + 0.3 V
Input Current to Any

Pin Except Supplies

1

±10 mA

Operating Temperature Range

Commercial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 108.2°C/W (LFCSP)
121°C/W (TQFP)
θJC Thermal Impedance 32.71°C/W (LFCSP)
45°C/W (TQFP)
Lead Temperature, Soldering

Reflow Temperature

255°C

(10 sec to 30 sec)

ESD 1.5 kV

1

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 32

AD7938-6

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

7

6

5

4

3

2

IN

IN

IN

V

V

V

27

26

25

VIN1

24

VIN0

23

V

22

REFIN/VREFOUT

21

AGND

20

CS

19

RD
WR

18

17

CONVST

14

15

16

BUSY

CLKIN

04751-006

CS, RD, and WR. The logic high/low

input.

DRIVE

CS, RD, and WR.

input.

DRIVE

th

rising edge of SCLK, see Figure 35.

CONVST is used to

RD read while CS is low.

Table 4. Pin Function Description

Pin No Mnemonic Function

1 to 8 DB0 to DB7

Data Bits 0 to 7. Three-state parallel digital I/O pins that provide the conversion result and also allow the control
and shadow registers to be programmed. These pins are controlled by
voltage levels for these pins are determined by the V

9 V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of
the AD7938-6 operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that

but should never exceed VDD by more than 0.3 V.

at V

DD

10 DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7938-6. This pin should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.

11 DB8/HBEN

Data Bit 8/High Byte Enable. When W/

CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte

by
of data being written to or read from the AD7938-6 is on DB0 to DB7. When HBEN is high, the top four bits of
the data being written to or read from the AD7938-6 are on DB0 to DB3. When reading from the device, DB4
to DB6 of the high byte contains the ID of the channel to which the conversion result corresponds (see the
channel address bits in Table 8). When writing to the device, DB4 to DB7 of the high byte must be all 0s.

12 to 14 DB9 to DB11

Data Bits 9 to 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the
control and shadow registers to be programmed in word mode. These pins are controlled by
The logic high/low voltage levels for these pins are determined by the V

15 BUSY

Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the
falling edge of
the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track
mode just prior to the falling edge of BUSY on the 13

16 CLKIN

Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for
the AD7938-6 takes 13 clock cycles + t
conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock.

17

CONVST Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from

track to hold mode on the falling edge of
power-down, when operating in autoshutdown or autostandby modes, a rising edge on
power-up the device.

18
19

WR Write Input. Active low logic input used in conjunction with CS to write data to the internal registers.
RD Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion

result is placed on the data bus following the falling edge of

20

CS Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data

to the internal registers.

DD

IN

IN

IN

V

V

V

30

29

28

AD7938-6

TOP VIEW

(Not to Scale)

11

12

DB9

DB1013DB11

DB8/HBEN

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

W/B32V

31

PIN 1

1

IDENTIFIER

2

3

4

5

6

7

8

9

10

DRIVE

DGND

V

Figure 2. Pin Configuration

B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled

CONVST and stays high for the duration of the conversion. Once the conversion is complete and

. The frequency of the master clock input therefore determines the

2

CONVST and the conversion process is initiated at this point. Following

Rev. 0 | Page 7 of 32

AD7938-6

Pin No Mnemonic Function

21 AGND

22 V

REFIN/VREFOUT

23 to 30 VIN0 to VIN7

31 VDD

32

B Word/Byte Input. When this input is logic high, data is transferred to and from the AD7938-6 in 12-bit words on

W/

Analog Ground. This is the ground reference point for all analog circuitry on the AD7938-6. All analog
input signals and any external reference signal should be referred to this AGND voltage. The AGND and
DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.

Reference Input/Output. This pin is connected to the internal reference and is the reference source for the
ADC. The nominal internal reference voltage is 2.5 V and this appears at this pin. This pin can be overdriven by
an external reference. The input voltage range for the external reference is 0.1 V to V
taken to ensure that the analog input range does not exceed V

Analog Input 0 to Analog Input 7. Eight analog input channels that are multiplexed into the on-chip track-and­hold. The analog inputs can be programmed to be eight single-ended inputs, four fully differential pairs, four
pseudo-differential pairs, or seven pseudo-differential inputs by setting the MODE bits in the control register
appropriately (see Table 8). The analog input channel to be converted can either be selected by writing to the
address bits (ADD2 to ADD0) in the control register prior to the conversion or the on-chip sequencer can be
used. The SEQ and SHDW bits in conjunction with the address bits in the control register allow the shadow
register to be programmed. The input range for all input channels can either be 0 V to V
the coding can be binary or twos complement, depending on the states of the RANGE and CODING bits in the
control register. Any unused input channels should be connected to AGND to avoid noise pickup.

Power Supply Input. The V
AGND with a 0.1 µF capacitor and a 10 µF tantalum capacitor.

Pins DB0 to DB11. When this pin is logic low, byte transfer mode is enabled. Data and the channel ID are
transferred on Pins DB0 to DB7, and Pin DB8/HBEN assumes its HBEN functionality. Unused data lines when
operating in byte transfer mode should be tied off to DGND.

; however, care must be

+ 0.3 V. See the Reference Section.

DD

range for the AD7938-6 is 2.7 V to 5.25 V. The supply should be decoupled to

DD

DD

or 0 V to 2 × V

REF

REF

, and

Rev. 0 | Page 8 of 32

AD7938-6

TERMINOLOGY

Integral Nonlinearity

This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (00 . . .000) to
(00 . . . 001) f rom the ideal, i.e., AGND + 1 LSB.

Offset Error Match

This is the difference in offset error between any two channels.

Gain Error

This is the deviation of the last code transition (111 . . .110) to
(111 . . . 111) from the ideal (i.e., V
error has been adjusted out.

Gain Error Match

This is the difference in gain error between any two channels.

Zero-Code Error

This applies when using the twos complement output coding
option, in particular to the 2 × V

biased about the V

+V

REF

REFIN

mid scale transition (all 0s to all 1s) from the ideal V

REF

.

i.e., V

Zero-Code Error Match

This is the difference in zero-code error between any two
channels.

Positive Gain Error

This applies when using the twos complement output coding
option, in particular to the 2 × V

biased about the V

+V

REF

REFIN

code transition (011. . .110) to (011 .. . 111) from the ideal (i.e.,

− 1 LSB) after the zero-code error has been adjusted out.

+V

REF

Positive Gain Error Match

This is the difference in positive gain error between any two
channels.

– 1 LSB) after the offset

REF

input range with −V

REF

REF

to

point. It is the deviation of the

voltage,

IN

input range with −V

REF

REF

to

point. It is the deviation of the last

Negative Gain Error

This applies when using the twos complement output coding
option, in particular to the 2 × V

biased about the V

+V

REF

point. It is the deviation of the first

REF

input range with −V

REF

REF

to

code transition (100 . . . 000) to (100 . . . 001) from the ideal
(i.e., −V

+ 1 LSB) after the zero-code error has been

REFIN

adjusted out.

Negative Gain Error Match

This is the difference in negative gain error between any two
channels.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full­scale sine wave signal to all seven nonselected input channels
and applying a 50 kHz signal to the selected channel. The
channel-to-channel isolation is defined as the ratio of the power
of the 50 kHz signal on the selected channel to the power of the
noise signal on the unselected channels that appears in the FFT
of this channel. The noise frequency on the unselected channels
varies from 40 kHz to 740 kHz. The noise amplitude is at 2 ×

, while the signal amplitude is at 1 × V

V

REF

REF

.

Power Supply Rejection Ratio (PSRR)

PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC V

supply of frequency fS. The frequenc y

DD

of the noise varies from 1 kHz to 1 MHz.

PSRR (dB) = 10log(Pf/Pf

Pf is the power at frequency f in the ADC output; Pf

power at frequency f

in the ADC output.

S

)

S

is the

S

Common-Mode Rejection Ratio (CMRR)

CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the common-mode voltage of V
frequency f

as

S

CMRR (dB) = 10log (Pf/Pf

)

S

IN+

and V

Pf is the power at frequency f in the ADC output; Pf
power at frequency f

in the ADC output.

S

of

IN−

is the

S

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns to track mode at the end
of conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.

Rev. 0 | Page 9 of 32

AD7938-6

Signal-to-(Noise + Distortion) Ratio (SINAD)

This is the measured ratio of signal-to-(noise + distortion) at
the output of the A/D converter. The signal is the rms amplitude
of the fundamental. Noise is the sum of all nonfundamental
signals up to half the sampling frequency (f
The ratio is dependent on the number of quantization levels in
the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal-to-(noise +
distortion) ratio for an ideal N-bit converter with a sine wave
input is given by

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

Thus, for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7938-6, it is defined as

()

THD

where V
V

is the rms amplitude of the fundamental and V2, V3,

1

, V5, and V6 are the rms amplitudes of the second through the

4

20logdB

−=

sixth harmonics.

/2), excluding dc.

S

V

1

22222

VVVVV

++++

65432

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f

/2 and excluding dc) to the rms value of the

S

fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those
for which neither m nor n are equal to 0. For example, the
second-order terms include (fa + fb) and (fa − fb), while the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb)
and (fa − 2fb).

The AD7938-6 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second-order terms are usually distanced
in frequency from the original sine waves while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dBs.

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