±0.2% maximum @ 25°C, 25 ppm/°C maximum
69 dB SINAD at 50 kHz input frequency
No pipeline delays
High speed parallel interface—word/byte modes
Full shutdown mode: 2 µA maximum
32-lead LFCSP and TQFP packages
of 2.7 V to 5.25 V
DD
Parallel ADCs with a Sequencer
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The AD7938/AD7939 are 12-bit and 10-bit, high speed, low
power, successive approximation (SAR) analog-to-digital
converters (ADCs). The parts operate from a single 2.7 V to
5.25 V power supply and feature throughput rates up to
1.5 MSPS. The parts contain a low noise, wide bandwidth,
differential track-and-hold amplifier that can handle input
frequencies up to 50 MHz.
These parts use advanced design techniques to achieve very
low power dissipation at high throughput rates. They also
feature flexible power management options. An on-chip control
register allows the user to set up different operating conditions,
including analog input range and configuration, output coding,
power management, and channel sequencing.
PRODUCT HIGHLIGHTS
The AD7938/AD7939 feature eight analog input channels with
a channel sequencer that allows a preprogrammed selection of
channels to be converted sequentially. These parts can operate
with either single-ended, fully differential, or pseudo
differential analog inputs.
The conversion process and data acquisition are controlled
using standard control inputs that allow easy interfacing with
microprocessors and DSPs. The input signal is sampled on the
CONVST
and the conversion is also initiated at
falling edge of
this point.
The AD7938/AD7939 have an accurate on-chip 2.5 V reference
that can be used as the reference source for the analog-to-digital
conversion. Alternatively, this pin can be overdriven to provide
an external reference.
1. High throughput with low power consumption.
2. Eight analog inputs with a channel sequencer.
3. Accurate on-chip 2.5 V reference.
4. Single-ended, pseudo differential, or fully differential
analog inputs that are software selectable.
5. Single-supply operation with V
function. The V
DRIVE
DRIVE
function allows the parallel interface to connect directly to
3 V or 5 V processor systems independent of V
Information furnishe d by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
AD7938/AD7939 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Circuit Information ........................................................................ 18
DC Leakage Current4 ±1 µA max
Input Capacitance 45 pF typ When in track
10 pF typ When in hold
VCM ± V
IN−
VCM ± V
IN−
/2 V VCM = common-mode voltage3 = V
REF
V VCM = V
REF
Rev. C | Page 3 of 36
, V
or V
REF
must remain within GND/VDD
IN+
IN−
/2
REF
AD7938/AD7939 Data Sheet
LOGIC OUTPUTS
Output High Voltage, VOH
2.4
V min
I
= 200 µA
CONVERSION RATE
Conversion Time
t2 + 13 t
ns
Track-and-Hold Acquisition Time
125
ns max
Full-scale step input
Normal Mode (Operational)
2.7
mA max
VDD = 4.75 V to 5.25 V
Autostandby Mode
0.3
mA typ
f
= 100 kSPS, VDD = 5 V
Parameter Value1 Unit Test Conditions/Comments
REFERENCE INPUT/OUTPUT
V
Input Voltage5 2.5 V ±1% for specified performance
REF
DC Leakage Current ±1 µA max
V
Output Voltage 2.5 V ±0.2% max @ 25°C
REFOUT
V
Temperature Coefficient 25 ppm/°C max
REFOUT
5 ppm/°C typ
V
Noise 10 µV typ 0.1 Hz to 10 Hz bandwidth
REF
130 µV typ 0.1 Hz to 1 MHz bandwidth
V
Output Impedance 10 Ω typ
REF
V
Input Capacitance 15 pF typ When in track
REF
25 pF typ When in hold
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, IIN ±5 µA max Typically 10 nA, VIN = 0 V or V
Input Capacitance, C
Output Low Voltage, VOL 0.4 V max I
Floating-State Leakage Current ±3 µA max
Floating-State Output Capacitance4
Output Coding Straight (natural) binary CODING bit = 0
Twos complement CODING bit = 1
2.4 V min
INH
0.8 V max
INL
4
IN
10 pF typ
10 pF typ
SOUR CE
= 200 µA
SINK
DRIVE
CLKIN
80 ns typ Sine wave input
Throughput Rate 1.5 MSPS max
POWER REQUIREMENTS
VDD 2.7/5.25 V min/max
V
2.7/5.25 V min/max
DRIVE
6
I
Digital inputs = 0 V or V
DD
Normal Mode (Static) 0.8 mA typ VDD = 2.7 V to 5.25 V, SCLK on or off
2.0 mA max VDD = 2.7 V to 3.6 V
SAMPLE
160 µA typ Static
Full/Autoshutdown Mode (Static) 2 µA max SCLK on or off
Power Dissipation
Normal Mode (Operational) 13.5 mW max VDD = 5 V
6 mW max VDD = 3 V
Autostandby Mode (Static) 800 µW typ VDD = 5 V
480 µW typ VDD = 3 V
Full/Autoshutdown Mode (Static) 10 µW max VDD = 5 V
6 µW max VDD = 3 V
1
Temperature range is −40°C to +85°C.
2
See the Terminology section.
3
For full common-mode range, see Figure 26 and Figure 27.
4
Sample tested during initial release to ensure compliance.
5
This device is operational with an external reference in the range of 0.1 V to VDD. See the Reference section for more information.
6
Measured with a midscale dc analog input.
DRIVE
Rev. C | Page 4 of 36
Data Sheet AD7938/AD7939
Peak Harmonic or Spurious Noise (SFDR)2
−72
dB max
Offset Error2
±2
LSB max
Pseudo Differential Input Range
AD7939 SPECIFICATIONS
VDD = V
T
= T
A
Table 3.
Parameter Value1 Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 50 kHz sine wave
Signal-to-Noise and Distortion (SINAD)2 61 dB min Differential mode
60 dB min Single-ended mode
Total Harmonic Distortion (THD)2 −70 dB max
Channel-to-Channel Isolation −75 dB typ fIN = 50 kHz, f
Aperture Delay2 5 ns typ
Aperture Jitter2 72 ps typ
Full Power Bandwidth2 50 MHz typ @ 3 dB
10 MHz typ @ 0.1 dB
DC ACCURACY
Resolution 10 Bits
Integral Nonlinearity2 ±0.5 LSB max
Differential Nonlinearity2 ±0.5 LSB max Guaranteed no missed codes to 10 bits
Single-Ended and Pseudo Differential Input Straight binary output coding
= 2.7 V to 5.25 V, internal/external V
DRIVE
MIN
to T
, unless otherwise noted.
MAX
= 2.5 V, unless otherwise noted, f
REF
CLKIN
Second-Order Terms −86 dB typ
Third-Order Terms −90 dB typ
= 25.5 MHz, f
SAMPLE
= 300 kHz
NOISe
= 1.5 MSPS;
Offset Error Match2 ±0.5 LSB max
Gain Error2 ±1.5 LSB max
Gain Error Match2 ±0.5 LSB max
Fully Differential Input Twos complement output coding
Positive Gain Error2 ±1.5 LSB max
Positive Gain Error Match2 ±0.5 LSB max
Zero-Code Error2 ±2 LSB max
Zero-Code Error Match2 ±0.5 LSB max
Negative Gain Error2 ±1.5 LSB max
Negative Gain Error Match2 ±0.5 LSB max
ANALOG INPUT
Single-Ended Input Range 0 to V
0 to 2 × V
V
0 to V
IN+
0 to 2 × V
V
−0.3 to +0.7 V typ VDD = 3 V
IN−
V RANGE bit = 0
REF
V RANGE bit = 1
REF
V RANGE bit = 0
REF
V RANGE bit =1
REF
−0.3 to +1.8 V typ VDD = 5 V
Fully Differential Input Range
V
V
IN+
IN+
and V
and V
VCM ± V
IN−
VCM ± V
IN−
/2 V VCM = common-mode voltage3 = V
REF
V VCM = V
REF
REF
, V
IN+
or V
must remain within GND/VDD
IN−
DC Leakage Current4 ±1 µA max
Input Capacitance 45 pF typ When in track
10 pF typ When in hold
REF
/2
Rev. C | Page 5 of 36
AD7938/AD7939 Data Sheet
V
Temperature Coefficient
25
ppm/°C max
Input Low Voltage, V
0.8
V max
Conversion Time
t2 + 13 t
ns
Power Dissipation
Full/Autoshutdown Mode (Static)
10
µW max
VDD = 5 V
Parameter Value1 Unit Test Conditions/Comments
REFERENCE INPUT/OUTPUT
V
Input Voltage5 2.5 V ±1% for specified performance
REF
DC Leakage Current4 ±1 µA max External reference applied to pin
V
Output Voltage 2.5 V ±0.2% max @ 25°C
REFOUT
REFOUT
5 ppm/°C typ
V
Noise 10 µV typ 0.1 Hz to 10 Hz bandwidth
REF
130 µV typ 0.1 Hz to 1 MHz bandwidth
V
Output Impedance 10 Ω typ
REF
V
Input Capacitance 15 pF typ When in track
REF
25 pF typ When in hold
LOGIC INPUTS
Input High Voltage, V
Input Current, IIN ±5 µA max Typically 10 nA, VIN = 0 V or V
Input Capacitance, C
LOGIC OUTPUTS
Output High Voltage, VOH 2.4 V min I
Output Low Voltage, VOL 0.4 V max I
Floating-State Leakage Current ±3 µA max
Floating-State Output Capacitance4 10 pF typ
Output Coding Straight (natural) binary CODING bit = 0
Twos complement CODING bit =1
CONVERSION RATE
Track-and-Hold Acquisition Time 125 ns max Full-scale step input
80 ns typ Sine wave input
Throughput Rate 1.5 MSPS max
POWER REQUIREMENTS
VDD 2.7/5.25 V min/max
V
2.7/5.25 V min/max
DRIVE
6
I
Digital inputs = 0 V or V
DD
Normal Mode (Static) 0.8 mA typ VDD = 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) 2.7 mA max VDD = 4.75 V to 5.25 V
2.0 mA max VDD = 2.7 V to 3.6 V
Autostandby Mode 0.3 mA typ f
160 µA typ Static
Full/Autoshutdown Mode (Static) 2 µA max SCLK on or off
2.4 V min
INH
INL
4
10 pF typ
IN
CLKIN
= 200 µA
SOURCE
= 200 µA
SINK
= 100 kSPS, VDD = 5 V
SAMPLE
DRIVE
DRIVE
Normal Mode (Operational) 13.5 mW max VDD = 5 V
6 mW max VDD = 3 V
Autostandby Mode (Static) 800 µW typ VDD = 5 V
480 µW typ VDD = 3 V
1
Temperature range is −40°C to +85°C.
2
See the Terminology section.
3
For full common-mode range, see Figure 26 and Figure 27.
4
Sample tested during initial release to ensure compliance.
5
This device is operational with an external reference in the range of 0.1 V to VDD. See the Reference section for more details.
6
Measured with a midscale dc analog input.
6 µW max VDD = 3 V
Rev. C | Page 6 of 36
Data Sheet AD7938/AD7939
t2
15
15
ns min
falling edge to CLKIN falling edge setup time.
t18
0
0
ns min
HBEN to WR setup time.
TIMING SPECIFICATIONS
VDD = V
T
MAX
Table 4.
Limit at T
Parameter1 AD7938 AD7939 Unit Description
2
f
CLKIN
25.5 25.5 MHz max
t
30 30 ns min Minimum time between end of read and start of next conversion; in other words, time
QUIET
t1 10 10 ns min
t3 50 50 ns max CLKIN falling edge to BUSY rising edge.
t4 0 0 ns min
t5 0 0 ns min
t6 10 10 ns min
t7 10 10 ns min Data setup time before WR.
t8 10 10 ns min Data hold after WR.
t9 10 10 ns min New data valid before falling edge of BUSY.
t10 0 0 ns min
t11 0 0 ns min
t12 30 30 ns min
t
133
4
t
3 3 ns min Bus relinquish time after RD.
14
50 50 ns max Bus relinquish time after RD.
t15 0 0 ns min HBEN to RD setup time.
t16 0 0 ns min HBEN to RD hold time.
t17 10 10 ns min Minimum time between reads/writes.
= 2.7 V to 5.25 V, internal/external V
DRIVE
= 2.5 V, unless otherwise noted; f
REF
, unless otherwise noted.
, T
MIN
MAX
700 700 kHz min CLKIN frequency.
from when the data bus goes into three-state until the next falling edge of
CONVST
pulse width.
CONVST
to WR setup time.
CS
to WR hold time.
CS
pulse width.
WR
to RD setup time.
CS
to RD hold time.
CS
pulse width.
RD
30 30 ns max Data access time after RD.
= 25.5 MHz, f
CLKIN
= 1.5 MSPS; TA = T
SAMPLE
CONVST
MIN
to
.
t19 10 10 ns min HBEN to WR hold time.
t20 40 40 ns max CLKIN falling edge to BUSY falling edge.
t21 15.7 15.7 ns min CLKIN low pulse width.
t22 7.8 7.8 ns min CLKIN high pulse width.
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
1.6 V. All timing specifications given above are with a 25 pF load capacitance (see Figure 36, Figure 37, Figure 38, and Figure 39).
2
Minimum CLKIN for specified performance, with slower SCLK frequencies performance specifications apply typically.
3
The time required for the output to cross 0.4 V or 2.4 V.
4
t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
discharging the 25 pF capacitor. This means that the time, t
bus loading.
, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
14
= t
= 5 ns (10% to 90% of VDD) and timed from a voltage level of
RISE
FALL
Rev. C | Page 7 of 36
AD7938/AD7939 Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
VDD to AGND/DGND −0.3 V to +7 V
V
to AGND/DGND −0.3 V to VDD + 0.3 V
DRIVE
Analog Input Voltage to AGND −0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to +7 V
V
to VDD −0.3 V to VDD + 0.3 V
DRIVE
Digital Output Voltage to DGND −0.3 V to V
V
to AGND −0.3 V to VDD + 0.3 V
REFIN
DRIVE
+ 0.3 V
AGND to DGND −0.3 V to +0.3 V
Input Current to Any Pin
Except Supplies
1
±10 mA
Operating Temperature Range
Commercial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 108.2°C/W (LFCSP)
121°C/W (TQFP)
θJC Thermal Impedance 32.71°C/W (LFCSP)
45°C/W (TQFP)
Lead Temperature, Soldering
Reflow Temperature (10 sec to 30 sec) 255°C
ESD 1.5 kV
1
Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. C | Page 8 of 36
Data Sheet AD7938/AD7939
03715-006
PIN 1
INDICATOR
1DB0
2DB1
3DB2
4DB3
5DB4
6DB5
7DB6
8DB7
24 V
IN
1
23 V
IN
0
22 V
REFIN
/V
REFOUT
21 AGND
20 CS
19 RD
18 WR
17 CONVST
9V
DRIVE
10DGND
11DB8/HBEN
12DB9
13DB10
14DB11
15BUSY
16CLKIN
32
W/B
31
V
DD
30
V
IN
7
29
V
IN
6
28
V
IN
5
27
V
IN
4
26
V
IN
3
25
V
IN
2
TOP VIEW
(Not to S cale)
AD7938/AD7939
NOTES
1. THE EXP OSED PAD IS L OCATED ON THE UNDE RS IDE OF
THE PACKAGE. CONNECT THE E P AD TO THE GROUND
PLANE OF THE PCB USING MULTIPLE VIAS.
03715-050
1
2
3
4
5
6
7
8
DB1
DB2
DB3
DB6
DB5
DB4
DB0
DB7
23
V
IN
0
22
V
REFIN
/V
REFOUT
21
AGND
18
WR
19
RD
20
CS
24
V
IN
1
17
CONVST
PIN 1
9
V
DRIVE
10
DGND
11
DB8/HBEN
12
DB9
13
DB10
14
DB11
15
BUSY
16
CLKIN
32
W/B
31
V
DD
30
V
IN
7
29
V
IN
6
28
V
IN
5
27
V
IN
4
26
V
IN
3
25
V
IN
2
AD7938/AD7939
TOP VIEW
(Not to Scale)
12 to
DB9 to
Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and allow the
and stays high for the duration of the conversion. Once the conversion is complete and the
20 CS
Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data to
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. LFCSP Pin Configuration
Figure 3. TQFP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 8 DB0 to DB7 Data Bit 0 to Data Bit 7. Three -state parallel digital I/O pins that provide the conversion result and allow the control
and shadow registers to be programmed. These pins are controlled by
levels for these pins are determined by the V
input. When reading from the AD7939, the two LSBs (DB0 and
DRIVE
CS, RD
DB1) are always 0 and the LSB of the conversion result is available on DB2.
9 V
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the
DRIVE
AD7938/AD7939 operates. This pin should be decoupled to DGND. The voltage at this pin can be different to that
but should never exceed VDD by more than 0.3 V.
at V
DD
10 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7938/AD7939. This pin should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
11 DB8/HBEN Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled by
, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data
CS, RD
being written to or read from the AD7938/AD7939 is on DB0 to DB7. When HBEN is high, the top four bits of the
data being written to or read from the AD7938/AD7939 are on DB0 to DB3. When reading from the device, DB4 to
DB6 of the high byte contains the ID of the channel to which the conversion result corresponds (see the channel
address bits in Table 10). When writing to the device, DB4 to DB7 of the high byte must be all 0s. Note that when
reading from the AD7939, the two LSBs of the low byte are 0s, and the remaining six bits are conversion data.
14
DB11
control and shadow registers to be programmed in word mode. These pins are controlled by CS, RD, and WR. The
logic high/low voltage levels for these pins are determined by the V
DRIVE
15 BUSY Busy Output. Logic output that indicates the status of the conversion. The BUSY output goes high following the
falling edge of
CONVST
result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just
prior to the falling edge of BUSY on the 13
16 CLKIN Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
17
18
19
CONVST
Write Input. Active low logic input used in conjunction with CS to write data to the internal registers.
WR
Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion
RD
AD7938/AD7939 takes 13 clock cycles + t
conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock.
Conversion Start Input. A falling edge on
mode to hold mode on the falling edge of
power-down, when operating in autoshutdown or autostandby modes, a rising edge on
the device.
result is placed on the data bus following the falling edge of
the internal registers.
th
rising edge of CLKIN. See Figure 36.
. The frequency of the master clock input therefore determines the
2
is used to initiate a conversion. The track-and-hold goes from track
CONVST
and the conversion process is initiated at this point. Following
CONVST
read while CS is low.
RD
Rev. C | Page 9 of 36
, and WR. The logic high/low voltage
input.
is used to power up
CONVST
AD7938/AD7939 Data Sheet
decoupled to AGND with a 470 nF capacitor. This pin can be overdriven by an external reference. The input voltage
SHDW bits in conjunction with the address bits in the control register allow the shadow register to be
Exposed Pad. The exposed pad is located on the underside of the package. Connect the EPAD to the ground plane
Pin No. Mnemonic Description
21 AGND Analog Ground. This is the ground reference point for all analog circuitry on the AD7938/AD7939. All analog input
signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages
should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
22 V
23 to
REFIN/VREFOUT
VIN0 to VIN7 Analog Input 0 to Analog Input 7. Eight analog input channels that are multiplexed into the on-chip track-and-
30
31 VDD Power Supply Input. The VDD range for the AD7938/AD7939 is 2.7 V to 5.25 V. The supply should be decoupled to
32 W/B Word/Byte Input. When this input is logic high, data is transferred to and from the AD7938/AD7939 in 12-bit/10-bit
E PA D
Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC.
The nominal internal reference voltage is 2.5 V, which appears at this pin. It is recommended that this pin is
range for the external reference is 0.1 V to VDD; however, care must be taken to ensure that the analog input range
does not exceed V
+ 0.3 V. See the Reference section.
DD
hold. The analog inputs can be programmed to be eight single-ended inputs, four fully differential pairs, four
pseudo differential pairs, or seven pseudo differential inputs by setting the MODE bits in the control register
appropriately (see Table 10
). The analog input channel to be converted can either be selected by writing to the
address bits (ADD2 to ADD0) in the control register prior to the conversion or the on-chip sequencer can be used.
The SEQ and
programmed. The input range for all input channels can either be 0 V to V
or 0 V to 2 × V
REF
, and the coding can
REF
be binary or twos complement, depending on the states of the RANGE and CODING bits in the control register.
Any unused input channels should be connected to AGND to avoid noise pickup.
AGND with a 0.1 µF capacitor and a 10 µF tantalum capacitor.
words on the DB0/DB2 to DB11 pins. When this pin is logic low, byte transfer mode is enabled. Data and the
channel ID are transferred on Pin DB0 to Pin DB7, and Pin DB8/HBEN assumes its HBEN functionality. Unused data
lines when operating in byte transfer mode should be tied off to DGND.
of the PCB using multiple vias.
Rev. C | Page 10 of 36
Data Sheet AD7938/AD7939
–
–
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
60
100mV p -p SINE WAVE ON VDDAND/OR V
NO DECOUPLING
DIFFERENTIAL/SINGLE-ENDED MODE
–70
–80
–90
PSRR (dB)
–100
–110
–120
INT REF
EXT REF
102106104108101010
SUPPLY RIPPLE FREQUENCY (kHz)
DRIVE
Figure 4. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
03715-007
0
–10
–20
–30
–40
–50
–60
AMPLI TUDE (d B)
–70
–80
–90
–100
–110
0
100
200
300
FREQUENCY (kHz)
Figure 7. AD7938 FFT @ V
4096 POINT FFT
V
=5V
DD
F
=1.5MSPS
SAMPLE
F
= 49.62kHz
IN
SINAD = 70.94dB
THD = –90.09dB
DIFFERENTIAL MODE
400
500
= 5 V
DD
600
03715-009
700
70
INTERNAL/EXTERNAL REFERENCE
V
=5V
DD
–75
–80
–85
ISOLATION (dB)
–90
–95
0100400200300600500800700
NOISE FREQUENCY (kHz)
Figure 5. AD7938 Channel-to-Channel Isolation
80
70
60
50
SINAD (dB)
40
30
F
=1.5MSPS
SAMPLE
RANGE = 0 TO V
DIFFERENTIAL MODE
20
0100400200 3006005001000700 800 900
REF
FREQUENCY (kHz)
VDD=5V
VDD=3V
1.0
0.8
0.6
0.4
0.2
0
–0.2
DNL ERROR (LS B)
–0.4
–0.6
–0.8
03715-021
–1.0
050020001000 15003000250040003500
Figure 8. AD7938 Typical DNL @ V
1.0
0.8
0.6
0.4
0.2
0
–0.2
INL ERROR (L S B)
–0.4
–0.6
–0.8
03715-008
–1.0
050020001000 15003000250040003500
CODE
CODE
VDD=5V
DIFFERENTIAL MODE
= 5 V
DD
VDD=5V
DIFFERENTIAL MODE
03715-010
03715-011
Figure 6. AD7938 SINAD vs. Analog Input Frequency
Figure 9. AD7938 Typical INL @ V
= 5 V
DD
for Various Supply Voltages
Rev. C | Page 11 of 36
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