Analog Devices AD7936 35 pra Datasheet

PRELIMINARY TECHNICAL DATA

AD7936/AD7935

VDD

12-/10-BIT

SAR ADC

AND

CONTROL

PARALLEL INTERFACE/CONTROL REGISTER

VIN0

CS RD WR

W/B

SEQUENCER

VIN7

I/P MUX

T/H

REFIN

REFOUT

CLKIN

CONVST

BUSY

AGND

VDRIVE

DGND

2.5 V VREF

8-Channel, 1.5 MSPS, 12- & 10-Bit

FEATURES Fast Throughput Rate: 1.5 MSPS Specified for V Low Power:

8 mW max at 1.5 MSPS with 3V Supplies

16 mW max at 1.5 MSPS with 5V Supplies 8 Analog Input Channels with a Sequencer Software Configurable Analog Inputs:

8-Channel Single Ended Inputs

4-Channel Fully Differential Inputs

4-Channel Pseudo Differential Inputs

7-Channel Pseudo Differential Inputs Accurate On-chip 2.5 V Reference Wide Input Bandwidth:

70dB SNR at 50kHz Input Frequency No Pipeline Delays High Speed Parallel Interface operating in

Byte format Full Shutdown Mode: 1 28-Lead TSSOP Package

of 2.7 V to 5.25 V

µA max

Parallel ADCs with a Sequencer

AD7936/AD7935

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The AD7936/AD7935 are 12- & 10-bit, high speed, low power, successive approximation (SAR) ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1.5 MSPS. The parts contain a low noise, wide bandwidth, differential track/hold amplifier that can handle input frequencies up to 20MHz.

The AD7936/AD7935 feature 8 analog input channels with a channel sequencer to allow a pre-programmed selection of channels to be converted sequentially. These parts can operate with either Single-ended, Fully Differential or Pseudo Differential analog inputs. The analog input configuration is chosen by setting the relevant bits in the on-chip Control Register.

The conversion process and data acquisition are controlled using standard control inputs allowing easy interfacing to Microprocessors and Dsps. The input signal is sampled on the falling edge of CONVST and the conversion is also initiated at this point.

The AD7936/AD7935 has an accurate on-chip 2.5 V reference that can be used as the reference source for the analog to digital conversion. Alternatively, this pin can be overdriven to provide an external reference in the range 100mV to 3.5 V.

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

These parts use advanced design techniques to achieve very low power dissipation at high throughput rates. They also feature flexible power management options.

An on-chip Control register allows the user to set up different operating conditions including analog input range and configuration, output coding, power management and channel sequencing.

PRODUCT HIGHLIGHTS

1. High Throughput with Low Power Consumption The AD7936/AD7935 offer 1.5 MSPS throughput with 8mW power consumption at V

= 3V.

2. Eight Analog Inputs with a Channel Sequencer.

A sequence of input channels can be selected, through which the AD7936/AD7935 will continuously cycle and convert on.

3. Accurate on-chip 2.5 V reference.

4. Software Configurable Analog Inputs

Single-Ended, Pseudo Differential or Fully Differential analog inputs that are software selectable.

5. Single-supply Operation with V

DRIVE

Function.

The AD7936/AD7935 operates from a single 2.7 V to

5.25 V supply. The V

function allows the parallel

DRIVE

interface to connect directly to either 3V or 5 V proces sor systems independent of V

6. No Pipeline Delay The parts feature a standard successive-approximation ADC with accurate control of the sampling instant via a CONVST input and once off conversion control.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2003

PRELIMINARY TECHNICAL DATA

AD7936–SPECIFICATIONS

( VDD = V F

CLKIN

=2.7 V to 5.25V, V

DRIVE

= 20MHz, F

= 1.5 MSPS; TA = T

SAMPLE

REFIN/VREFOUT

= 2.5V unless otherwise noted,

to T

MIN

, unless otherwise noted.)

MAX

Parameter BVersion1 Units Test Conditions/Comments

DYNAMIC PERFORMANCE F

Signal to Noise + Distortion

(SINAD) Signal to Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise -75 dB max -82dB typ

(SFDR)

Intermodulation Distortion (IMD)

70 dB min

-75 dB max -80dB typ

=50kHz Sine Wave

fa = 40.1kHz, fb = 51.5kHz Second Order Terms -85 dB typ Third Order Terms -85 dB typ

Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation

-8 2 dB typ

Full Power Bandwidth 20 MHz typ @ 3 dB

2.5 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 12 Bits Integral Nonlinearity Differential Nonlinearity Total Unadjusted Error TBD LSB max

0V to V

Input Range

REF IN

±1 LSB max ±0.95 LSB max Guaranteed No Missed Codes to 12 Bits.

Straight Binary Output Coding Offset Error ±3 LSB max Offset Error Match ±0.5 LSB max Gain Error ±2 LSB max Gain Error Match ±0.6 LSB max

0V to 2 x V

Input Range

REF IN

-V

REF IN

to +V

Biased about V

REF IN

REF

with

Twos Complement Output Coding Positive Gain Error ±2 LSB max Positive Gain Error Match ±0.6 LSB max Zero Code Error ±3 LSB max Zero Code Error Match ±1 LSB max Negative Gain Error ±1 LSB max Negative Gain Error Match ±0.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

REF

0 to 2xV

V RANGE bit in the Control register set to 1. V RANGE bit in the Control register set to 0.

REF

DD/VDRIVE

= 4.75 V to 5.25 V for 0-2V DC Leakage Current ±1 µA max Input Capacitance 20 pF typ

REFERENCE INPUT/OUTPUT

Input Voltage 2.5

REFIN

V ±1% Specified Performance DC Leakage Current ±1 µA max V V V

Output Voltage 2.49/2.51 Vmin/max

REFOUT

Tempco 15 ppm/°C typ

REFOUT

Output Impedance 10 Ω

REF

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

Input Capacitance, C

0.7xV

INH

0.3xV

INL

DRIVE

V min

V max

± 1 µA max Typically 10 nA, V 10 pF max

= 0 V or V

DRIVE

LOGIC OUTPUTS

Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ±10 µA max Floating-State Output Capacitance

-0.2 V min I

DRIVE

0.4 V max I

10 pF max

= 200 µA; VDD = 2.7 V to 5.25 V

SOURCE

=200µA

SINK

Output Coding Straight (Natural) Binary CODING bit in the control register set to 1.

2s Complement CODING bit in the control register set to 0.

REF

range

–2–

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PRELIMINARY TECHNICAL DATA

AD7936–SPECIFICATIONS

Parameter B Version

Units Test Conditions/Comments

CONVERSION RATE Conversion Time 12 CLKIN

cycles (max)

Track/Hold Acquisition Time 300 ns max Sine Wave Input

325 ns max Full-Scale Step Input

Throughput Rate 1.5 MSPS max Conversion Time + Acquisition Time

POWER REQUIREMENTS

DRIVE

Normal Mode(Static) 0.5 mA typ V Normal Mode (Operational) 3.2 mA max V

2.7/5.25 V min/max

2.6 mA max V

Digital I/Ps = 0V or V

= 2.7V to 5.25V.

= 4.75V to 5.25V.

= 2.7V to 3.6V.

DRIVE

Auto StandBy Mode 1.55 mA typ

90 µA max (Static)

Auto Shutdown Mode 1 mA typ

1 µA max (Static)

Full Shut-Down Mode 1 µA max SCLK On or Off.

Power Dissipation

Normal Mode (Operational) 16 mW max V

8 mW max V

Auto Standby-Mode (Static) 450 µW max V

270 µW max V

Auto Shutdown-Mode (Static) 5 µW max V

3 µW max V

Full Shutdown-Mode 5 µW max V

= 5V.

= 3V.

= 5V.

= 3V.

= 5V.

= 3V.

= 5V.

3 µW max VDD = 3V.

NOTES

Temperature ranges as follows: B Versions: –40°C to +85°C.

See Terminology Section.

Bit 9 in the Control register set to 1

Bit 9 in the Control register set to 0

This device is operational with an external reference in the range 0.1 V to 3.5 V.

Sample tested @ +25°C to ensure compliance.

Specifications subject to change without notice.

REV. PrA

–3–

PRELIMINARY TECHNICAL DATA

AD7935–SPECIFICATIONS

( VDD = V F

CLKIN

=2.7 V to 5.25V, V

DRIVE

= 20MHz, F

= 1.5MSPS; TA = T

SAMPLE

REFIN/VREFOUT

= 2.5V unless otherwise noted,

to T

MIN

, unless otherwise noted.)

MAX

Parameter B Version1 Units Test Conditions/Comments

DYNAMIC PERFORMANCE F

Signal to Noise + Distortion

(SINAD) Signal to Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise

(SFDR) Intermodulation Distortion (IMD)

60 dB min

-73 dB max

=50kHz Sine Wave

fa = 40.1kHz, fb = 51.5kHz Second Order Terms -75 dB typ Third Order Terms -75 dB typ

Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation

-8 2 dB typ

Full Power Bandwidth 20 MHz typ @ 3 dB

2.5 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 10 Bits Integral Nonlinearity

±0.5 LSB max Differential Nonlinearity ±0.5 LSB max Guaranteed No Missed Codes to 10 Bits. Total Unadjusted Error TBD LSB max

0V to V

Input Range

REF IN

Straight Binary Output Coding Offset Error ±3 LSB max Offset Error Match ±0.5 LSB max Gain Error ±2 LSB max Gain Error Match ±0.6 LSB max

0V to 2 x V

Input Range

REF IN

-V

REF IN

to +V

Biased about V

REF IN

REF

with

Twos Complement Output CodingOffset Positive Gain Error ±2 LSB max Positive Gain Error Match ±0.6 LSB max Zero Code Error ±3 LSB max Zero Code Error Match ±1 LSB max Negative Gain Error ±1 LSB max Negative Gain Error Match ±0.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

REF

0 to 2xV

V RANGE bit in the Control register set to 1. V RANGE bit in the Control register set to 0.

REF

DD/VDRIVE

= 4.75 V to 5.25 V for 0-2V

REF

DC Leakage Current ±1 µA max Input Capacitance 20 pF typ

REFERENCE INPUT/OUTPUT

Input Voltage 2.5

REFIN

V ±1% Specified Performance

DC Leakage Current ±1 µA max

Input Impedance 36 kΩ

REFIN

V V V

Output Voltage 2.49/2.51 Vmin/max

REFOUT

Tempco 15 ppm/°C typ

REFOUT

Output Impedance 10 Ω

REF

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

Input Capacitance, C

0.7xV

INH

0.3xV

INL

DRIVE

V min

V max ± 1 µA max Typically 10 nA, V 10 pF max

= 0 V or V

DRIVE

LOGIC OUTPUTS

Output High Voltage, VOH V Output Low Voltage, V Floating-State Leakage Current ±10 µA max Floating-State Output Capacitance

-0.2 V min I

DRIVE

0.4 V max I

10 pF max

= 200 µA; VDD = 2.7 V to 5.25 V

SOURCE

=200µA

SINK

Output Coding Straight (Natural) Binary CODING bit in the control register set to 1.

2s Complement CODING bit in the control register set to 0.

–4–

REV. PrA

range

PRELIMINARY TECHNICAL DATA

AD7935–SPECIFICATIONS

Parameter B Version

Units Test Conditions/Comments

CONVERSION RATE Conversion Time 10 CLKIN

cycles (max)

Track/Hold Acquisition Time 300 ns max Sine Wave Input

325 ns max Full-Scale Step Input

Throughput Rate 1.5 MSPS max Conversion Time + Acquisition Time

POWER REQUIREMENTS

DRIVE

Normal Mode(Static) 0.5 mA typ V Normal Mode (Operational) 3.2 mA max V

2.7/5.25 V min/max

2.6 mA max V

Digital I/Ps = 0V or V

= 2.7V to 5.25V.

= 4.75V to 5.25V.

= 2.7V to 3.6V.

DRIVE

Auto StandBy Mode 1.55 mA typ

90 µA max (Static)

Auto Shutdown Mode 1 mA typ

1 µA max (Static)

Full Shut-Down Mode 1 µA max SCLK On or Off.

Power Dissipation

Normal Mode (Operational) 16 mW max V

8 mW max V

Auto Standby-Mode (Static) 450 µW max V

270 µW max V

Auto Shutdown-Mode (Static) 5 µW max V

3 µW max V

Full Shutdown-Mode 5 µW max V

= 5V.

= 3V.

= 5V.

= 3V.

= 5V.

= 3V.

= 5V.

3 µW max VDD = 3V.

NOTES

Temperature ranges as follows: B Versions: –40°C to +85°C.

See Terminology Section

Bit 9 in the Control register set to 1

Bit 9 in the Control register set to 0

This device is operational with an external reference in the range 0.1 V to 3.5 V.

Sample tested @ +25°C to ensure compliance.

Specifications subject to change without notice.

REV. PrA

–5–

PRELIMINARY TECHNICAL DATA

AD7936/AD7935

( VDD = V F

CLKIN

TIMING SPECIFICATIONS

Limit at T

MIN

, T

MAX

1,2, 3

Parameter AD7936 AD7935 Units Description

CLKIN

10 10 kHz min 20 20 MHz max

quiet

convert

100 100 ns min Minimum time between conversions TBD TBD ns max Conversion Time 100 100 ns min CONVST pulsewidth 0 0 ns min CS to WR setup time 0 0 ns max CS to WR hold time 55 5 5 ns min WR Pulse Width 10 1 0 ns min Data Setup time before WR 5 1/2 t

CLKIN

5 ns min Data Hold after WR

1/2 t

CLKIN

ns min New data valid before falling edge of BUSY

0 0 ns min CS to RD setup time 0 0 ns max CS to RD hold time 55 50

55 ns min RD Pulse Width

50 ns max Data access time after RD 5 5 ns min Bus relinquish time after RD 40 40 ns max Bus relinquish time after RD

15 1 5 ns min HBEN to RD setup time 5 5 ns min HBEN to RD hold time 60 60 ns min/max Minimum time between Reads 0 0 ns min HBEN to WR setup time 5 5 ns max HBEN to RD setup time

=2.7 V to 5.25V, V

DRIVE

= 20MHz, F

= 1.5MSPS; TA = T

SAMPLE

REFIN/VREFOUT

= 2.5V unless otherwise noted,

to T

MIN

, unless otherwise noted.)

MAX

NOTES

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V level of 1.6 Volts.

See Figure 20 and 21.

All timing specifications given above are with a 25pF load capacitance.

Mark/Space ratio for the SCLK input is 40/60 to 60/40.

The time required for the output to cross 0.4 V or 0.7 x V

t12 is derived form the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t12 quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.

Specifications subject to change without notice.

DRIVE

) and timed from a voltage

–6–

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PRELIMINARY TECHNICAL DATA

AD7936/AD7935

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

VDD to AGND/DGND . . . . . . . . . . . . . . . . . –0.3 V to 7 V

to AGND/DGND . . . . . . . . . . . . . . . –0.3 V to 7 V

DRIVE

Analog Input Voltage to AGND . –0.3 V to V

+ 0.3 V

Digital Input Voltage to DGND . . . . . . . . . . –0.3 V to 7 V

to V

DRIVE

Digital Output Voltage to AGND –0.3 V to V REF

to AGND . . . . . . . . . ........–0.3 V to VDD + 0.3 V

Input Current to Any Pin Except Supplies

. . . . . . . . . . . . . . . . . . . . . . . . .

–0.3 V to VDD + 0.3 V

+ 0.3 V

. . . . ±10 mA

Operating Temperature Range

Commercial (B Version) . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +150°C

Thermal Impedance . . . . . . . . . . . . . 97.9°C/W (TSSOP

Thermal Impedance . . . . . . . . . . . . . . 14°C/W (TSSOP)

Lead Temperature, Soldering

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . +215°C

Infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . +220°C

E S D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV

NOTES

Stresses above those listed under “Absolute Maximum Ratings” may

cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Transient currents of up to 100 mA will not cause SCR latch up.

ORDERING GUIDE

Linearity Package Package

Model Range Error (LSB)1 Option Descriptions

AD7936 -40°C to +85°C ±1 RU-28 TSSOP AD7935 -40°C to +85°C ±1 RU-28 TSSOP EVAL-ADxxxxCB EVAL-CONTROL BRD2

NOTES

Linearity error here refers to integral linearity error.

This can be used as a stand-alone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes.

Evaluation Board Controller. This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards

ending in the CB designators. The following needs to be ordered to obtain a complete evaluation kit: the ADC Evaluation Board (EVALADxxxxCB), the EVAL-CONTROL BRD2 and a 12 V ac transformer. See the ADxxxx evaluation board technical note for more details.

Evaluation Board Controller Board

CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7936/AD7935 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

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