ANALOG DEVICES AD7910 Service Manual

250 kSPS,

FEATURES

Throughput rate: 250 kSPS
Specified for V
Low power

3.6 mW typ at 250 kSPS with 3 V supplies

12.5 mW typ at 250 kSPS with 5 V supplies

Wide input bandwidth

71 dB SNR at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface

SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Standby mode: 1 μA max
6-lead SC70 package
8-lead MSOP package

APPLICATIONS

Battery-powered systems

Personal digital assistants

Medical instruments

Mobile communications
Instrumentation and control systems
Data acquisition systems
High speed modems
Optical sensors

GENERAL DESCRIPTION

of 2.35 V to 5.25 V

DD

10-/12-Bit ADCs in 6-Lead SC70

AD7910/AD7920

FUNCTIONAL BLOCK DIAGRAM

V

DD

10-/12-BIT

V

T/H

IN

PRODUCT HIGHLIGHTS

SUCCESSIVE

APPROXIMATION

ADC

CONTROL LOGIC

AD7910/AD7920

GND

Figure 1.

SCLK
SDATA
CS

02976-001

The AD7910/AD79201 are, respectively, 10-bit and 12-bit, high
speed, low power, successive approximation ADCs. The parts
operate from a single 2.35 V to 5.25 V power supply and feature
throughput rates up to 250 kSPS. The parts contain a low noise,
wide bandwidth track-and-hold amplifier that can handle input
frequencies in excess of 13 MHz.

The conversion process and data acquisition are controlled

CS

using

and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of

CS

and the conversion is initiated at this

point. There are no pipeline delays associated with the part.

The AD7910/AD7920 use advanced design techniques to
achieve very low power dissipation at high throughput rates.

The reference for the part is taken internally from V

DD

. This
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the part is 0 to V

. The conversion rate

DD

is determined by the SCLK.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

1. 10-/12-bit ADCs in SC70 and MSOP packages.

2. Low power consumption.

3. Flexible power/serial clock speed management. The

conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced when power-down mode is used while not
converting. The part also features a power-down mode to
maximize power efficiency at lower throughput rates.
Current consumption is 1 μA maximum and 50 nA typically
when in power-down mode.

4. Reference derived from the power supply.

5. No pipeline delay. The parts feature a standard successive

approximation ADC with accurate control of the sampling

CS

instant via a

1

Protected by U.S. Patent No. 6,681,332.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

input and once-off conversion control.

AD7910/AD7920

TABLE OF CONTENTS

Features .............................................................................................. 1

ADC Transfer Function............................................................. 14

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights........................................................................... 1

Specifications..................................................................................... 3

AD7910.......................................................................................... 3

AD7920.......................................................................................... 4

Timing Specifications .................................................................. 6

Timing Examples .............................................................................. 7

Timing Example 1 ........................................................................ 7

Timing Example 2 ........................................................................ 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Typical Performance Characteristics ........................................... 10

Typical C o n ne ction D i a g ram ................................................... 14

Analog Input............................................................................... 15

Digital Inputs .............................................................................. 15

Modes of Operation ....................................................................... 16

Normal Mode.............................................................................. 16

Power-Down Mode .................................................................... 16

Power-Up Time .......................................................................... 16

Power vs. Throughput Rate ........................................................... 18

Serial Interface................................................................................ 19

Microprocessor Interfacing ........................................................... 20

AD7910/AD7920 to TMS320C541 Interface......................... 20

AD7910/AD7920 to ADSP-218x.............................................. 20

AD7910/AD7920 to DSP563xx Interface ............................... 21

Application Hints ........................................................................... 22

Grounding and Layout .............................................................. 22

Te r mi n ol o g y .................................................................................... 12

Circuit Information........................................................................ 13

Converter Operation...................................................................... 14

REVISION HISTORY

9/05—Rev. B to Rev. C

Updated Formatting ..........................................................Universal

Updated Outline Dimensions....................................................... 23

Changes to Ordering Guide.......................................................... 24

3/04—Rev. A to Rev. B

Added U.S. Patent Number ............................................................ 1

Changes to Note 5 ............................................................................ 2

Changes to Note 6 of AD7920 Specifications............................... 4

Changes to Note 1 of Timing Specifications ................................ 4

Changes to Absolute Maximum Ratings ...................................... 6

Changes to Ordering Guide............................................................ 6

Evaluating Performance ............................................................ 22

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 24

8/03—Rev. 0 to Rev. A

Changes to Ordering Guide.............................................................6

Changes to Evaluating the AD7910/AD7920 Performance

Section.............................................................................................. 18

Updated Outline Dimensions ...................................................... 19

Rev. C | Page 2 of 24

AD7910/AD7920

SPECIFICATIONS

AD7910

VDD = 2.35 V to 5.25 V, f

Table 1.

Parameter1 A Grade

DYNAMIC PERFORMANCE fIN = 100 kHz sine wave

Signal-to-Noise + Distortion (SINAD)3 61 dB min
Total Harmonic Distortion (THD)3 −72 dB max
Peak Harmonic or Spurious Noise (SFDR)3 −73 dB max
Intermodulation Distortion (IMD)3

Second-Order Terms −82 dB typ fa = 100.73 kHz, fb = 90.7 kHz

Third-Order Terms −82 dB typ fa = 100.73 kHz, fb = 90.7 kHz
Aperture Delay 10 ns typ
Aperture Jitter 30 ps typ
Full Power Bandwidth 13.5 MHz typ @ 3 dB
2 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 10 Bits
Integral Nonlinearity ±0.5 LSB max
Differential Nonlinearity ±0.5 LSB max Guaranteed no missed codes to 10 bits
Offset Error
Gain Error

3, 4

±1 LSB max

3, 4

Total Unadjusted Error (TUE)

ANALOG INPUT

Input Voltage Ranges 0 to VDD V
DC Leakage Current ±0.5 A max
Input Capacitance 20 pF typ Track-and-hold in track, 6 pF typ when in hold

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V

0.4 V max VDD = 3 V
Input Current, IIN, SCLK Pin ± 0.5 A max Typically 10 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin
Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH VDD − 0.2 V min I
Output Low Voltage, VOL 0.4 V max I
Floating-State Leakage Current ±1 A max
Floating-State Output Capacitance5 5 pF max
Output Coding Straight (natural) binary

CONVERSION RATE

Conversion Time 2.8 s max 14 SCLK cycles with SCLK at 5 MHz
Track-and-Hold Acquisition Time3 250 ns max
Throughput Rate 250 kSPS max

POWER REQUIREMENTS

VDD 2.35/5.25 V min/max
IDD Digital I/Ps = 0 V or VDD

Normal Mode (Static) 2.5 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off

1.2 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off

Normal Mode (Operational) 3 mA max VDD = 4.75 V to 5.25 V, f

1.4 mA max VDD = 2.35 V to 3.6 V, f

Full Power-Down Mode 1 A max Typically 50 nA

= 5 MHz, f

SCLK

= 250 kSPS, TA = T

SAMPLE

1, 2

MIN

to T

, unless otherwise noted.

MAX

Unit Test Conditions/Comments

±1 LSB max

3, 4

2.4 V min

INH

0.8 V max VDD = 5 V

INL

±1.2 LSB max

± 10 nA typ

5

5 pF max

IN

SOURCE

= 200 A

SINK

= 200 A, VDD = 2.35 V to 5.25 V

= 250 kSPS

SAMPLE

= 250 kSPS

SAMPLE

Rev. C | Page 3 of 24

AD7910/AD7920

Parameter1 A Grade

Power Dissipation

6

Normal Mode (Operational) 15 mW max VDD = 5 V, f

4.2 mW max VDD = 3 V, f

1, 2

Unit Test Conditions/Comments

= 250 kSPS

SAMPLE

= 250 kSPS

SAMPLE

Full Power-Down 5 W max VDD = 5 V
3 W max VDD = 3 V

1

Temperature range from −40°C to +85°C.

2

Operational from VDD = 2.0 V, with input high voltage (V

3

See the Terminology section.

4

SC70 values guaranteed by characterization.

5

Guaranteed by characterization.

6

See the Power vs. Throughput Rate section.

) 1.8 V min.

INH

AD7920

VDD = 2.35 V to 5.25 V, f

Table 2.

Parameter1 A Grade

DYNAMIC PERFORMANCE fIN = 100 kHz sine wave

Signal-to-Noise + Distortion (SINAD)3 70 70 dB min VDD = 2.35 V to 3.6 V, TA = 25°C
69 69 dB min VDD = 2.4 V to 3.6 V

71.5 71.5 dB typ VDD = 2.35 V to 3.6 V
69 69 dB min VDD = 4.75 V to 5.25 V, TA = 25°C
68 68 dB min VDD = 4.75 V to 5.25 V
Signal-to-Noise Ratio (SNR)3 71 71 dB min VDD = 2.35 V to 3.6 V, TA = 25°C
70 70 dB min VDD = 2.4 V to 3.6 V
70 70 dB min VDD = 4.75 V to 5.25 V, TA = 25°C
69 69 dB min VDD = 4.75 V to 5.25 V
Total Harmonic Distortion (THD)3 −80 −80 dB typ
Peak Harmonic or Spurious Noise (SFDR)3 −82 −82 dB typ
Intermodulation Distortion (IMD)3

Second-Order Terms −84 −84 dB typ fa = 100.73 kHz, fb = 90.72 kHz

Third-Order Terms −84 −84 dB typ fa = 100.73 kHz, fb = 90.72 kHz
Aperture Delay 10 10 ns typ
Aperture Jitter 30 30 ps typ
Full Power Bandwidth 13.5 13.5 MHz typ @ 3 dB
2 2 MHz typ @ 0.1 dB

DC ACCURACY B Grade4

Resolution 12 12 Bits
Integral Nonlinearity3 ±1.5 LSB max
± 0.75 LSB typ
Differential Nonlinearity −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits
±0.75 LSB typ
Offset Error

3, 5

±1.5 LSB max
±1.5 ±0.2 LSB typ
Gain Error

3, 5

±1.5 ±0.5 LSB typ
Total Unadjusted Error (TUE)

ANALOG INPUT

Input Voltage Ranges 0 to VDD 0 to VDD V
DC Leakage Current ±0.5 ±0.5 A max
Input Capacitance 20 20 pF typ Track-and-hold in track, 6 pF typ when in hold

= 5 MHz, f

SCLK

= 250 kSPS, TA = T

SAMPLE

, 1 2

B Grade

MIN

to T

, unless otherwise noted.

MAX

1, 2

Unit Test Conditions/Comments

±1.5 LSB max

3, 5

±2 LSB max

Rev. C | Page 4 of 24

AD7910/AD7920

Parameter1 A Grade

, 1 2

B Grade

1, 2

Unit Test Conditions/Comments

LOGIC INPUTS

Input High Voltage, V

2.4 2.4 V min

INH

1.8 1.8 V min VDD = 2.35 V
Input Low Voltage, V

0.8 0.8 V max VDD = 3.6 V to 5.25 V

INL

0.4 0.4 V max VDD = 2.35 V to 3.6 V
Input Current, IIN, SCLK Pin ±0.5 ±0.5 A max Typically 10 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin
Input Capacitance, C

6

IN

5 5 pF max

±10 ±10 nA typ

LOGIC OUTPUTS

Output High Voltage, VOH VDD − 0.2 VDD − 0.2 V min I
Output Low Voltage, VOL 0.4 0.4 V max I

= 200 µA, VDD = 2.35 V to 5.25 V

SOURCE

= 200 µA

SINK

Floating-State Leakage Current ±1 ±1 A max
Floating-State Output Capacitance6 5 5 pF max
Output Coding Straight (natural) binary

CONVERSION RATE

Conversion Time 3.2 3.2 s max 16 SCLK cycles with SCLK at 5 MHz
Track-and-Hold Acquisition Time3 250 250 ns max
Throughput Rate 250 250 kSPS max See the Serial Interface section

POWER REQUIREMENTS

VDD 2.35/5.25 2.35/5.25 V min/max
IDD Digital I/Ps = 0 V or VDD

Normal Mode (Static) 2.5 2.5 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off

1.2 1.2 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off
Normal Mode (Operational) 3 3 mA max VDD = 4.75 V to 5.25 V, f

1.4 1.4 mA max VDD = 2.35 V to 3.6 V, f

SAMPLE

= 250 kSPS

SAMPLE

= 250 kSPS

Full Power-Down Mode 1 1 A max Typically 50 nA

Power Dissipation

Normal Mode (Operational) 15 15 mW max VDD = 5 V, f

4.2 4.2 mW max VDD = 3 V, f

7

SAMPLE

SAMPLE

= 250 kSPS
= 250 kSPS

Full Power-Down 5 5 W max VDD = 5 V

3 3 W max VDD = 3 V

1

Temperature range from −40°C to +85°C.

2

Operational from VDD = 2.0 V, with input low voltage (V

3

See the Terminology section.

4

B Grade, maximum specifications apply as typical figures when VDD = 4.75 V to 5.25 V.

5

SC70 values guaranteed by characterization.

6

Guaranteed by characterization.

7

See the Power vs. Throughput Rate section.

) 0.35 V max.

INL

Rev. C | Page 5 of 24

AD7910/AD7920

TIMING SPECIFICATIONS

VDD = 2.35 V to 5.25 V, TA = T

Table 3.

AD7910/AD7920

Parameter1

2

f

10 kHz min3

SCLK

Limit at T

5 MHz max
t

14 × t

CONVER T

16 × t
t

50 ns min

QUIET

t1 10 ns min
t2 10 ns min

4

t

22 ns max

3

t4 40 ns max Data access time after SCLK falling edge
t5 0.4 × t
t6 0.4 × t

5, 6

t

7

SCLK to data valid hold time

10 ns min VDD ≤ 3.3 V

9.5 ns min 3.3 V < VDD ≤ 3.6 V
7 ns min VDD > 3.6 V

6, 7

t

8

36 ns max SCLK falling edge to SDATA three-state

See Note 7 ns min SCLK falling edge to SDATA three-state

8

t

POWER-UP

1

Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2

Mark/Space ratio for the SCLK input is 40/60 to 60/40.

3

Minimum f

4

Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 1.8 V when VDD = 2.35 V and 0.8 V or 2.0 V for VDD > 2.35 V.

5

Measured with a 50 pF load capacitor.

6

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated

at which specifications are guaranteed.

SCLK

1 s max Power-up time from full power-down

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, shown in the Timing Specifications is the true bus relinquish
time of the part and is independent of the bus loading.

7

T7 values apply to t8 minimum values also.

8

See Power-Up Time section.

to T

MIN

, T

MIN

AD7910

SCLK

AD7920

SCLK

, unless otherwise noted.

MAX

Unit Description

MAX

Minimum quiet time required between bus relinquish and start of next
conversion

Minimum

CS pulse width
CS to SCLK setup time
Delay from

ns min SCLK low pulse width

SCLK

ns min SCLK high pulse width

SCLK

CS until SDATA three-state disabled

TO OUTPUT

PIN

200μAI

C

L

50pF

200μAI

OL

1.6V

OH

02976-002

Figure 2. Load Circuit for Digital Output Timing Specifications

Rev. C | Page 6 of 24

AD7910/AD7920

S

TIMING EXAMPLES

Figure 3 and Figure 4 show some of the timing parameters from
Tabl e 3.

TIMING EXAMPLE 1

From Figure 4, having f
250 kSPS gives a cycle time of t
With t

= 10 ns min, this leaves t

2

satisfies the requirement of 250 ns for t
comprises 2.5(1/f

SCLK

allows a value of 954 ns for t
requirement of 50 ns.

CS

SCLK

SDATA

STATE

= 5 MHz and a throughput rate of

SCLK

+ 12.5(1/f

2

to be 1.49 μs. This 1.49 μs

ACQ

) + t8 + t

t

2

12345 13141516

t

3

Z

, where t8 = 36 ns max. This

QUIET

, satisfying the minimum

QUIET

ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0

4 LEADING ZEROS

) + t

SCLK

ACQ

. From Figure 4, t

ACQ

t

t

4

= 4 μs.

t

CONVERT

6

t

ACQ

7

Figure 3. AD7920 Serial Interface Timing Diagram

TIMING EXAMPLE 2

The AD7920 can also operate with slower clock frequencies.

Figure 4, having f

From
150 kSPS gives a cycle time of t
With t

= 10 ns min, this leaves t

2

satisfies the requirement of 250 ns for t
comprises 2.5(1/f

SCLK

value of 2.19 μs for t
of 50 ns. As in this example and with other slower clock values,
the signal may already be acquired before the conversion is
complete, but it is still necessary to leave 50 ns minimum t
between conversions. In this example, the signal should be fully
acquired at approximately Point C in

B

t

5

= 3.4 MHz and a throughput rate of

SCLK

+ 12.5(1/f

2

to be 2.97 μs. This 2.97 μs

ACQ

) + t8 + t

, satisfying the minimum requirement

QUIET

, t8 = 36 ns max. This allows a

QUIET

) + t

SCLK

ACQ

. From Figure 4, t

ACQ

Figure 4.

t

1

t

8

t

QUIET

THREE-STATETHREE-

= 6.66 μs.

ACQ

QUIET

02976-003

CS

t

SCLK

CONVERT

)

B

1/THROUGHPUT

C

t

8

t

ACQ

t

QUIET

02976-004

CLK

t

2

12345 13141516

12.5(1/f

Figure 4. Serial Interface Timing Example

Rev. C | Page 7 of 24

AD7910/AD7920

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Tabl e 4.

Parameter Rating

VDD to GND −0.3 V to +7 V
Analog Input Voltage to GND −0.3 V to VDD + 0.3 V
Digital Input Voltage to GND −0.3 V to +7 V
Digital Output Voltage to GND −0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies1± 10 mA
Operating Temperature Range

Commercial (A, B Grade) −40°C to +85°C

Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
MSOP Package

θJA Thermal Impedance 205.9°C/W

θJC Thermal Impedance 43.74°C/W
SC70 Package

θJA Thermal Impedance 340.2°C/W

θJC Thermal Impedance 228.9°C/W
Lead Temperature, Soldering

Reflow (10 sec to 30 sec) 235 (0/+5)°C
ESD 3.5 kV

1

Transient currents of up to 100 mA will not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 8 of 24