Analog Devices AD7894 Datasheet

5 V, 14-Bit Serial, 5 ␮s

SIGNAL

SCALING*

TRACK/

HOLD

14-BIT

ADC

AD7894

OUTPUT

REGISTER

REF IN

V

DD

V

IN

CONVST

GND BUSY SCLK SDATA

*AD7894-10, AD7894-3

a

FEATURES
Fast 14-Bit ADC with 5 ␮s Conversion Time
8-Lead SOIC Package
Single 5 V Supply Operation
High Speed, Easy-to-Use, Serial Interface
On-Chip Track/Hold Amplifier
Selection of Input Ranges

ⴞ10 V for AD7894-10
ⴞ2.5 V for AD7894-3

0 V to +2.5 V for AD7894-2
High Input Impedance
Low Power: 20 mW Typ
Pin Compatible Upgrade of 12-Bit AD7895

GENERAL DESCRIPTION

The AD7894 is a fast, 14-bit ADC that operates from a single
+5 V supply and is housed in a small 8-lead SOIC. The part

contains a 5 µs successive approximation A/D converter, an on-

chip track/hold amplifier, an on-chip clock and a high speed
serial interface.

Output data from the AD7894 is provided via a high speed,
serial interface port. This two-wire serial interface has a serial
clock input and a serial data output with the external serial clock
accessing the serial data from the part.

In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the AD7894 is also speci­fied for dynamic performance parameters including harmonic
distortion and signal-to-noise ratio.

The part accepts an analog input range of ±10 V (AD7894-10),
±2.5 V (AD7894-3), 0 V to +2.5 V (AD7894-2), and operates

from a single +5 V supply consuming only 20 mW typical.

The AD7894 features a high sampling rate mode and, for low
power applications, a proprietary automatic power-down mode
where the part automatically goes into power-down once conver­sion is complete and “wakes up” before the next conversion
cycle.

The part is available in a small outline IC (SOIC).

ADC in SO-8 Package

AD7894

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. Fast, 14-Bit ADC in 8-Lead Package

The AD7894 contains a 5␣ µs ADC, a track/hold amplifier,

control logic and a high speed serial interface, all in an 8-lead
package. This offers considerable space saving over alterna­tive solutions.

2. Low Power, Single Supply Operation
The AD7894 operates from a single +5 V supply and con­sumes only 20 mW. The automatic power-down mode,
where the part goes into power-down once conversion is
complete and “wakes up” before the next conversion cycle,
makes the AD7894 ideal for battery powered or portable
applications.

3. High Speed Serial Interface
The part provides high speed serial data and serial clock lines
allowing for an easy, two-wire serial interface arrangement.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

AD7894–SPECIFICATIONS

(VDD = +5 V ⴞ 5%, GND = 0 V, REF IN = +2.5 V. All specifications T
otherwise noted.)

MIN

to T

MAX

unless

Parameter A Versions

DYNAMIC PERFORMANCE

Signal to (Noise + Distortion) Ratio

2

3

@ +25°C 78 78 dB min f

T

to T

MIN

MAX

Total Harmonic Distortion (THD)

Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)

77 77 dB min See Figure 14

3

–86 –86 dB max fIN = 10 kHz Sine Wave, f

3

–92 –92 dB typ fIN = 10 kHz Sine Wave, f

3

l

B Versions1Units Test Conditions/Comments

= 70 kHz Sine Wave, f

IN

Typically –87 dB. See Figure 15

fa = 9 kHz, fb = 9.5 kHz, f
2nd Order Terms –92 –92 dB typ
3rd Order Terms –92 –92 dB typ

DC ACCURACY

Resolution 14 14 Bits
Minimum Resolution for Which

No Missing Codes Are Guaranteed 14 14 Bits

Relative Accuracy
Differential Nonlinearity
AD7894-2

Positive Gain Error

3

3

3

±2 ±1.5 LSB max

–1 to +1.5 –1 to +1.5 LSB max

±12 ±10 LSB max

Unipolar Offset Error ±8 ±6 LSB max

AD7894-10, AD7894-3 Only

Positive Gain Error
Negative Gain Error

3

3

±8 ±6 LSB max
±8 ±6 LSB max

Bipolar Zero Error ±10 ±8 LSB max

ANALOG INPUT

AD7894-10

Input Voltage Range ±10 ±10 V

Input Current 2 2 mA max See Analog Input Section

AD7894-3

Input Voltage Range ±2.5 ±2.5 V

Input Current 1.5 1.5 mA max See Analog Input Section

AD7894-2

Input Voltage Range 0 to +2.5 0 to +2.5 V
Input Current 500 500 nA max

REFERENCE INPUT

REF IN Input Voltage Range 2.375/2.625 2.375/2.625 V min/V max 2.5 V ± 5%
Input Current 1 1 µA max

Input Capacitance

4

10 10 pF max

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

4

2.4 2.4 V min V

0.8 0.8 V max V

±10 ±10 µA max V

10 10 pF max

= 5 V ± 5%

DD

= 5 V ± 5%

DD

= 0 V to V

IN

DD

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OL

OH

4.0 4.0 V min I

0.4 0.4 V max I

SOURCE

= 1.6 mA

SINK

= 400 µA

Output Coding
AD7894-10, AD7894-3 Twos Complement
AD7894-2 Straight (Natural) Binary

CONVERSION RATE

Conversion Time

Mode 1 Operation 5 5 µs max

Mode 2 Operation
Track/Hold Acquisition Time

5

3

10 10 µs max

0.35 0.35 µs max

SAMPLE AND HOLD

–3 dB Small Signal Bandwidth 7.5 7.5 MHz typ
Aperture Jitter 50 50 ps typ

SAMPLE

SAMPLE

SAMPLE

SAMPLE

= 160 kHz

= 160 kHz,

= 160 kHz

= 160 kHz

–2–

REV. 0

AD7894

WARNING!

ESD SENSITIVE DEVICE

Parameter A Versions

POWER REQUIREMENTS

V

DD

I

DD

+5 +5 V nom ±5% for Specified Performance

5.5 5.5 mA max Digital Inputs @ VDD, V
Power Dissipation 27.5 27.5 mW max Typically 20 mW
Power-Down Mode

I

@ T

DD

Power Dissipation T

NOTES

1

Temperature ranges are as follows: A, B Versions: –40°C to +85°C.

2

Applies to Mode 1 operation. See Operating Modes section.

3

See Terminology.

4

Sample tested @ +25°C to ensure compliance.

5

This 10 µs includes the “wake-up” time from standby. This “wake-up” time is timed from the rising edge of CONVST, whereas conversion is timed from the falling
edge of CONVST, for narrow CONVST pulsewidth the conversion time is effectively the “wake-up” time plus conversion time, hence 10 µs. This can be seen from
Figure 3. Note that if the CONVST pulsewidth is greater than 5 µs, the effective conversion time will increase beyond 10 µs.

Specifications subject to change without notice.

TIMING CHARACTERISTICS

MIN

to T

MAX

MIN

to T

MAX

20 20 µA max Digital Inputs @ GND, VDD = 5 V ± 5%
100 100 µW max

1, 2

(VDD = +5 V ⴞ 5%, GND = 0 V, REF IN = +2.5 V)

Parameter A, B Versions Units Test Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.

2

The SCLK maximum frequency is 16 MHz. Care must be taken when interfacing to account for the data access time, t4, and the setup time required for the user’s
processor. These two times will determine the maximum SCLK frequency with which the user’s system can operate. See Serial Interface section for more information.

3

Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V.

4

Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
of the part and as such is independent of external bus loading capacitances.

Specifications subject to change without notice.

40 ns min CONVST Pulsewidth

2

31.25

2

31.25

3

60

10 ns min Data Hold Time after Falling Edge of SCLK

4

20

l

B Versions1Units Test Conditions/Comments

= 5 V ± 5%

DD

Typ 15 µW

ns min SCLK High Pulsewidth
ns min SCLK Low Pulsewidth
ns max Data Access Time after Falling Edge of SCLK

= 5 V ± 5%

V

DD

ns max Bus Relinquish Time after Falling Edge of SCLK

, quoted in the timing characteristics is the true bus relinquish time

6

ABSOLUTE MAXIMUM RATINGS*

(T

= +25°C unless otherwise noted)

A

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣ V to +7 V

Analog Input Voltage to GND

␣ ␣ AD7894-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±17 V

␣ ␣ AD7894-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V

␣ ␣ AD7894-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +10 V

Reference Input Voltage to GND . . . . –0.3 V to V

Digital Input Voltage to GND . . . . . . . –0.3 V to V

Digital Output Voltage to GND . . . . . –0.3 V to V

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 170°C/W

␣␣θ

JA

␣ ␣ Lead Temperature, Soldering

␣␣␣␣Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C

␣␣␣␣Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

␣ ␣ Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C

␣ ␣ Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7894 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–3–REV. 0

AD7894

ORDERING GUIDE

Temperature Package Package

Model Range INL Input Range SNR Description Option

AD7894AR-10 –40°C to +85°C ±2 LSB ±10 V 77 dB 8-Lead Narrow Body SOIC SO-8
AD7894BR-10 –40°C to +85°C ±1.5 LSB ±10 V 77 dB 8-Lead Narrow Body SOIC SO-8
AD7894AR-3 –40°C to +85°C ±2 LSB ±2.5 V 77 dB 8-Lead Narrow Body SOIC SO-8
AD7894BR-3 –40°C to +85°C ±1.5 LSB ±2.5 V 77 dB 8-Lead Narrow Body SOIC SO-8
AD7894AR-2 –40°C to +85°C ±2 LSB 0 V to +2.5 V 77 dB 8-Lead Narrow Body SOIC SO-8

PIN FUNCTION DESCRIPTIONS

Pin Pin
No. Mnemonic Description

1 REF IN Voltage Reference Input. An external reference source should be connected to this pin to provide the

reference voltage for the AD7894’s conversion process. The REF IN input is buffered on-chip. The
nominal reference voltage for correct operation of the AD7894 is +2.5␣ V.

2V

IN

3 GND Analog Ground. Ground reference for track/hold, comparator, digital circuitry and DAC.
4 SCLK Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7894.

5 SDATA Serial Data Output. Serial data from the AD7894 is provided at this output. The serial data is clocked

6 BUSY The BUSY pin is used to indicate when the part is doing a conversion. The BUSY pin will go high on

7 CONVST Conversion Start. Edge-triggered logic input. On the falling edge of this input, the track/hold goes into its

8V

DD

Analog Input Channel. The analog input range is ±10 V (AD7894-10), ±2.5 V (AD7894-3) and 0 V to

+2.5␣ V (AD7894-2).

A new serial data bit is clocked out on the falling edge of this serial clock. Data is guaranteed valid for
10 ns after this falling edge so data can be accepted on the falling edge when a fast serial clock is used.
The serial clock input should be taken low at the end of the serial data transmission.

out by the falling edge of SCLK, but the data can also be read on the falling edge of SCLK. This is pos­sible because data bit N is valid for a specified time after the falling edge of SCLK (data hold time) (see
Figure 5). Sixteen bits of serial data are provided as two leading zeroes followed by the 14 bits of conver­sion data. On the 16th falling edge of SCLK, the SDATA line is held for the data hold time and then
disabled (three-stated). Output data coding is twos complement for the AD7894-10 and AD7894-3, and
straight binary for the AD7894-2.

the falling edge of CONVST and will return low when the conversion is complete.

hold mode and conversion is initiated. If CONVST is low at the end of conversion, the part goes into
power-down mode. In this case, the rising edge of CONVST will cause the part to begin waking up.

Positive supply voltage, +5 V ± 5%.

1.6mA

TO

OUTPUT

PIN

50pF

400mA

+1.6V

Figure 1. Load Circuit for Access Time and Bus
Relinquish Time

–4–

PIN CONFIGURATION

SOIC (SO-8)

REF IN

V

GND

1

2

IN

3

4

AD7894

TOP VIEW

(Not to Scale)

8

V

7

CONVST

6

BUSY

5

SDATASCLK

DD

REV. 0