Analog Devices AD7891 d Datasheet

LC2MOS 8-Channel, 12-Bit

2.5V

REFERENCE

TRACK/HOLD

V

IN1A

V

IN1B

V

IN2A

V

IN2B

V

IN3A

V

IN3B

V

IN4A

V

IN4B

V

IN5A

V

IN5B

V

IN6A

V

IN6B

V

IN7A

V

IN7B

V

IN8A

V

IN8B

CONTROL LOGIC

WR CS RD EOC CONVST

MODE AGND

AGND DGND

CLOCK

V

DDVDD

AD7891

12-BIT

ADC

ADDRESS

DECODE

REF OUT/

REF IN

REF GND

STANDBY

M

U
X

DATA/
CONTROL
LINES

a

FEATURES
Fast 12-Bit ADC with 1.6 ␮s Conversion Time
8 Single-Ended Analog Input Channels
Overvoltage Protection on Each Channel
Selection of Input Ranges:

ⴞ5 V, ⴞ10 V for AD7891-1

0 to +2.5 V, 0 to +5 V, ⴞ2.5 V for AD7891-2
Parallel and Serial Interface
On-Chip Track/Hold Amplifier
On-Chip Reference
Single-Supply, Low Power Operation (100 mW Max)
Power-Down Mode (75 ␮W Typ)

APPLICATIONS
Data Acquisition Systems
Motor Control
Mobile Communication Base Stations
Instrumentation

High Speed Data Acquisition System

AD7891

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The AD7891 is an 8-channel, 12-bit data acquisition system
with a choice of either parallel or serial interface structure. The
part contains an input multiplexer, an on-chip track/hold ampli­fier, a high speed 12-bit ADC, a 2.5 V reference, and a high
speed interface. The part operates from a single 5 V supply and
accepts a variety of analog input ranges across two models, the
AD7891-1 (± 5V and ± 10 V) and the AD7891-2 (0 V to +2.5 V,
0V to +5 V, and ± 2.5 V).

The AD7891 provides the option of either a parallel or serial
interface structure determined by the MODE pin. The part
has standard control inputs and fast data access times for both
the serial and parallel interfaces, ensuring easy interfacing to
modern microprocessors, microcontrollers, and digital signal
processors.

In addition to the traditional dc accuracy specifications, such as
linearity, full-scale and offset errors, the part is also specified for
dynamic performance parameters, including harmonic distortion

PRODUCT HIGHLIGHTS

1. The AD7891 is a complete monolithic 12-bit data acquisition
system that combines an 8-channel multiplexer, 12-bit ADC,

2.5 V reference, and track/hold amplifier on a single chip.

2. The AD7891-2 features a conversion time of 1.6 ms and an
acquisition time of 0.4 ms. This allows a sample rate of
500 kSPS when sampling one channel and 62.5 kSPS when
channel hopping. These sample rates can be achieved using
either a software or hardware convert start. The AD7891-1
has an acquisition time of 0.6 ms when using a hardware
convert start and an acquisition time of 0.7 ms when using a
software convert start. These acquisition times allow sample
rates of 454.5 kSPS and 435 kSPS, respectively, for hardware
and software convert start.

3. Each channel on the AD7891 has overvoltage protection. This
means an overvoltage on an unselected channel does not affect
the conversion on a selected channel. The AD7891-1 can
withstand overvoltages of ± 17 V.

and signal-to-noise ratio.

Power dissipation in normal mode is 82 mW typical; in
the standby mode, this is reduced to 75 mW typ. The part is
available in a 44-terminal MQFP and a 44-lead PLCC.

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD7891–SPECIFICATIONS

(VDD = 5 V ⴞ 5%, AGND = DGND = 0 V, REF IN = 2.5 V. All specifications T
unless otherwise noted.)

MIN

to T

Parameter A Version1B Version Y Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

2

Signal-to-(Noise + Distortion) Ratio

4

Sample Rate = 454.5 kSPS3 (AD7891-1),
500 kSPS

3

(AD7891-2). Any channel.

@ 25∞C707070dB min

to T

T

MIN

Total Harmonic Distortion

MAX

Peak Harmonic or Spurious Noise
Intermodulation Distortion

4

4

70 70 70 dB min
–78 –78 –78 dB max

4

–80 –80 –80 dB max

fa = 9 kHz, fb = 9.5 kHz.
Second-Order Terms –80 –80 –80 dB typ
Third-Order Terms –80 –80 –80 dB typ

Channel-to-Channel Isolation

4

–80 –80 –80 dB max

DC ACCURACY Any channel.

Resolution 12 12 12 Bits
Minimum Resolution for which

No Missing Codes Are Guaranteed 12 12 12 Bits

Relative Accuracy
Differential Nonlinearity
Positive Full-Scale Error
Positive Full-Scale Error Match
Unipolar Offset Error ± 4 ± 4 ± 4 LSB max Input ranges of 0 V to 2.5 V, 0 V to 5 V.
Unipolar Offset Error Match
Negative Full-Scale Error
Negative Full-Scale Error Match
Bipolar Zero Error ± 4 ± 4 ± 4 LSB max Input ranges of ± 2.5 V, ± 5V, ± 10 V.
Bipolar Zero Error Match

4

4

4

5

4

5

± 1 ± 0.75 ± 1 LSB max
± 1 ± 1 ± 1 LSB max
± 3 ± 3 ± 3 LSB max

4, 5

0.6 0.6 0.6 LSB typ 1.5 LSB max.

0.1 0.1 0.1 LSB typ 1 LSB max.
± 3 ± 3 ± 3 LSB max Input ranges of ± 2.5 V, ± 5V, ± 10 V.

4, 5

0.6 0.6 0.6 LSB typ 1.5 LSB max.

0.2 0.2 0.2 LSB typ 1.5 LSB max.

ANALOG INPUTS

AD7891-1 Input Voltage Range

± 5 ± 5 ± 5V Input applied to both V

AD7891-1 V
AD7891-1 V

± 10 ± 10 ± 10 V Input applied to V

Input Resistance 7.5 7.5 7.5 kW min Input range of ± 5V.

INXA

Input Resistance 15 15 15 kW min Input range of ± 10 V.

INXA

INXA

AD7891-2 Input Voltage Range 0 to 2.5 0 to 2.5 0 to 2.5 V Input applied to both V

AD7891-2 V
AD7891-2 V

0 to 5 0 to 5 0 to 5 V Input applied to V
± 2.5 ± 2.5 ± 2.5 V Input applied to V

Input Resistance 1.5 1.5 1.5 kW min Input ranges of ± 2.5 V and 0 V to 5 V.

INXA

Input Current ± 50 ± 50 ± 50 nA max Input range of 0 V to 2.5 V.

INXA

INXA

INXA

INXA

, V

INXA

, V
, V

INXB

INXB

INXB

and V

INXB

= AGND.

and V

INXB

= AGND.
= REF IN6.

REFERENCE INPUT/OUTPUT

REF IN Input Voltage Range 2.375/2.625 2.375/2.625 2.375/2.625 V min/V max 2.5 V ± 5%.
Input Impedance 1.6 1.6 1.6 kW min Resistor connected to internal reference node.
Input Capacitance

5

10 10 10 pF max
REF OUT Output Voltage 2.5 2.5 2.5 V nom
REF OUT Error @ 25∞C ± 10 ± 10 ± 10 mV max

to T

T

MIN

MAX

± 20 ± 20 ± 20 mV max
REF OUT Temperature Coefficient 25 25 25 ppm/∞C typ
REF OUT Output Impedance 5 5 5 kW nom See REF IN input impedance.

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INH

Input Capacitance5 C

INH

INL

IN

2.4 2.4 2.4 V min VDD = 5 V ± 5%.

0.8 0.8 0.8 V max VDD = 5 V ± 5%.

± 10 ± 10 ± 10 mA max

10 10 10 pF max

,

MAX

.

.

–2–

REV. D

AD7891

Parameter A Version1B Version Y Version Unit Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OH

OL

4.0 4.0 4.0 V min I

0.4 0.4 0.4 V max I

DB11to DB0

Floating-State Leakage Current ± 10 ± 10 ± 10 mA max
Floating-State Capacitance

5

15 15 15 pF max

Output Coding

Straight (Natural) Binary Data format bit of control register = 0.
Twos Complement Data format bit of control register = 1.

CONVERSION RATE

Conversion Time 1.6 1.6 1.6 ms max
Track/Hold Acquisition Time 0.6 0.6 0.6 ms max AD7891-1 hardware conversion.

0.7 0.7 0.7 ms max AD7891-1 software conversion.

0.4 0.4 0.4 ms max AD7891-2.

POWER REQUIREMENTS

V

DD

I

DD

555V nom ±5% for specified performance.

Normal Mode 20 20 21 mA max
Standby Mode 80 80 80 mA max Logic inputs = 0 V or V

Power Dissipation V

Normal Mode 100 100 105 mW max Typically 82 mW.
Standby Mode 400 400 400 mW max Typically 75 mW.

NOTES

1

Temperature ranges for the A and B Versions: –40∞ C to +85∞C. Temperature range for the Y Version: –55∞C to +105∞C.

2

The AD7891-1’s dynamic performance (THD and SNR) and the AD7891-2’s THD are measured with an input frequency of 10 kHz. The AD7891-2’s SNR is
evaluated with an input frequency of 100 kHz.

3

This throughput rate can only be achieved when the part is operated in the parallel interface mode. Maximum achievable throughput rate in the serial interface mode
is 357 kSPS.

4

See the Terminology section.

5

Sample tested during initial release and after any redesign or process change that may affect this parameter.

6

REF IN must be buffered before being applied to V

Specifications subject to change without notice.

INXB

.

SOURCE

= 1.6 mA.

SINK

= 5 V.

DD

= 200 mA.

DD

.

ABSOLUTE MAXIMUM RATINGS*

(TA = 25∞C, unless otherwise noted)

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

Analog Input Voltage to AGND

AD7891-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 17 V

AD7891-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V, +10 V

Reference Input Voltage to AGND . . . . –0.3 V to V

Digital Input Voltage to DGND . . . . . . –0.3 V to V

Digital Output Voltage to DGND . . . . . –0.3 V to V

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Commercial (A, B Versions) . . . . . . . . . . . – 40∞C to +85∞C

Automotive (Y Version) . . . . . . . . . . . . . . –55∞C to +105∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C

MQFP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 95∞C/W

q

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215∞C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C

PLCC Package, Power Dissipation . . . . . . . . . . . . . . 500 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 55∞C/W

q

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215∞C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7891 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. D

–3–

AD7891

TIMING CHARACTERISTICS

1, 2

Parameter A, B, Y Versions Unit Test Conditions/Comments

t

CONV

1.6 ms max Conversion Time

Parallel Interface

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

3

t

9

4

t

10

0 ns min CS to RD/WR Setup Time
35 ns min Write Pulse Width
25 ns min Data Valid to Write Setup Time
5 ns min Data Valid to Write Hold Time
0 ns min CS to RD/WR Hold Time
35 ns min CONVST Pulse Width
55 ns min EOC Pulse Width
35 ns min Read Pulse Width
25 ns min Data Access Time after Falling Edge of RD
5 ns min Bus Relinquish Time after Rising Edge of RD
30 ns max

Serial Interface

t
t
t
t
t
t
t
t

t

11

12

13

14

15

16

17

18

18A

3

3

3

4

4

30 ns min RFS Low to SCLK Falling Edge Setup Time
20 ns max RFS Low to Data Valid Delay
25 ns min SCLK High Pulse Width
25 ns min SCLK Low Pulse Width
5 ns min SCLK Rising Edge to Data Valid Hold Time
15 ns max SCLK Rising Edge to Data Valid Delay
20 ns min RFS to SCLK Falling Edge Hold Time
0 ns min Bus Relinquish Time after Rising Edge of RFS
30 ns max
0 ns min Bus Relinquish Time after Rising Edge of SCLK
30 ns max

t

19

t

20

t

21

t

22

NOTES

1

Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1 ns (10% to
90% of 5 V) and timed from a voltage level of 1.6 V.

2

See Figures 2, 3, and 4.

3

Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

4

These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.

Specifications subject to change without notice.

20 ns min TFS Low to SCLK Falling Edge Setup Time
15 ns min Data Valid to SCLK Falling Edge Setup Time
10 ns min Data Valid to SCLK Falling Edge Hold Time
30 ns min TFS Low to SCLK Falling Edge Hold Time

1.6mA

TO

OUTPUT

PIN

50pF

200␮A

1.6V

Figure 1. Load Circuit for Access Time and Bus Relinquish Time

–4–

REV. D

ORDERING GUIDE

AD7891

Relative Temperature

Model Input Range Sample Rate Accuracy Range Package Option

AD7891ACHIPS-1 DIE
AD7891ACHIPS-2 DIE
AD7891AS-1 ± 5 V or ± 10 V 454 kSPS ± 1 LSB –40∞C to +85∞CS-44
AD7891ASZ-1

2

± 5 V or ± 10 V 454 kSPS ± 1 LSB –40∞C to +85∞CS-44
AD7891AP-1 ± 5 V or ± 10 V 454 kSPS ± 1 LSB –40∞C to +85∞C P-44A
AD7891AP-1REEL ± 5 V or ± 10 V 454 kSPS ± 1 LSB –40∞C to +85∞C P-44A
AD7891BS-1 ± 5 V or ± 10 V 454 kSPS ± 0.75 LSB –40∞C to +85∞CS-44
AD7891BP-1 ± 5 V or ± 10 V 454 kSPS ± 0.75 LSB –40∞C to +85∞C P-44A
AD7891BP-1REEL ± 5 V or ± 10 V 454 kSPS ± 0.75 LSB –40∞C to +85∞C P-44A
AD7891YS-1 ± 5 V or ± 10 V 454 kSPS ± 1 LSB –55∞C to +105∞CS-44
AD7891YS-1REEL ± 5 V or ± 10 V 454 kSPS ± 1 LSB –55∞C to +105∞CS-44
AD7891YP-1 ± 5 V or ± 10 V 454 kSPS ± 1 LSB –55∞C to +105∞C P-44A
AD7891YP-1REEL ± 5 V or ± 10 V 454 kSPS ± 1 LSB –55∞C to +105∞C P-44A
AD7891AS-2 0 V to +5 V, 0 V to +2.5 V, ± 2.5 V 500 kSPS ± 1 LSB –40∞C to +85∞CS-44
AD7891ASZ-2

2

0 V to +5 V, 0 V to +2.5 V, ± 2.5 V 500 kSPS ± 1 LSB –40∞C to +85∞CS-44
AD7891AP-2 0 V to +5 V, 0 V to +2.5 V, ± 2.5 V 500 kSPS ± 1 LSB –40∞C to +85∞C P-44A
AD7891AP-2REEL 0 V to +5 V, 0 V to +2.5 V, ±2.5 V 500 kSPS ± 1 LSB –40∞C to +85∞C P-44A
AD7891BS-2 0 V to +5 V, 0 V to +2.5 V, ± 2.5 V 500 kSPS ± 0.75 LSB –40∞C to +85∞CS-44
AD7891BP-2 0 V to +5 V, 0 V to +2.5 V, ± 2.5 V 500 kSPS ± 0.75 LSB –40∞C to +85∞C P-44A
AD7891BP-2REEL 0 V to +5 V, 0 V to +2.5 V, ± 2.5 V 500 kSPS ± 0.75 LSB –40∞C to +85∞C P-44A
AD7891YS-2 0 V to +5 V, 0 V to +2.5 V, ± 2.5 V 500 kSPS ± 1 LSB –55∞C to +105∞CS-44
AD7891YS-2REEL 0 V to +5 V, 0 V to +2.5 V, ± 2.5 V 500 kSPS ± 1 LSB –55∞C to +105∞CS-44
EVAL-AD7891-1CB Evaluation Board
EVAL-AD7891-2CB Evaluation Board

NOTES

1

S = Plastic Quad Flatpack (MQFP); P = Plastic Leaded Chip Carrier (PLCC).

2

Z = Pb-free part.

1

REF GND

REF OUT/REF IN

NC = NO CONNECT

NC

V

AGND

MODE

DB11/TEST

DB10/TEST

DB9/TFS

DB8/RFS

DB7/DATA IN

DD

PLCC

IN1A

IN1BVIN2AVIN2BVIN3AVIN3BVIN4AVIN4BVIN5AVIN5B

STANDBY

V

V

6 543 21444342 41 40

7

8

9

10

11

12

13

14

15

16

17

18 19 20 21 22 23 24 25 26 27 28

DD

V

DGND

DB6/SCLK

AD7891

TOP VIEW

(Not to Scale)

DB3/A0

DB4/A1

DB5/A2/DATA OUT

PIN 1
IDENTIFIER

DB2/SWCON

DB0/FORMAT

DB1/SWSTBY

WR

PIN CONFIGURATIONS

39

V

IN6A

38

V

IN6B

37

V

IN7A

36

V

IN7B

35

V

IN8A

34

V

IN8B

33

AGND

32

EOC

31

NC

30

CONVST

29

CS

RD

REF GND

NC

REF OUT/REF IN

V

AGND

MODE

DB11/TEST

DB10/TEST

DB9/TFS
DB8/RFS

DB7/DATA IN

NC = NO CONNECT

MQFP

IN1A

IN1BVIN2AVIN2BVIN3AVIN3BVIN4AVIN4BVIN5AVIN5B

STANDBY

V

V

44 43 42 41 40 39 38 37 36 35 34

1

PIN 1

2

IDENTIFIER

3

4

DD

5

6

7

8

9

10

11

(Not to Scale)

12 13 14 15 16 17 18 19 20 21 22

DD

V

DGND

DB6/SCLK

AD7891

TOP VIEW

DB3/A0

DB4/A1

DB2/SWCON

DB0/FORMAT

DB1/SWSTBY

DB5/A2/DATA OUT

WR

RD

33

V

32

V

31

V

30

V

29

V

28

V

27

AGND

26

EOC

25

NC

24

CONVST

23

CS

IN6A

IN6B

IN7A

IN7B

IN8A

IN8B

REV. D

–5–

AD7891

PIN FUNCTION DESCRIPTIONS

PLCC MQFP
Pin No. Pin No. Mnemonic Description

1–528–43 V
34–44 channel contains two input pins to allow a number of different input ranges to be used

10, 19 4, 13 V

11, 33 5, 27 AGND Analog Ground. Ground reference for track/hold, comparator, and DAC.

20 14 DGND Digital Ground. Ground reference for digital circuitry.
644STANDBY Standby Mode Input. TTL compatible input used to put the device into the power

93 REF OUT/REF IN Voltage Reference Output/Input. The part can either be used with its own internal refer-

71 REF GND Reference Ground. Ground reference for the part’s on-chip reference buffer. The REF

30 24 CONVST Convert Start. Edge-triggered logic input. A low-to-high transition on this input puts

32 26 EOC End-of-Conversion. Active low logic output indicating converter status. The end of con-

12 6 MODE Interface Mode. Control input that determines the interface mode for the part. With this

INXA

DD

, V

INXB

Analog Input Channels. The AD7891 contains eight pairs of analog input channels. Each

with the AD7891. There are two possible input voltage ranges on the AD7891-1. The
± 5V input range is selected by connecting the input voltage to both V
while the ± 10 V input range is selected by applying the input voltage to V
necting V

to AGND. The AD7891-2 has three possible input ranges. The 0 V to

INXB

2.5 V input range is selected by connecting the analog input voltage to both V
0V to 5 V input range is selected by applying the input voltage to V

to AGND while the ± 2.5 V input range is selected by connecting the analog input

V

INXB

voltage to V

and connecting V

INXA

to REF IN (provided this REF IN voltage comes

INXB

and V

INXA

INXA

and V

INXA

and connecting

INXA

,

INXB

and con-

; the

INXB

from a low impedance source). The channel to be converted is selected by the A2, A1,
and A0 bits of the control register. In the parallel interface mode, these bits are available as
three data input lines (DB3 to DB5) in a parallel write operation. While in the serial inter­face mode, these three bits are accessed via the DATA IN line in a serial write operation.
The multiplexer has guaranteed break-before-make operation.

Positive Supply Voltage, 5 V ± 5%.

save or standby mode. The STANDBY input is high for normal operation and low for
standby operation.

ence or with an external reference source. The on-chip 2.5 V reference voltage is pro­vided at this pin. When using this internal reference as the reference source for the
part, REF OUT should be decoupled to REF GND with a 0.1 mF disc ceramic capaci­tor. The output impedance of the reference source is typically 2 kW. When using an
external reference source as the reference voltage for the part, the reference source
should be connected to this pin. This overdrives the internal reference and provides the
reference source for the part. The reference pin is buffered on-chip but must be able to
sink or source current through this 2 kW resistor to the output of the on-chip reference.
The nominal reference voltage for correct operation of the AD7891 is 2.5 V.

OUT pin of the part should be decoupled with a 0.1 mF capacitor to this REF GND
pin. If the AD7891 is used with an external reference, the external reference should also
be decoupled to this pin. The REF GND pin should be connected to the AGND pin
or the system’s AGND plane.

the track/hold into hold and initiates conversion. When changing channels on the part,
sufficient time should be given for multiplexer settling and track/hold acquisition between
the channel change and the rising edge of CONVST.

version is signified by a low-going pulse on this line. The duration of this EOC pulse is
nominally 80 ns.

pin at a logic low, the AD7891 is in its serial interface mode; with this pin at a logic high,
the device is in its parallel interface mode.

–6–

REV. D