Analog Devices AD7891 Datasheet

LC2MOS 8-Channel, 12-Bit

+2.5V

REFERENCE

TRACK/HOLD

V

IN1A

V

IN1B

V

IN2A

V

IN2B

V

IN3A

V

IN3B

V

IN4A

V

IN4B

V

IN5A

V

IN5B

V

IN6A

V

IN6B

V

IN7A

V

IN7B

V

IN8A

V

IN8B

CONTROL LOGIC

WR CS RD EOC CONVST

MODE AGND

AGND DGND

CLOCK

VDDV

DD

AD7891

12-BIT

ADC

ADDRESS

DECODE

REF OUT/

REF IN

REF GND

STANDBY

M

U
X

DATA/
CONTROL
LINES

a

High Speed Data Acquisition System

AD7891

FEATURES
Fast 12-Bit ADC with 1.6 ␮s Conversion Time
Eight Single-Ended Analog Input Channels
Overvoltage Protection on Each Channel
Selection of Input Ranges:

ⴞ5 V, ⴞ10 V for AD7891-1

0 to +2.5 V, 0 to +5 V, ⴞ2.5 V for AD7891-2
Parallel and Serial Interface
On-Chip Track/Hold Amplifier
On-Chip Reference
Single Supply, Low Power Operation (85 mW max)
Power-Down Mode (75 ␮W typ)

APPLICATIONS
Data Acquisition Systems
Motor Control
Mobile Communication Base Stations
Instrumentation

GENERAL DESCRIPTION

The AD7891 is an eight-channel 12-bit data acquisition system
with a choice of either parallel or serial interface structure. The
part contains an input multiplexer, an on-chip track/hold ampli­fier, a high speed 12-bit ADC, a +2.5␣ V reference and a high
speed interface. The part operates from a single +5 V supply
and accepts a variety of analog input ranges across two models,

the AD7891-1 (±5␣ V and ±10␣ V) and the AD7891-2 (0 V to
+2.5 V, 0 V to +5␣ V and ±2.5␣ V).

The AD7891 provides the option of either a parallel interface or
serial interface structure determined by the MODE pin. The
part has standard control inputs and fast data access times for
both the serial and parallel interfaces which ensures easy inter­facing to modern microprocessors, microcontrollers and digital
signal processors.

In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the part is also specified for
dynamic performance parameters including harmonic distortion

PRODUCT HIGHLIGHTS

1. The AD7891 is a complete monolithic 12-bit data acquisition
system combining an eight-channel multiplexer, 12-bit ADC,
+2.5␣ V reference and track/hold amplifier on a single chip.

2. The AD7891-2 features a conversion time of 1.6 µs and an
acquisition time of 0.4␣ µs. This allows a sample rate of

500␣ kSPS when sampling one channel and 62.5 kSPS when
channel hopping. These sample rates can be achieved using
either a software or hardware convert start. The AD7891-1

has an acquisition time of 0.6 µs when using a hardware
convert start and an acquisition time of 0.7 µs when using a

software convert start. These acquisition times allow sample
rates of 454.5 kSPS and 435 kSPS respectively for hardware
and software convert start.

3. Each channel on the AD7891 has overvoltage protection.
This means that an overvoltage on an unselected channel
does not affect the conversion on a selected channel. The

AD7891-1 can withstand overvoltages of ±17 V.

and signal-to-noise ratio.

Power dissipation in normal mode is 90 mW typical while in

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

the standby mode this is reduced to 75 µW typ. The part is

available in a 44-terminal plastic quad flatpack (PQFP) and a
44-lead plastic leaded chip carrier (PLCC).

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

AD7891–SPECIFICATIONS

(VDD = +5 V ⴞ 5%, AGND = DGND = 0 V, REF IN = +2.5 V. All Specifications T
T

unless otherwise noted.)

MAX

MIN

to

ABY

Parameter Version1Version Version Units Test Conditions/Comments

DYNAMIC PERFORMANCE

2

Signal to (Noise + Distortion) Ratio

4

Sample Rate = 454.5 kSPS3 (AD7891-1),
500 kSPS

3

(AD7891-2). Any Channel

@ +25°C 707070dB min

T

to T

MIN

Total Harmonic Distortion
Peak Harmonic or Spurious Noise
Intermodulation Distortion

MAX

4

4

70 70 70 dB min
–78 –78 –78 dB max

4

–80 –80 –80 dB max

fa = 9 kHz, fb = 9.5 kHz
2nd Order Terms –80 –80 –80 dB typ
3rd Order Terms –80 –80 –80 dB typ

Channel-to-Channel Isolation

4

–80 –80 –80 dB max

DC ACCURACY Any Channel

Resolution 12 12 12 Bits
Minimum Resolution for Which

No Missing Codes are Guaranteed 12 12 12 Bits

Relative Accuracy
Differential Nonlinearity
Positive Full-Scale Error
Positive Full-Scale Error Match

4

4

4

±1 ±0.75 ±1 LSB max
±1 ±1 ±1 LSB max
±3 ±3 ±3 LSB max

4, 5

0.6 0.6 0.6 LSB typ 1.5 LSB max

Unipolar Offset Error ±3 ±3 ±3 LSB max Input Ranges of 0 V to +2.5␣ V, 0 V to +5␣ V

Unipolar Offset Error Match
Negative Full-Scale Error
Negative Full-Scale Error Match

5

4

0.1 0.1 0.1 LSB typ 1 LSB max

±3 ±3 ±3 LSB max Input Ranges of ±2.5␣ V, ±5␣ V, ±10␣ V

4, 5

0.6 0.6 0.6 LSB typ 1.5 LSB max

Bipolar Zero Error ±4 ±4 ±4 LSB max Input Ranges of ±2.5␣ V, ±5␣ V, ±10␣ V

Bipolar Zero Error Match

5

0.2 0.2 0.2 LSB typ 1.5 LSB max

ANALOG INPUTS

AD7891-1 Input Voltage Range

AD7891-1 V
AD7891-1 V

±5␣ ±5␣ ±5␣ Volts Input Applied to Both V
±10␣ ±10␣ ±10 Volts Input Applied to V

Input Resistance 7.5 7.5 7.5 kΩ min Input Range of ±5␣ V

INXA

Input Resistance 15 15 15 kΩ min Input Range of ±10␣ V

INXA

INXA

INXA

, V

and V

= AGND

INXB

INXB

AD7891-2 Input Voltage Range

AD7891-2 V
AD7891-2 V

0 to +2.5␣ 0 to +2.5␣ 0 to +2.5␣ ␣ Volts Input Applied to Both V
0 to +5␣ 0 to +5␣ 0 to +5␣ Volts Input Applied to V

±2.5␣ ± 2.5␣ ±2.5␣ Volts Input Applied to V

Input Resistance 1.5 1.5 1.5 kΩ min Input Ranges of ±2.5␣ V and 0 to +5␣ V

INXA

Input Current ±50 ±50 ±50 nA max Input Range of 0 V to +2.5␣ V

INXA

INXA

INXA

INXA

, V
, V

and V

= AGND

INXB

= REF IN

INXB

INXB

6

REFERENCE INPUT/OUTPUT

REF IN Input Voltage Range 2.375/2.625 2.375/2.625 2.375/2.625 V min/V max 2.5 V ± 5%
Input Impedance 1.6 1.6 1.6 kΩ min Resistor Connected to Internal Reference Node

Input Capacitance

5

10 10 10 pF max

REF OUT Output Voltage 2.5 2.5 2.5 V␣ nom

REF OUT Error @ +25°C ±10 ±10 ±10 mV max

T

MIN

to T

MAX

±20 ±20 ±20 mV max
REF OUT Temperature Coefficient 25 25 25 ppm/°C typ
REF OUT Output Impedance 5 5 5 kΩ nom See REF IN Input Impedance

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

INH

Input Capacitance,5 C

INH

IN

2.4 2.4 2.4 V min V

0.8 0.8 0.8 V max V

±10 ±10 ±10 µA max

10 10 10 pF max

= 5 V ± 5%

DD

= 5 V ± 5%

DD

–2– REV. A

AD7891

WARNING!

ESD SENSITIVE DEVICE

ABY

Parameter Version1Version Version Units Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OH

OL

4.0 4.0 4.0 V min I

0.4 0.4 0.4 V max I

DB11–DB0

Floating-State Leakage Current ±10 ±10 ±10 µA max

Floating-State Capacitance

5

15 15 15 pF max

Output Coding

Straight (Natural) Binary Data Format Bit of Control Register = 0
2s Complement Data Format Bit of Control Register = 1

CONVERSION RATE

Conversion Time 1.6 1.6 1.6 µs max
Track/Hold Acquisition Time 0.6 0.6 0.6 µs max AD7891-1 Hardware Conversion

0.7 0.7 0.7 µs max AD7891-1 Software Conversion

0.4 0.4 0.4 µs max AD7891-2

POWER REQUIREMENTS

V

DD

I

DD

+5 +5 +5 V nom ±5% for Specified Performance

Normal Mode 17 17 18 mA max

Standby Mode 80 80 80 µA max Logic Inputs = 0 V or V

Power Dissipation VDD = 5 V

Normal Mode 85 85 90 mW max Typically 70␣ mW

Standby Mode 400 400 400 µW max Typically 75 µW

NOTES

1

Temperature Ranges for the A and B Versions: –40°C to +85°C. Temperature Range for the Y Version: –55°C to +105°C.

2

The AD7891-1’s dynamic performance (THD and SNR) and the AD7891-2’s THD are measured with an input frequency of 10␣ kHz. The AD7891-2’s SNR is
evaluated with an input frequency of 100␣ kHz.

3

This throughput rate can only be achieved when the part is operated in the parallel interface mode. Maximum achievable throughput rate in the serial interface mode
is 357␣ kSPS.

4

See Terminology.

5

Sample tested during initial release and after any redesign or process change that may affect this parameter.

6

REF IN must be buffered before being applied to V

Specifications subject to change without notice.

INXB

.

SOURCE

= 1.6 mA

SINK

= 200 µA

DD

ABSOLUTE MAXIMUM RATINGS*

(T

= +25°C unless otherwise noted)

A

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7␣ V

V

DD

Analog Input Voltage to AGND

AD7891-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±17␣ V

AD7891-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V, +10␣ V

Reference Input Voltage to AGND . . . . –0.3 V to V

Digital Input Voltage to DGND . . . . . . –0.3 V to V

Digital Output Voltage to DGND . . . . . –0.3 V to V

+ 0.3␣ V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Commercial (A, B Version) . . . . . . . . . . . . – 40°C to +85°C

Automotive (Y Version) . . . . . . . . . . . . . . –55°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

PQFP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 95°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

PLCC Package, Power Dissipation . . . . . . . . . . . . . . 500 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 55°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7891 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–3–REV. A

AD7891

TIMING CHARACTERISTICS

1, 2

Parameter A, B, Y Versions Units Test Conditions/Comments

t

CONV

1.6 µs max Conversion Time

Parallel Interface

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

3

t

9

4

t

10

0 ns min CS to RD/WR Setup Time
35 ns min Write Pulsewidth
25 ns min Data Valid to Write Setup Time
5 ns min Data Valid to Write Hold Time
0 ns min CS to RD/WR Hold Time
35 ns min CONVST Pulsewidth
55 ns min EOC Pulsewidth
35 ns min Read Pulsewidth
25 ns min Data Access Time after Falling Edge of RD
5 ns min Bus Relinquish Time after Rising Edge of RD
30 ns max

Serial Interface

t
t
t
t
t
t
t
t

t

11

12

13

14

15

16

17

18

18A

3

3

3

4

4

30 ns min RFS Low to SCLK Falling Edge Setup Time
20 ns max RFS Low to Data Valid Delay
25 ns min SCLK High Pulsewidth
25 ns min SCLK Low Pulsewidth
5 ns min SCLK Rising Edge to Data Valid Hold Time
15 ns max SCLK Rising Edge to Data Valid Delay
20 ns min RFS to SCLK Falling Edge Hold Time
0 ns min Bus Relinquish Time after Rising Edge of RFS
30 ns max
0 ns min Bus Relinquish Time after Rising Edge of SCLK
30 ns max

t

19

t

20

t

21

t

22

NOTES

1

Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1 ns (10% to
90% of +5 V) and timed from a voltage level of +1.6 V.

2

See Figures 2, 3 and 4.

3

Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8␣ V or 2.4␣ V.

4

These times are derived from the measured time taken by the data outputs to change 0.5␣ V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.

Specifications subject to change without notice.

20 ns min TFS Low to SCLK Falling Edge Setup Time
15 ns min Data Valid to SCLK Falling Edge Setup Time
10 ns min Data Valid to SCLK Falling Edge Hold Time
30 ns min TFS Low to SCLK Falling Edge Hold Time

1.6mA

TO

OUTPUT

PIN

50pF

200mA

+1.6V

Figure 1. Load Circuit for Access Time and Bus Relinquish Time

–4– REV. A

AD7891

V

IN6A

AGND

EOC

NC

CONVST
CS

REF GND

NC

REF OUT/REF IN

V

DD

AGND

MODE
DB11/TEST
DB10/TEST

DB9/TFS
DB8/RFS

DB7/DATA IN

STANDBY

V

IN1A

DB6/SCLK

V

DD

DGND

DB5/A2/DATA OUT

DB3/A0

DB2/SWCON

DB1/SWSTBY

DB0/FORMAT

WR

RD

DB4/A1

V

IN1BVIN2AVIN2BVIN3AVIN3BVIN4AVIN4BVIN5AVIN5B

V

IN6B

V

IN7A

V

IN7B

V

IN8A

V

IN8B

NC = NO CONNECT

44 43 42 41 40 39 38 37 36 35 34

1
2
3
4
5
6
7
8

9
10
11

12 13 14 15 16 17 18 19 20 21 22

33
32
31
30
29
28
27
26
25
24
23

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

AD7891 PQFP

ORDERING GUIDE

Model Input Ranges Sample Rate Relative Accuracy Temperature Range Package Options*

AD7891AS-1 ±5 V or ±10 V 454 kSPS ±1 LSB –40°C to +85°CS-44
AD7891AP-1 ±5 V or ±10 V 454 kSPS ±1 LSB –40°C to +85°C P-44A
AD7891BS-1 ±5 V or ±10 V 454 kSPS ±0.75 LSB –40°C to +85°CS-44
AD7891BP-1 ±5 V or ±10 V 454 kSPS ±0.75 LSB –40°C to +85°C P-44A
AD7891YS-1 ±5 V or ±10 V 454 kSPS ±1 LSB –55°C to +105°CS-44
AD7891YP-1 ±5 V or ±10 V 454 kSPS ±1 LSB –55°C to +105°C P-44A
AD7891AS-2 0 V to +5 V, 0 V to +2.5 V 500 kSPS ±1 LSB –40°C to +85°CS-44

or ±2.5 V

AD7891AP-2 0 V to +5 V, 0 V to +2.5 V 500 kSPS ±1 LSB –40°C to +85°C P-44A

or ±2.5 V

AD7891BS-2 0 V to +5 V, 0 V to +2.5 V 500 kSPS ±0.75 LSB –40°C to +85°CS-44

or ±2.5 V

AD7891BP-2 0 V to +5 V, 0 V to +2.5 V 500 kSPS ±0.75 LSB –40°C to +85°C P-44A

or ±2.5 V

AD7891YS-2 0 V to +5 V, 0 V to +2.5 V 500 kSPS ±1 LSB –55°C to +105°CS-44

or ±2.5 V

*S = Plastic Quad Flatpack (PQFP); P = Plastic Leaded Chip Carrier (PLCC).

PIN CONFIGURATIONS

REF GND

REF OUT/REF IN

DB11/TEST
DB10/TEST

DB9/TFS

DB8/RFS

DB7/DATA IN

NC = NO CONNECT

6 5 4 3 2 1 44 43 42 41 40

7
8

NC

9

10

V

DD

11

AGND

12

MODE

13
14
15
16
17

18 19 20 21 22 23 24 25 26 27 28

DB6/SCLK

PLCC

IN1A

IN1BVIN2AVIN2BVIN3AVIN3BVIN4AVIN4BVIN5AVIN5B

STANDBY

V

V

PIN 1
IDENTIFIER

AD7891 PLCC

TOP VIEW

(Not to Scale)

DD

V

DGND

DB3/A0

DB4/A1

DB2/SWCON

DB5/A2/DATA OUT

RD

WR

DB0/FORMAT

DB1/SWSTBY

39
38
37
36
35
34
33
32
31
30
29

V

IN6A

V

IN6B

V

IN7A

V

IN7B

V

IN8A

V

IN8B

AGND

EOC

NC

CONVST
CS

PQFP

–5–REV. A

AD7891

TERMINOLOGY
Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f

/2), excluding dc.

S

The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan­tization noise. The theoretical signal to (noise +distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

Thus for a 12-bit converter, this is 74␣ dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7891 it is defined as:

2

THD dB

()

VVVVV

++++

=

20

223242526

log

V

1

where V1 is the rms amplitude of the fundamental and V2, V3,

, V5 and V6 are the rms amplitudes of the second through the

V

4

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f

/2 and excluding dc) to the rms value of the

S

fundamental. Normally, the value of this specification is deter­mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

The AD7891 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of differ­ent significance. The second order terms are usually distanced
in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa­rately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
fundamental expressed in dBs.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full­scale 20 kHz (AD7891-1) or 100 kHz (AD7891-2) sine wave
signal to one input channel and determining how much that
signal is attenuated in each of the other channels. The figure
given is the worst case across all eight channels.

Relative Accuracy

Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Positive Full-Scale Error (AD7891-1, ±10 V and ±5 V,
AD7891-2, ±2.5 V)

This is the deviation of the last code transition (01. . .110 to

01. . .111) from the ideal 4 × REF IN – 3/2 LSB (AD7891-1
±10 V range), 2 × REF IN – 3/2 LSB (AD7891-1 ± 5 V range)
or REF IN – 3/2 LSB (AD7891-2, ±2.5 V range), after the

Bipolar Zero Error has been adjusted out.

Positive Full-Scale Error (AD7891-2, 0 V to 5 V and 0 V to

2.5 V)

This is the deviation of the last code transition (11. . .110 to

11. . .111) from the ideal 2 × REF IN – 3/2 LSB (0 V to 5 V

range) or REF IN – 3/2 LSB (0 V to 2.5 V range), after the
unipolar offset error has been adjusted out.

Bipolar Zero Error (AD7891-1, ±10 V and ± 5 V, AD7891-2 ,
±2.5 V)

This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal AGND – 1/2 LSB.

Unipolar Offset Error (AD7891-2, 0 V to 5 V and 0 V to 2.5 V)

This is the deviation of the first code transition (00. . .000 to

00. . .001) from the ideal AGND + 1/2 LSB.

Negative Full-Scale Error (AD7891-1, ±10 V and ±5 V,
AD7891-2, ±2.5 V)

This is the deviation of the first code transition (10. . .000 to

10. . .001) from the ideal –4 × REF IN + 1/2 LSB (AD7891-1
±10 V range), –2 × REF IN + 1/2 LSB (AD7891-1 ± 5 V range)
or –REF IN + 1/2 LSB (AD7891-2, ±2.5 V range), after Bipolar

Zero Error has been adjusted out.

Track/Hold Acquisition Time

Track/hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within

±1/2 LSB, after the end of conversion (the point at which the

track/hold returns to track mode). It also applies to situations
where a change in the selected input channel takes place or
where there is a step input change on the input voltage applied
to the selected V

input of the AD7891. It means that the user

IN

must wait for the duration of the track/hold acquisition time
after the end of conversion or after a channel change/step input
change to V

before starting another conversion, to ensure that

IN

the part operates to specification.

–6– REV. A