Analog Devices AD7890SQ-4, AD7890SQ-2, AD7890SQ-10, AD7890BR-4, AD7890BR-2 Datasheet

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LC2MOS 8-Channel, 12-Bit

FEATURES Fast 12-Bit ADC with 5.9 ␮s Conversion Time Eight Single-Ended Analog Input Channels Selection of Input Ranges:

ⴞ10 V for AD7890-10 0 V to 4.096 V for AD7890-4

0 V to 2.5 V for AD7890-2 Allows Separate Access to Multiplexer and ADC On-Chip Track/Hold Amplifier On-Chip Reference High-Speed, Flexible, Serial Interface Single Supply, Low-Power Operation (50 mW Max) Power-Down Mode (75 ␮W Typ)

GENERAL DESCRIPTION

The AD7890 is an eight-channel 12-bit data acquisition system. The part contains an input multiplexer, an on-chip track/hold amplifier, a high-speed 12-bit ADC, a 2.5 V reference and a high speed, serial interface. The part operates from a single 5 V supply and accepts an analog input range of ±10 V (AD7890-10), 0 V to 4.096 V (AD7890-4) and 0 V to 2.5 V (AD7890-2).

The multiplexer on the part is independently accessible. This allows the user to insert an antialiasing filter or signal conditioning, if required, between the multiplexer and the ADC. This means that one antialiasing filter can be used for all eight channels. Connection of an external capacitor allows the user to adjust the time given to the multiplexer settling to include any external delays in the filter or signal conditioning circuitry.

Output data from the AD7890 is provided via a high-speed bidirectional serial interface port. The part contains an on-chip control register, allowing control of channel selection, conversion start and power-down via the serial port. Versatile, high speed logic ensures easy interfacing to serial ports on microcontrollers and digital signal processors.

In addition to the traditional dc accuracy specifications such as linearity, full-scale and offset errors, the AD7890 is also specified for dynamic performance parameters including harmonic distortion and signal-to-noise ratio.

Serial, Data Acquisition System

AD7890

FUNCTIONAL BLOCK DIAGRAM

MUX

SIGNAL

IN1

SCALING*

SIGNAL

IN2

SCALING*

SIGNAL

IN3

SCALING*

SIGNAL

IN4

SCALING*

SIGNAL

IN5

SCALING*

SIGNAL

IN6

SCALING*

SIGNAL

IN7

SCALING*

SIGNAL

IN8

SCALING*

AD7890

AGND

MUX

DGND

Power dissipation in normal mode is low at 30 mW typ and the part can be placed in a standby (power-down) mode if it is not required to perform conversions. The AD7890 is fabricated in Analog Devices’ Linear Compatible CMOS (LC a mixed technology process that combines precision bipolar circuits with low power CMOS logic. The part is available in a 24-lead, 0.3" wide, plastic or hermetic dual-in-line package or in a 24-lead small outline package (SOIC).

PRODUCT HIGHLIGHTS

1. Complete 12-Bit Data Acquisition System-on-a-Chip The AD7890 is a complete monolithic ADC combining an eight-channel multiplexer, 12-bit ADC, 2.5 V reference and a track/hold amplifier on a single chip.

2. Separate Access to Multiplexer and ADC The AD7890 provides access to the output of the multiplexer allowing one antialiasing filter for eight channels—a considerable saving over the eight antialiasing filters required if the multiplexer was internally connected to the ADC.

3. High-Speed Serial Interface The part provides a high-speed serial interface for easy connection to serial ports of microcontrollers and DSP processors.

OUT

TRACK/HOLD

CLOCK

CLK

SHAINREF OUT/

REF IN

2k⍀

REFERENCE

12-BIT

ADC

OUTPUT/CONTROL REGISTER

SCLK

TFS

RFS

DATA

OUT

*NO SCALING ON AD7890-2

2.5V

CONVST

SMODE

DATA

MOS) process,

EXT

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001

AD7890–SPECIFICATIONS

= 5 V, AGND = DGND = 0 V, REF IN = 2.5 V, f

connect to SHA IN. All specifications T

MIN

to T

= 2.5 MHz external, MUX OUT

CLK IN

unless otherwise noted.)

MAX

Parameter A Versions1B Versions S Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE Using External CONVST. Any Channel

Signal to (Noise + Distortion) Ratio Total Harmonic Distortion (THD)2–78 –78 –78 dB max fIN = 10 kHz Sine Wave, f Peak Harmonic or Spurious Noise2–79 –79 –79 dB max fIN = 10 kHz Sine Wave, f Intermodulation Distortion fa = 9 kHz, fb = 9.5 kHz, f

70 70 70 dB min fIN = 10 kHz Sine Wave, f

SAMPLE

= 100 kHz = 100 kHz = 100 kHz

= 100 kHz 2nd Order Terms –80 –80 –80 dB typ 3rd Order Terms –80 –80 –80 dB typ

Channel-to-Channel Isolation

–80 –80 –80 dB max fIN = 1 kHz Sine Wave

DC ACCURACY

Resolution 12 12 12 Bits Minimum Resolution for Which

No Missing Codes Are Guaranteed 12 12 12 Bits

Relative Accuracy Differential Nonlinearity Positive Full-Scale Error Full-Scale Error Match AD7890-2, AD7890-4

Unipolar Offset Error Unipolar Offset Error

AD7890-10 Only

Negative Full-Scale Error Bipolar Zero Error

Match 2 2 2 LSB max

± 1 ± 0.5 ± 1 LSB max ± 1 ± 1 ± 1 LSB max ± 2.5 ± 2.5 ± 2.5 LSB max

2 2 2 LSB max

± 2 ± 2 ± 2 LSB max

± 2 ± 2 ± 2 LSB max ± 5 ± 5 ± 5 LSB max

Bipolar Zero Error Match 2 2 2 LSB max

ANALOG INPUTS

AD7890-10

Input Voltage Range ± 10 ± 10 ± 10 Volts Input Resistance 20 20 20 kΩ min

AD7890-4

Input Voltage Range 0 to 4.096 0 to 4.096 0 to 4.096 Volts Input Resistance 11 11 11 kΩ min

AD7890-2

Input Voltage Range 0 to 2.5 0 to 2.5 0 to 2.5 Volts Input Current 50 50 200 nA max

MUX OUT OUTPUT

Output Voltage Range 0 to 2.5 0 to 2.5 0 to 2.5 Volts Output Resistance

(AD7890-10, AD7890-4) 3/5 3/5 3/5 kΩ min/kΩ max (AD7890-2) 222kΩ max Assuming VIN Is Driven from Low Impedance

SHA IN INPUT

Input Voltage Range 0 to 2.5 0 to 2.5 0 to 2.5 Volts Input Current ± 50 ± 50 ± 50 nA max

REFERENCE OUTPUT/INPUT

REF IN Input Voltage Range 2.375/2.625 2.375/2.625 2.375/2.625 V min/V max 2.5 V ± 5% Input Impedance 1.6 1.6 1.6 kΩ min Resistor Connected to Internal Reference Node Input Capacitance

10 10 10 pF max REF OUT Output Voltage 2.5 2.5 2.5 V nom REF OUT Error @ 25°C ± 10 ± 10 ± 10 mV max

MIN

to T

MAX

± 20 ± 20 ± 25 mV max REF OUT Temperature Coefficient 25 25 25 ppm/°C typ REF OUT Output Impedance 222kΩ nom

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

Input Capacitance, C

INH

INL

2.4 2.4 2.4 V min VDD = 5 V ± 5%

0.8 0.8 0.8 V max VDD = 5 V ± 5%

± 10 ± 10 ± 10 µA max VIN = 0 V to V

10 10 10 pF max

–2–

REV. B

Parameter A Versions1B Versions S Version Unit Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, V Output Low Voltage, V Serial Data Output Coding

AD7890-10 Two’s Complement AD7890-4 Straight (Natural) Binary AD7890-2 Straight (Natural) Binary

CONVERSION RATE

Conversion Time 5.9 5.9 5.9 µs max f

Track/Hold Acquisition Time

POWER REQUIREMENTS

(Normal Mode) 10 10 10 mA max Logic Inputs = 0 V or V

IDD (Standby Mode)6 @ 25°C151515µA typ Logic Inputs = 0 V or V Power Dissipation

Normal Mode 50 50 50 mW max Typically 30 mW Standby Mode @ 25°C 757575µW typ

NOTES

Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.

See Terminology.

This sample rate is only achievable when tiling the part in external clocking mode.

Full-scale error match applies to positive full scale for the AD7890-2 and AD7890-4. It applies to both positive and negative full scale for the AD7890-10.

Sample tested @ 25°C to ensure compliance.

Analog inputs on AD7890-10 must be at 0 V to achieve correct power-down current.

Specifications subject to change without notice.

2, 5

4.0 4.0 4.0 V min I

0.4 0.4 0.4 V max I

222µs max

555V nom± 5% for Specified Performance

= 200 µA

SOURCE

= 1.6 mA

SINK

= 2.5 MHz, MUX OUT

CLK IN

Connected to SHA IN

AD7890

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Analog Input Voltage to AGND

AD7890-10, AD7890-4 . . . . . . . . . . . . . . . . . . . . . . . ±17 V

AD7890-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V, +10 V

Reference Input Voltage to AGND . . . –0.3 V to V

Digital Input Voltage to DGND . . . . . –0.3 V to V

Digital Output Voltage to DGND . . . . –0.3 V to V

+ 0.3 V

Operating Temperature Range

Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 260°C

Cerdip Package, Power Dissipation . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 70°C/W

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Linearity Package

Model Range Error Option*

AD7890AN-2 –40°C to +85°C ± 1 LSB N-24 AD7890BN-2 –40°C to +85°C ± 1/2 LSB N-24 AD7890AR-2 –40°C to +85°C ± 1 LSB R-24 AD7890BR-2 –40°C to +85°C ± 1/2 LSB R-24 AD7890SQ-2 –55°C to +125°C ±1 LSB Q-24 AD7890AN-4 –40°C to +85°C ± 1 LSB N-24 AD7890BN-4 –40°C to +85°C ± 1/2 LSB N-24 AD7890AR-4 –40°C to +85°C ± 1 LSB R-24 AD7890BR-4 –40°C to +85°C ± 1/2 LSB R-24 AD7890SQ-4 –55°C to +125°C ±1 LSB Q-24 AD7890AN-10 –40°C to +85°C ±1 LSB N-24 AD7890BN-10 –40°C to +85°C ± 1/2 LSB N-24 AD7890AR-10 –40°C to +85°C ± 1 LSB R-24 AD7890BR-10 –40°C to +85°C ± 1/2 LSB R-24 AD7890SQ-10 –55°C to +125°C ±1 LSB Q-24

*N = Plastic DIP; Q = Cerdip; R = SOIC.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7890 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. B

–3–

WARNING!

ESD SENSITIVE DEVICE

AD7890

TIMING CHARACTERISTICS

Limit at T

(VDD = 5 V ⴞ 5%, AGND = DGND = 0 V, REF IN = 2.5 V, f

1, 2

connected to SHA IN.)

, T

MIN

MAX

= 2.5 MHz external, MUX OUT

CLK IN

Parameter (A, B, S Versions) Unit Conditions/Comments

CLKIN

100 kHz min Master Clock Frequency. For Specified Performance

2.5 MHz max

CLK IN LO

CLK IN HI

tf t

CONVERT

CST

0.3 × t 0 3 × t

CLK IN

ns min Master Clock Input Low Time

ns min Master Clock Input High Time 25 ns max Digital Output Rise Time. Typically 10 ns 25 ns max Digital Output Fall Time. Typically 10 ns

5.9 µs max Conversion Time 100 ns min CONVST Pulsewidth

Self-Clocking Mode

CLK IN HI

+ 50 ns max RFS Low to SCLK Falling Edge

25 ns max RFS Low to Data Valid Delay t

CLK IN HI

CLK IN LO

ns nom SCLK High Pulsewidth

ns nom SCLK Low Pulsewidth 20 ns max SCLK Rising Edge to Data Valid Delay 40 ns max SCLK Rising Edge to RFS Delay 50 ns max Bus Relinquish Time after Rising Edge of SCLK 0 ns min TFS Low to SCLK Falling Edge t

+ 50 ns max

CLK IN

0 ns min Data Valid to TFS Falling Edge Setup Time (A2 Address Bit) 20 ns min Data Valid to SCLK Falling Edge Setup Time 10 ns min Data Valid to SCLK Falling Edge Hold Time 20 ns min TFS to SCLK Falling Edge Hold Time

External-Clocking Mode

19A

NOTES

Sample tested at –25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

See Figures 8 to 11.

The AD7890 is production tested with f

Specified using 10% and 90% points on waveform of interest.

These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the tim ing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.

20 ns min RFS Low to SCLK Falling Edge Setup Time 40 ns max RFS Low to Data Valid Delay 50 ns min SCLK High Pulsewidth 50 ns min SCLK Low Pulsewidth 35 ns max SCLK Rising Edge to Data Valid Delay 20 ns min RFS to SCLK Falling Edge Hold Time 50 ns max Bus Relinquish Time after Rising Edge of RFS 90 ns max Bus Relinquish Time after Rising Edge of SCLK 20 ns min TFS Low to SCLK Falling Edge Setup Time 10 ns min Data Valid to SCLK Falling Edge Setup Time 15 ns min Data Valid to SCLK Falling Edge Hold Time 40 ns min TFS to SCLK Falling Edge Hold Time

at 2.5 MHz. It is guaranteed by characterization to operate at 100 kHz.

CLK IN

1.6mA

TO OUTPUT

50pF

200␮A

+2.1V

Figure 1. Load Circuit for Access Time and Bus Relinquish Time

–4–

REV. B

AD7890

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

1 AGND Analog Ground. Ground reference for track/hold, comparator and DAC.

2 SMODE Control Input. Determines whether the part operates in its External Clocking (slave) or Self-Clocking

(master) serial mode. With SMODE at a logic low, the part is in its Self-Clocking serial mode with RFS and SCLK as outputs. This Self-Clocking mode is useful for connection to shift registers or to serial ports of DSP processors. With SMODE at a logic high, the part is in its External Clocking serial mode with SCLK and RFS as inputs. This External Clocking mode is useful for connection to the serial port of microcontrollers such as the 8xC51 and the 68HCxx and for connection to the serial ports of DSP processors.

3 DGND Digital Ground. Ground reference for digital circuitry.

EXT

5 CONVST Convert Start. Edge-triggered logic input. A low to high transition on this input puts the track/hold

6 CLK IN Clock Input. An external TTL-compatible clock is applied to this input pin to provide the clock source

7 SCLK Serial Clock Input. In the External Clocking (slave) mode (see Serial Interface section) this is an

8 TFS Transmit Frame Synchronization Pulse. Active low logic input with serial data expected after the

9 RFS Receive Frame Synchronization Pulse. In the External Clocking mode, this pin is an active low logic

10 DATA OUT Serial Data Output. Sixteen bits of serial data are provided with one leading zero, preceding the three

11 DATA IN Serial Data Input. Serial data to be loaded to the control register is provided at this input. The first

12 V

13 MUX OUT Multiplexer Output. The output of the multiplexer appears at this pin. The output voltage range

14 SHA IN Track/Hold Input. The input to the on-chip track/hold is applied to this pin. It is a high impedance

15 AGND Analog Ground. Ground reference for track/hold, comparator and DAC.

16 V

IN1

External Capacitor. An external capacitor is connected to this pin to determine the length of the internal pulse (see CONVST input and Control Register section). Larger capacitances on this pin extend the pulse to allow for settling time delays through an external antialiasing filter or signal conditioning circuitry.

into hold and initiates conversion provided that the internal pulse has timed out (see Control Register section). If the internal pulse is active when the CONVST goes high, the track/hold will not go into hold until the pulse times out. If the internal pulse has timed out when CONVST goes high, the rising edge of CONVST drives the track/hold into hold and initiates conversion.

for the conversion sequence. In the Self-Clocking serial mode, the SCLK output is derived from this CLK IN pin.

externally applied serial clock which is used to load serial data to the control register and to access data from the output register. In the Self-Clocking (master) mode, the internal serial clock, which is derived from the clock input (CLK IN), appears on this pin. Once again, it is used to load serial data to the control register and to access data from the output register.

falling edge of this signal.

input with RFS provided externally as a strobe or framing pulse to access serial data from the output register. In the Self-Clocking mode, it is an active low output which is internally generated and provides a strobe or framing pulse for serial data from the output register. For applications which require that data be transmitted and received at the same time, RFS and TFS should be connected together.

address bits of the Control register and the 12 bits of conversion data. Serial data is valid on the falling edge of SCLK for sixteen edges after RFS goes low. Output coding from the ADC is two’s complement for the AD7890-10 and straight binary for the AD7890-4 and AD7890-2.

five bits of serial data are loaded to the control register on the first five falling edges of SCLK after TFS goes low. Serial data on subsequent SCLK edges is ignored while TFS remains low.

Positive supply voltage, 5 V ± 5%.

from this output is 0 V to 2.5 V for the nominal analog input range to the selected channel. The output impedance of this output is nominally 3.5 kΩ. If no external antialiasing filter is required, MUX OUT should be connected to SHA IN.

input and the input voltage range is 0 V to 2.5 V.

Analog Input Channel 1. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to 4.096 V (AD7890-4) and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1 and A2 bits in the control register. The multiplexer has guaranteed break-beforemake operation.

REV. B

–5–

AD7890

Pin Mnemonic Description

17 V

18 V

19 V

20 V

21 V

22 V

23 V

IN2

IN3

IN4

IN5

IN6

IN7

IN8

24 REF OUT/REF IN Voltage Reference Output/Input. The part can be used with either its own internal reference or with

Analog Input Channel 2. Single-ended analog input. The analog input range on is ±10 V (AD7890-

10), 0 V to 4.096 V (AD7890-4) and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1 and A2 bits in the control register. The multiplexer has guaranteed breakbefore-make operation.

Analog Input Channel 3. Single-ended analog input. The analog input range on is ±10 V (AD7890-

Analog Input Channel 4. Single-ended analog input. The analog input range on is ±10 V (AD7890-

Analog Input Channel 5. Single-ended analog input. The analog input range on is ±10 V (AD7890-

Analog Input Channel 6. Single-ended analog input. The analog input range on is ±10 V (AD7890-

Analog Input Channel 7. Single-ended analog input. The analog input range on is ±10 V (AD7890-

Analog Input Channel 8. Single-ended analog input. The analog input range on is ±10 V (AD7890-

an external reference source. The on-chip 2.5 V reference voltage is provided at this pin. When using this internal reference as the reference source for the part, REF OUT should decoupled to AGND with a 0.1 µF disc ceramic capacitor. The output impedance of this reference source is typically 2 kΩ. When using an external reference source as the reference voltage for the part, the reference source should be connected to this pin. This overdrives the internal reference and provides the reference source for the part. The REF IN input is buffered on-chip. The nominal reference voltage for correct operation of the AD7890 is 2.5 V.

PIN CONFIGURATION

DIP and SOIC

AGND REF OUT/REF IN

SMODE

DGND V

EXT

CONVST

DATA OUT AGND

AD7890

CLK IN V

SCLK V

DATA IN SHA IN

TFS

RFS

TOP VIEW

(Not to Scale)

MUX OUT

IN8

IN7

IN6

IN5

IN4

IN3

IN2

IN1

–6–

REV. B

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