Analog Devices AD7885, AD7884 Datasheet

LC2MOS

±5V F

±5V S

±3V F ±3V S

16-BIT

ACCURATE

DAC

AD7884

TIMER

CONTROL

DGND

CS
RD

BUSY

DB15

V S

REF+

REF+

V F

V

REF–

AGNDS AGNDF

AV

DD

V

SS

GND

DB0

V

INV

CONVST

IN

V

DD

AV

SS

R7

2kΩ

R8

2kΩ

9

9

9

16 16

V

REF–

5kΩ

3kΩ

3kΩ

4kΩ

4kΩ

R1

R2

R3

R4

C1

SW1

R5

SW2

SW3

2kΩ

R6

A1

A2

9-BIT

ADC

LATCH

+

ALU

O
U
T
P
U
T

D
R

I
V
E
R
S

IN

IN IN

±5V F

±5V S

16-BIT

ACCURATE

DAC

AD7885

TIMER

CONTROL

DGND

CS
RD

BUSY

DB7

V S

REF+

V F

REF+

V

REF–

AGNDS AGNDF

AV

DD

V

SS

GND

DB0

V

INV

CONVST

IN

V

DD

AV

SS

R7

2kΩ

R8

2kΩ

9

9

9

16

8

V

REF–

5kΩ

3kΩ

2kΩ

4kΩ

4kΩ

R1

R2

3kΩR3

R4

C1

SW1

R5

SW2

SW3

R6

A1

A2

9-BIT

ADC

LATCH

+

ALU

O
U
T
P
U
T

D
R

I

V
E
R
S

IN

IN

±3V

HBEN

a

16-Bit, High Speed Sampling ADCs

FEATURES
Monolithic Construction
Fast Conversion: 5.3 ms
High Throughput: 166 kSPS
Low Power: 250 mW

APPLICATIONS
Automatic Test Equipment
Medical Instrumentation
Industrial Control
Data Acquisition Systems
Robotics

GENERAL DESCRIPTION

The AD7884/AD7885 is a 16-bit monolithic analog-to-digital
converter with internal sample-and-hold and a conversion time
of 5.3 µs. The maximum throughput rate is 166 kSPS. It uses a
two pass flash architecture to achieve this speed. Two input
ranges are available: ±5 V and ±3 V. Conversion is initiated by
the

CONVST signal. The result can be read into a microproces-

sor using the

CS and RD inputs on the device. The AD7884 has
a 16-bit parallel reading structure while the AD7885 has a byte
reading structure. The conversion result is in 2s complement
code.

The AD7884/AD7885 has its own internal oscillator which con­trols conversion. It runs from ± 5 V supplies and needs a V

REF+

of +3 V.
The AD7884 is available in a 40-pin plastic DIP package and in

a 44-pin PLCC package.
The AD7885 is available in a 28-pin plastic DIP package and

the AD7885A is available in a 44-pin PLCC package.

AD7884/AD7885

FUNCTIONAL BLOCK DIAGRAMS

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

© Analog Devices, Inc., 1995

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

AD7884/AD7885/AD7885A–SPECIFICATIONS

= +3 V; AGND = DGND = GND = 0 V; f

Parameter Version

= 166 kHz. All specifications T

SAMPLE

AB

1, 2, 3

Versions

to T

MIN

1, 2, 3

Units Test Conditions/Comments

, unless otherwise noted.)

MAX

(VDD = +5 V 6 5%, VSS = –5 V 6 5%, V

REF

+S

DC ACCURACY

Resolution 16 16 Bits
Minimum Resolution for Which

No Missing Codes Are Guaranteed 16 16 Bits
Integral Nonlinearity ±0.0075 % FSR max Typically 0.003% FSR
Positive Gain Error ±0.03 ±0.03 % FSR typ AD7885AN/BN: 0.1% typ
Positive Gain Error ±0.05 % FSR max AD7885BN: 0.2% max

Gain TC

4

±2 ±2 ppm FSR/°C typ
Bipolar Zero Error ±0.05 ±0.05 % FSR typ
Bipolar Zero Error ±0.15 % FSR max
Bipolar Zero TC

4

±8 ±8 ppm FSR/°C typ
Negative Gain Error ±0.03 ±0.03 % FSR typ AD7885AN/BN: 0.1% typ
Negative Gain Error ±0.05 % FSR max AD7885BN: 0.2% max

Offset TC

4

±2 ±2 ppm FSR/°C typ
Noise 120 120 µV rms typ 78 µV rms typical in ±3 V Input Range

DYNAMIC PERFORMANCE

Signal to (Noise + Distortion) Ratio 84 84 dB min Input Signal: ±5 V, 1 kHz Sine Wave, Typically 86 dB

82 82 dB typ Input Signal: ±5 V, 12 kHz Sine Wave
Total Harmonic Distortion –88 –88 dB max Input Signal: ±5 V, 1 kHz Sine Wave

–84 –84 dB typ Input Signal: ±5 V, 12 kHz Sine Wave
Peak Harmonic or Spurious Noise –88 –88 dB max Input Signal: ±5 V, 1 kHz Sine Wave
Intermodulation Distortion (IMD)

2nd Order Terms –84 –84 dB typ f

= 11.5 kHz, fB = 12 kHz, f

A

3rd Order Terms –84 –84 dB typ fA = 11.5 kHz, fB = 12 kHz, f

SAMPLE
SAMPLE

= 166 kHz
= 166 kHz

CONVERSION TIME

Conversion Time 5.3 5.3 µs max
Acquisition Time 2.5 2.5 µs max
Throughput Rate 166 166 kSPS max There is an overlap between conversion and acquisition.

ANALOG INPUT

Voltage Range ±5 ±5 Volts

±3 ±3 Volts
Input Current ±4 ±4 mA max

REFERENCE INPUT

Reference Input Current ±5 ±5 mA max V

+ S = +3 V

REF

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

IN

IN

INH

INL

4

2.4 2.4 V min VDD = 5 V ± 5%

0.8 0.8 V max VDD = 5 V ± 5%

±10 ±10 µA max Input Level = 0 V to V

10 10 pF max

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OL

OH

4.0 4.0 V min I

0.4 0.4 V max I

SOURCE

= 1.6 mA

SINK

= 40 µA

DB15–DB0

Floating-State Leakage Current 10 10 µA max
Floating-State Output Capacitance415 15 pF max

POWER REQUIREMENTS

V

DD

V

SS

I

DD

I

SS

+5 +5 V nom ±5% for Specified Performance

–5 –5 V nom ±5% for Specified Performance

35 35 mA max Typically 25 mA

30 30 mA max Typically 25 mA
Power Supply Rejection Ratio

∆Gain/∆V
∆Gain/∆V

DD
SS

86 86 dB typ

86 86 dB typ
Power Dissipation 325 325 mW max Typically 250 mW

NOTES

1

Temperature ranges are as follows: A, B Versions: –40 °C to +85°C.

2

VIN = ±5 V.

3

The AD7885AAP has the same specs as the AD7884AP. The AD7885ABP has the same specs as the AD7884BP.

4

Sample tested to ensure compliance.

Specifications subject to change without notice.

–2–

DD

REV. C

TIMING CHARACTERISTICS

AD7884/AD7885

1, 2

(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4 and 5.)

Limit at +258C Limit at T

MIN

, T

MAX

Parameter (All Versions) (A, B Versions) Units Conditions/Comments

t

1

t

2

t

3

t

4

t

5

2

t

6

3

t

7

50 50 ns min CONVST Pulse Width
100 100 ns max CONVST to BUSY Low Delay
0 0 ns min CS to RD Setup Time
60 60 ns min RD Pulse Width
0 0 ns min CS to RD Hold Time
57 57 ns max Data Access Time after RD
5 5 ns min Bus Relinquish Time after RD
50 50 ns max

t

8

t

9

t

10

t

11

t

12

t

13

t

14

NOTES

1

Timing specifications in bold print are 100% production tested. All other times are sample tested at +5°C to ensure compliance. All input signals are specified
with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

t6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

3

t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrap­olated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
bus relinquish time of the part and as such is independent of external bus loading capacitances.

Specifications subject to change without notice.

40 40 ns min New Data Valid before Rising Edge of BUSY
10 80 ns min HBEN to RD Setup Time
25 25 ns min HBEN to RD Hold Time
60 60 ns min HBEN Low Pulse Duration
60 60 ns min HBEN High Pulse Duration
55 70 ns max Propagation Delay from HBEN Falling to Data Valid
55 70 ns max Propagation Delay from HBEN Rising to Data Valid

, quoted in the Timing Characteristics is the true

7

ORDERING GUIDE

Linearity
Temperature Error SNR Package
Range (% FSR) (dB) Option

2

Model

1

AD7884AN –40°C to +85°C 84 N-40A
AD7884BN –40°C to +85°C ±0.0075 84 N-40A
AD7884AP –40°C to +85°C 84 P-44A
AD7884BP –40°C to +85°C ±0.0075 84 P-44A
AD7885AN –40°C to +85°C 84 N-28A
AD7885BN –40°C to +85°C ±0.0075 84 N-28A
AD7885AAP –40°C to +85°C 84 P-44A
AD7885ABP –40°C to +85°C ± 0.0075 84 P-44A

NOTES

1

Analog Devices reserves the right to ship cerdip (Q) packages in lieu of plastic

DIP (N) packages.

2

N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC).

TO OUTPUT PIN

C

L

100pF

1.6mA

200µA

I

OL

+2.1V

I

OH

Figure 1. Load Circuit for Access Time and Bus Relinquish
Time

REV. C

–3–

AD7884/AD7885

DATA

OLD DATA VALID NEW DATA VALID

BUSY

CONVST

t

1

t

2

t

8

t

CONVERT

t

CS

RD

1

t

2

CONVST

HBEN

BUSY

DATA

RD

t

3

t

CONVERT

Hi-Z

t

1

CS

t

2

t

CONVERT

Hi-Z Hi-Z

CONVST

BUSY

DATA

Figure 2. AD7884 Timing Diagram, Using

CS

t

6

t

4

DATA
VALID

and

RD

t

5

t

7

Hi-Z

Figure 3. AD7884 Timing Diagram, with CS and

RD

Permanently Low

t

9

t

3

t

6

t

4

DATA

VALID

DB0–DB7 DB8–DB15

t

10

t

5

t

7

DATA
VALID

Hi-Z

Figure 4. AD7885 Timing Diagram, Using CS and

t

CONVST

HBEN

BUSY

DATA

1

t

2

OLD DATA VALID

(DB8 – DB15)

Figure 5. AD7885 Timing Diagram, with CS and RD Permanently Low

RD

t

11

t

CONVERT

t

8

NEW DATA VALID

(DB8 – DB15)

–4–

t

13

NEW DATA VALID

(DB0 – DB7)

t

t

14

NEW DATA VALID

12

(DB8 – DB15)

NEW DATA VALID

(DB0 – DB7)

REV. C

AD7884/AD7885

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V

SS

AV

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to –7 V

SS

AGND Pins to DGND . . . . . . . . . . . . –0.3 V to V

AV

DD

AV

to V

SS

to V

2

. . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

2

. . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V

SS

GND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V

V

S, VINF to AGND . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V

IN

V

to AGND . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V

REF+

V

to AGND . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V

REF–

V

to AGND . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V

INV

Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V

Digital Outputs to DGND . . . . . . . . . . –0.3 V to V

1

Operating Temperature Range

Commercial Plastic (A, B Versions) . . . . . –40°C to +85°C

Industrial Cerdip (A, B Versions) . . . . . . . . –40°C to +85°C

Extended Cerdip (T Versions) . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

+ 0.3 V

DD

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C

Power Dissipation (Any Package) to +75°C . . . . . . . 1000 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

1

Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2

If the AD7884/AD7885 is being powered from separate analog and digital supplies,
AVSS should always come up before VSS. See Figure 12 for a recommended
protection circuit using Schottky diodes.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATIONS

DIP

F

S

S

IN

IN

IN

±5V

±3V

V

INV

V

REF–

±3V S

IN

±3V F

IN

±5V S

IN

±5V F

IN

AGNDS

AGNDF

AV

AV

GND

GND

V
V

V

CONVST

CS

RD

V

BUSY

DD

SS

SS

SS

DD

SS

1

2
3

4

5

6

7

8
9

10

11
12

13
14

15

16

17

18
19

20

AD7884

TOP VIEW

(Not to Scale)

V

40

V S

REF+

V F

39

REF+

38

DB15

37

DB14

DB13

36

DB12

35

34

DB11

DB10

33
32

DB9

DB8

31

DGND

30

V

DB7
DB6

DB5

DB4

DB3

DB2
DB1

DB0

CONVST

DD

29

28
27

26

25

24

23
22

21

REF–

±3V

±5V S

IN

±5V F

IN

AGNDS

AGNDF

AV

AV

GND

V

V

CS
RD

DD

SS

SS

DD

IN

1

2
3

4

5

6

7

8
9

10

11

12

13
14

AD7885

TOP VIEW

(Not to Scale)

V

28

INV

27

V S

REF+

26

V F

REF+

DB7

25

24

DB6

DB5

23

DB4

22

DGND

21
20

DB3

DB2

19

DB1

18

DB0

17

16

BUSY
HBEN

15

±5VINF
AGNDS
AGNDF

AV

AV

GND
GND

±5VINF

AGNDS
AGNDF

AV
AV

GND
GND

7
8
9

10

DD

11

SS

12

NC

13
14

V

15

SS

V

16

SS

V

17

DD

7
8
9

10

DD

SS

11

NC

12
13
14

V

15

SS

V

16

SS

V

17

DD

±3V

18 19 20 21 22 23 24 25 26 27 28

CONVST

S

±5V

18 19 20 21 22 23 24

CS

F

IN

±3V

CS

CONVST

SS

RD

V

S

IN

IN

±3V

RD

HBEN

PLCC

INVVREF

NC

V

21443456 42 41 4043

AD7884

TOP VIEW

(Not to Scale)

NC

BUSY

INVVREF

NC

V

21443456 42 41 4043

AD7885A

TOP VIEW

(Not to Scale)

NC

BUSY

S

F

REF+

REF+

V

V

DB1

DB0

NC = NO CONNECT

S

F

REF+

REF+

V

V

25 26 27 28

NCNCNC

NC = NO CONNECT

DB15

DB2

DB14

DB3

NC

DB13

DB4

NCNCNC

DB0

DB12

39

DB11

38
37

DB10

36

DB9

35

DB8
NC

34

DGND

33

V

DD

32

DB7

31

DB6

30

DB5

29

DB7

39

DB6

38

NC

37
36

DB5

35

DB4

34

NC

33

DGND
V

32

DD

DB3

31

DB2

30

DB1

29

REV. C

–5–