Analog Devices AD7872, AD7871 Datasheet

LC2MOS

a

FEATURES
Complete Monolithic 14-Bit ADC
2s Complement Coding
Parallel, Byte and Serial Digital Interface
80 dB SNR at 10 kHz Input Frequency
57 ns Data Access Time
Low Power—50 mW typ
83 kSPS Throughput Rate
16-Lead SOIC (AD7872)

APPLICATIONS
Digital Signal Processing
High Speed Modems
Speech Recognition and Synthesis
Spectrum Analysis
DSP Servo Control

GENERAL DESCRIPTION

The AD7871 and AD7872 are fast, complete, 14-bit analog-to­digital converters. They consist of a track/hold amplifier,
successive-approximation ADC, 3 V buried Zener reference and
versatile interface logic. The ADC features a self-contained, laser
trimmed internal clock, so no external clock timing components
are required. The on-chip clock may be overridden to synchronize
ADC operation to the digital system for minimum noise.

The AD7871 offers a choice of three data output formats: a sin­gle, parallel, 14-bit word; two 8-bit bytes or a 14-bit serial data
stream. The AD7872 is a serial output device only. The two
parts are capable of interfacing to all modern microprocessors
and digital signal processors.

The AD7871 and AD7872 operate from ± 5 V power supplies,
accept bipolar input signals of ± 3 V and can convert full power
signals up to 41.5 kHz.

In addition to the traditional dc accuracy specifications, the
AD7871 and AD7872 are also fully specified for dynamic perfor­mance parameters including distortion and signal-to-noise ratio.

Both devices are fabricated in Analog Devices’ LC
technology process. The AD7871 is available in 28-pin plastic DIP
and PLCC packages. The AD7872 is available in a 16-pin plastic
DIP, hermetic DIP and 16-lead SOIC packages.

2

MOS mixed

Complete 14-Bit, Sampling ADCs

AD7871/AD7872

FUNCTIONAL BLOCK DIAGRAMS

PRODUCT HIGHLIGHTS

1. Complete 14-Bit ADC on a Chip.

2. Dynamic Specifications for DSP Users.

3. Low Power.

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND =
O V, f

AD7871/AD7872–SPECIFICATIONS

= 2 MHz external, f

CLK

noted.) All Specifications T

= 83 kHz unless otherwise

SAMPLE

to T

MIN

unless otherwise noted.

MAX

J, A K T, B

Parameter Versions1Version1Versions1Units Test Conditions/Comments

INL

IN

INH

5

OL

OH

2

80 80 79 dB min SNR is Typically 82 dB for <VIN<41.5 kHz;

= 10 kHz Sine Wave

IN

–85 dB typ

= 10 kHz.

IN

–85 dB typ

= 50 kHz

SAMPLE

–85 dB typ

= 50 kHz

SAMPLE

–85 dB typ

±12 ±12 ±12 LSB max
±12 ±12 ±12 LSB max

2.98/3.02 2.98/3.02 2.98/3.02 V min/V max

Reference Load Should Not Be Changed During
Conversion

2.4 2.4 2.4 V min VDD = 5 V ± 5%

0.8 0.8 0.8 V max VDD = 5 V ± 5%
±10 ±10 ±10 µA max VIN = 0 V to V

DD
DD

10 10 10 pF max

4.0 4.0 4.0 V min I

0.4 0.4 0.4 V max I

SOURCE

= 1.6 mA

SINK

= 40 µA

+5 +5 +5 V nom ±5% for Specified Performance
–5 –5 –5 V nom ±5% for Specified Performance
13 13 13 mA max Typically 6 mA
6 6 6 mA max Typically 4 mA

–2–

REV. D

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio3 (SNR) @ +25°C 80 80 79 dB min VIN = 10 kHz Sine Wave

T

to T

MIN

MAX

Total Harmonic Distortion (THD) –86 –88 dB max V

Peak Harmonic or Spurious Noise –86 –88 dB max V

Intermodulation Distortion (IMD)

Second Order Terms –86 –88 dB max fa = 9 kHz, fb = 9.5 kHz, f

Third Order Terms –86 –88 dB max fa = 9 kHz, fb = 9.5 kHz, f

Track/Hold Acquisition Time 2 2 2 µs max

DC ACCURACY

Resolution 14 14 14 Bits
Minimum Resolution for Which

No Missing Codes Are Guaranteed 14 14 14 Bits
Integral Nonlinearity @ +25°C ±1/2 ±1/2 LSB typ
Integral Nonlinearity ±1 ±1 LSB max
Bipolar Zero Error ±12 ±12 ±12 LSB max
Positive Gain Error
Negative Gain Error

4

4

ANALOG INPUT

Input Voltage Range ± 3 ±3 ±3 Volts
Input Current ±500 ±500 ±500 µA max

REFERENCE OUTPUT

REF OUT @ +25°C 2.99/3.01 2.99/3.01 2.99/3.01 V min/V max

T

to T

MIN

MAX

REF OUT Tempco ±40 ±40 ppm/°C max Typically 35 ppm
Reference Load Sensitivity

(∆REF OUT/∆I) ±1.2 ±1.2 ±1.2 mV max Reference Load Current Change (0 µA–300 µA);

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

IN

Input Current (14/8/CLK Input Only) ±10 ±10 ±10 µA max VIN = VSS to V
Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V
DB13 – DB0

Floating-State Leakage Current 10 10 10 µA max

Floating-State Output Capacitance515 15 15 pF max

CONVERSION TIME

External Clock 10 10 10 µs max
Internal Clock 10.5 10.5 11 µs max The Internal Clock Has a Nominal Value of 2 MHz

POWER REQUIREMENTS

V

DD

V

SS

I

DD

I

SS

Power Dissipation 95 95 95 mW max Typically 50 mW

NOTES

1

Temperature ranges are as follows: J, K versions, 0°C to +70°C; A, B versions, –40 °C to +85 °C; T version; –55 °C to +125 °C.

2

VIN = ±3 V.

3

SNR calculation includes distortion and noise components.

4

Measured with respect to internal reference.

5

Sample tested @ +25°C to ensure compliance.

Specifications subject to change without notice.

TIMING CHARACTERISTICS

WARNING!

ESD SENSITIVE DEVICE

AD7871/AD7872

1, 2

(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = O V. See Figures 9, 10, 11 and 12.)

Parameter (J, K, A, B Versions) (T Version) Units Conditions/Comments

t
t
t
t
t
t
t

t
t
t
t
t
t

t
t

t
t
t
t
t

NOTES

1

Timing Specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

Serial timing is measured with a 4.7 kΩ pull-up resistor on SDATA and SSTRB and a 2 kΩ pull-up resistor on SCLK. The capacitance on all three outputs is 35 pF.

3

t6 and t17 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

4

t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of bus loading.

5

SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.

6

SDATA will drive higher capacitive loads, but this will add to t12 since it increases the external RC time constant (4.7 k Ω//CL) and hence the time to reach 2.4 V.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

SS

AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V

V

IN

REF OUT, C

Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V

Digital Outputs to DGND . . . . . . . . . . –0.3 V to V

Operating Temperature Range

Commercial (J, K Versions) . . . . . . . . . . . . . .0°C to +70°C

Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C

Extended (T Version) . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C

Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7871/AD7872 features proprietary ESD protection circuitry, permanent dam­age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. D

Limit at T

1
2
3
4
5

3

6

4

7

50 50 ns min CONVST Pulse Width
0 0 ns min CS to RD Setup Time (Mode 1)
60 75 ns min RD Pulse Width
0 0 ns min CS to RD Hold Time (Mode 1)
70 70 ns min RD to INT Delay

57 70 ns max Data Access Time after RD
55 ns min Bus Relinquish Time after RD

MIN

, T

MAX

Limit at T

MIN

, T

MAX

50 50 ns max

8
9
10

5

11

6

12
13

0 0 ns min HBEN to RD Setup Time
0 0 ns min HBEN to RD Hold Time
100 100 ns min SSTRB to SCLK Falling Edge Setup Time
440 440 ns min SCLK Cycle Time
155 155 ns max SCLK to Valid Data Delay. CL = 35 pF
140 150 ns max SCLK Rising Edge to SSTRB
20 20 ns min

14

4 4 ns min Bus Relinquish Time after SCLK
100 100 ns max

15
16

3

17
18
19
20

60 60 ns min CS to RD Setup Time (Mode 2)
120 120 ns max CS to BUSY Propagation Delay
200 200 ns min Data Setup Time Prior to BUSY
0 0 ns min CS to RD Hold Time (Mode 2)
0 0 ns min HBEN to CS Setup Time
0 0 ns min HBEN to CS Hold Time

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V

+ 0.3 V

to AGND . . . . . . . . . . . . . . . . V

to AGND . . . . . . . . . . . . . . . . . . 0 V to V

REF

–0.3 V to VDD + 0.3 V

SS

DD

+ 0.3 V

DD

DD

–3–

, quoted in the Timing Characteristics is the true bus relinquish

7

Figure 1. Load Circuit for Access Time

Figure 2. Load Circuit for Output Float Delay

AD7871/AD7872

AD7871 PIN FUNCTION DESCRIPTION

DIP
No. Mnemonic Function

1 CONVST Convert Start. A low to high transition on this input puts the track/hold into the hold mode. This

input is asynchronous to the CLK.

CS Chip Select. Active low logic input. The device is selected when this input is active. With CONVST

2

tied low, a new conversion is initiated when

RD Read. Active low logic input. This input is used in conjunction with CS low to enable the data outputs.

3
4 BUSY/INT Busy/Interrupt. Logic low output indicating converter status. See timing diagrams.
5 CLK Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying

this pin to VSS enables the internal laser-trimmed oscillator.

6 DB13/HBEN Data Bit 13 (MSB)/High Byte Enable. The function of this pin is dependent on the state of the

14/

8/CLK input (see Pin 28). When 14-bit data is selected, this pin provides the DB13 output. When
either byte or serial data is selected, this pin becomes the HBEN logic input. HBEN is used for 8-bit
bus interfacing. When HBEN is low, DB7 to DB0 is the lower byte of data. With HBEN high, DB7
to DB0 is the upper byte of data (see Table I).

Table I. Byte Output Format

HBEN DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
HIGH LOW LOW DB13 DB12 DB11 DB10 DB9 DB8

LOW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CS and RD must be held high for the duration of this pulse.

CS goes low.

7 DB12/

SSTRB Data Bit 12/Serial Strobe. When 14-bit data is selected, this pin provides the DB12 data output.

Otherwise it is an active low three-state output that provides a framing pulse for serial data.

8 DB11/SCLK Data Bit 11/Serial Clock. When 14-bit data is selected, this pin provides the DB11 data output.

Otherwise SCLK is the gated serial clock output that is derived from the internal or external ADC
clock. If the 14/

8/CLK input is held at –5 V, then the SCLK runs continuously. With 14/8/CLK at

0 V, it is gated off (three-state) after serial transmission is complete.

9 DB10/SDATA Data Bit 10/Serial Data. When 14-bit parallel data is selected, this pin provides the DB10 data

output. Otherwise it is the three-state serial data output used in conjunction with SCLK and
in serial data transmission. Serial data is valid on the falling edge of SCLK, when

10–13 DB9–DB6 Three-State Data Outputs controlled by

14/

8/CLK and the HBEN inputs. With 14/8/CLK high, they are always DB9–DB6; with 14/8/CLK

CS and RD. Their function depends on the state of the

SSTRB is low.

SSTRB

low, their function depends on HBEN (see Table I).
14 DGND Digital Ground. Ground return for digital circuitry.
15–20 DB5/DB13– Three-State Data Outputs controlled by CS and RD. Their function depends on the 14/8/CLK

DB0/DB8 and HBEN inputs. With 14/

8/CLK high, they are always DB5–DB0; with 14/8/CLK low or –5 V,

their function is controlled by HBEN (see Table I).
21 V

DD

Positive Supply, +5 V ± 5%.
22 AGND Analog Ground. Ground reference for analog circuitry.
23 C

REF

Decoupling point for on-chip reference. Connect 10 nF between this pin and AGND.
24 NC No Connect.
25 REF OUT Voltage Reference Output. The internal 3 V reference is provided at this pin. The external load

capability is 500 µA.
26 V
27 V
28 14/

IN
SS

8/CLK Three-Function Input. Defines both the parallel and serial data formats. With this pin at +5 V, the

Analog Input. The input range is ± 3 V.

Negative Supply, –5 V ± 5%.

output data is 14-bit parallel only. With this pin at 0 V, both byte and serial data are available, and

the SCLK is noncontinuous. With this pin at –5 V, both byte and serial data are available and the

SCLK is continuous.

–4–

REV. D

AD7871/AD7872

AD7872 PIN FUNCTION DESCRIPTION

DIP
No. Mnemonic Function

1 CONTROL Control Input. With this pin at 0 V, the SCLK is noncontinuous; with this pin at –5 V, the SCLK

is continuous.

2

3 CLK Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying

4

5 SCLK Serial Clock. SCLK is the gated serial clock output derived from the internal or external ADC

6 SDATA Serial Data. This is the three-state serial data output used in conjunction with SCLK and

7 NC No Connect.
8 DGND Digital Ground. Ground return for digital circuitry.
9V
10 NC No Connect.
11 C
12 AGND Analog Ground. Ground reference for analog circuitry.
13 REF OUT Voltage Reference Output. The internal 3 V reference is provided at this pin. The external load

14 V
15 V
16 V

CONVST Convert Start. A low to high transition on this input puts the track/hold into the hold mode. This

input is asynchronous to the CLK.

this pin to V

, enables the internal laser-trimmed oscillator.

SS

SSTRB This is an active low three-state output that provides a framing pulse for serial data. An external

4.7 kΩ pull-up resistor is required on

clock. If the 14/

8/CLK input is at –5 V, then the SCLK runs continuously. With CONTROL

SSTRB.

at 0 V, it is gated off (three-state) after serial transmission is complete. SCLK is an open-drain
output and requires an external 2 kΩ pull-up resistor.

SSTRB in

serial data transmission. Serial data is valid on the falling edge of SCLK, when

SSTRB is low. An

external 4.7 kΩ pull-up resistor is required on SDATA.

DD

REF

Positive Supply for analog circuitry, +5 V ± 5%.

Decoupling point for on-chip reference. Connect 10 nF capacitor between this pin and AGND.

capability is 500 µA.

IN
SS
DD

Analog Input. The input range is ± 3 V.
Negative Supply, –5 V ± 5%.
Positive Supply for analog circuitry, +5 V ± 5%. Pin 16 and Pin 9 should be connected together.

REV. D

PIN CONFIGURATIONS

DIP DIP, SOIC PLCC

–5–