Analog Devices AD7866CB, AD7866ARU, AD7866BRU Datasheet

Dual 1 MSPS, 12-Bit, 2-Channel

a

FEATURES
Dual 12-Bit, 2-Channel ADC
Fast Throughput Rate

1 MSPS
Specified for V
Low Power

11.4 mW Max at 1 MSPS with 3 V Supplies

24 mW Max at 1 MSPS with 5 V Supplies
Wide Input Bandwidth

70 dB SNR at 300 kHz Input Frequency
Onboard Reference 2.5 V
Flexible Power/Throughput Rate Management
Simultaneous Conversion/Read
No Pipeline Delays
High-Speed Serial Interface SPI

MICROWIRE
Shut-Down Mode

1 ␮A Max
20-Lead TSSOP Package

of 2.7 V to 5.25 V

DD

TM

/DSP Compatible

TM

/QSPITM/

SAR ADC with Serial Interface

AD7866

FUNCTIONAL BLOCK DIAGRAM

BUF

T/H

T/H

BUF

D

AAV

CAP

REF SELECT

12-BIT

SUCCESSIVE-

APPROXIMATION

ADC

CONTROL

LOGIC

12-BIT

SUCCESSIVE-

APPROXIMATION

ADC

D

B

CAP

AD7866

DGND

DDDVDD

OUTPUT

DRIVERS

OUTPUT

DRIVERS

D

A0
RANGE
SCLK

CS

V

D

V

A1

V

A2

V

B1

V

B2

V

REF

2.5V
REF

MUX

MUX

AGND AGND

OUT

DRIVE

OUT

A

B

GENERAL DESCRIPTION

The AD7866 is a dual 12-bit high-speed, low power, successive­approximation ADC. The part operates from a single 2.7 V to 5.25 V
power supply and features throughput rates up to 1 MSPS. The
device contains two ADCs, each preceded by a low-noise, wide
bandwidth track/hold amplifier which can handle input frequencies
in excess of 10 MHz.

The conversion process and data acquisition are controlled
using standard control inputs allowing easy interfacing to
microprocessors or DSPs. The input signal is sampled on the
falling edge of CS and conversion is also initiated at this point.
The conversion time is determined by the SCLK frequency.
There are no pipelined delays associated with the part.

The AD7866 uses advanced design techniques to achieve very low
power dissipation at high throughput rates. With 3 V supplies
and 1 MSPS throughput rate, the part consumes a maximum of

3.8 mA. With 5 V supplies and 1 MSPS, the current consumption
is a maximum of 4.8 mA. The part also offers flexible power/
throughput rate management when operating in sleep mode.

The analog input range for the part can be selected to be a 0 V
to V

range or a 2 × V

REF

range with either straight binary or

REF

two’s complement output coding. The AD7866 has an
on-chip 2.5 V reference which can be overdriven if an external

SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

reference is preferred. Each on-board ADC can also be supplied
with a separate individual external reference.

The AD7866 is available in a 20-lead thin shrink small outline
(TSSOP) package.

PRODUCT HIGHLIGHTS

1. The AD7866 features two complete ADC functions allowing
simultaneous sampling and conversion of two channels. Each
ADC has a 2-channel input multiplexer. The conversion
result of both channels is available simultaneously on separate
data lines, or both may be taken on one data line if only one
serial port is available.

2. High Throughput with Low Power Consumption—The
AD7866 offers a 1 MSPS throughput rate with 11.4 mW
maximum power consumption when operating at 3 V.

3. Flexible Power/Throughput Rate Management—The
conversion rate is determined by the serial clock allowing
the power consumption to be reduced as the conversion time
is reduced through a SCLK frequency increase. Power
efficiency can be maximized at lower throughput rates if the
part enters sleep during conversions.

4. No Pipeline Delay—The part features two standard successive­approximation ADCs with accurate control of the sampling
instant via a CS input and once off conversion control.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

AD7866–SPECIFICATIONS

(TA = T

1

External on D

MIN

to T

, VDD = 2.7 V to 5.25 V, V

MAX

A and D

CAP

CAP

= 2.7 V to 5.25 V, Reference = 2.5 V

DRIVE

B, f

= 20 MHz, unless otherwise noted.)

SCLK

Parameter A Version1B Version1Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal to Noise + Distortion (SINAD)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)

2

2

2

68 68 dB min fIN = 300 kHz Sine Wave, fS = 1 MSPS
–75 –75 dB max f

2

–76 –76 dB max fIN = 300 kHz Sine Wave, fS = 1 MSPS

= 300 kHz Sine Wave, fS = 1 MSPS

IN

Second Order Terms –88 –88 dB typ
Third Order Terms –88 –88 dB typ
Channel to Channel Isolation –88 –88 dB typ

SAMPLE AND HOLD

Aperture Delay
Aperture Jitter
Aperture Delay Matching

3

3

3

10 10 ns max
50 50 ps typ
200 200 ps max

Full Power Bandwidth 12 12 MHz typ @ 3 dB

2 2 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 12 12 Bits
Integral Nonlinearity ± 1.5 ± 1LSB max

± 1.5 LSB max
Differential Nonlinearity –0.95/+1.25 –0.95/+1.25 LSB max
0 V to V

Input Range

REF

B Grade, 0 V to V
0 V to 2 × V

range only; ±0.5 LSB typ

REF

range; ± 0.5

REF

LSB
Guaranteed No Missed Codes to 12 Bits
Straight Binary Output Coding

Offset Error ± 8 ± 8LSB max
Offset Error Match ± 1.2 ± 1.2 LSB typ
Gain Error ± 2.5 ± 2.5 LSB max
Gain Error Match ± 0.2 ± 0.2 LSB typ

2 × V

Input Range –V

REF

REF

to +V

Biased about V

REF

Positive Gain Error ± 2.5 ± 2.5 LSB max Two’s Complement Output Coding
Zero Code Error ± 8 ± 8LSB max
Zero Code Error Match ± 0.2 ± 0.2 LSB typ
Negative Gain Error ± 2.5 ± 2.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

0 to 2 × V

REF

REF

0 to V

REF

0 to 2 × V

V RANGE Pin Low upon CS Falling Edge
V RANGE Pin High upon CS Falling Edge

REF

DC Leakage Current ± 500 ± 500 nA max
Input Capacitance 30 30 pF typ When in Track

10 10 pF typ When in Hold

REFERENCE INPUT/OUTPUT

Reference Input Voltage 2.5 2.5 V ± 1% for Specified Performance
Reference Input Voltage Range
DC Leakage Current ± 30 ±30 µA max V

Input Capacitance 20 20 pF typ
Reference Output Voltage

Output Impedance

V

REF

4

5

6

2/3 2/3 V min/V max REF SELECT Pin Tied High

Pin;

± 160 ± 160 µA max D

REF

CAP

A, D

CAP

B Pins;

2.45/2.55 2.45/2.55 V min/V max
25 25 Ω typ VDD = 5 V
45 45 Ω typ V

DD

= 3 V
Reference Temperature Coefficient 50 50 ppm/°C typ
REF OUT Error (T

MIN

to T

) ±15 ± 15 mV typ

MAX

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

3

0.7 V

DRIVE

0.3 V

DRIVE

± 1 ± 1 µA max Typically 15 nA, V
10 10 pF max

0.7 V

0.3 V

DRIVE

DRIVE

V min
V max

= 0 V or V

IN

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ±1 ± 1 µA max V
Floating-State Output Capacitance

OH

OL

3

V

DRIVE

– 0.2 V

– 0.2 V min I

DRIVE

0.4 0.4 V max I

10 10 pF max

= 200 µA

SOURCE

= 200 µA

SINK

= 2.7 V to 5.25 V

DD

Output Coding Straight (Natural) Binary Selectable with Either Input Range

Two’s Complement

REF

DRIVE

typ

with

–2–

REV. 0

AD7866

Parameter A Version1B Version1Unit Test Conditions/Comments

CONVERSION RATE

Conversion Time 16 16 SCLK cycles 800 ns with SCLK = 20 MHz
Track/Hold Acquisition Time
Throughput Rate 1 1 MSPS max See Serial Interface Section

POWER REQUIREMENTS

V

DD

V

DRIVE

7

I

DD

Normal Mode (Static) 3.1 3.1 mA max VDD = 4.75 V to 5.25 V. Add 0.5 mA

Operational, f

= 1 MSPS 4.8 4.8 mA max VDD = 4.75 V to 5.25 V. Add 0.5 mA

S

Partial Power-Down Mode 1.6 1.6 mA max f

Partial Power-Down Mode 560 560 µA max (Static) Add 100 µA Typical if Using Internal

Full Power-Down Mode 1 1 µA max SCLK On or Off.

Power Dissipation

7

Normal Mode (Operational) 24 24 mW max VDD = 5 V

Partial Power-Down (Static) 2.8 2.8 mW max V

Full Power-Down (Static) 5 5 µW max V

NOTES

1

Temperature ranges as follows: A, B Versions: –40°C to +85°C.

2

See Terminology section.

3

Sample tested @ 25°C to ensure compliance.

4

External reference range that may be applied at V

5

Relates to pins V

6

See Reference section for D

7

See Power Versus Throughput Rate section.

Specifications subject to change without notice.

REF

, D

CAP

A, or D

CAP

3

B.

CAP

A, D

B output impedances.

CAP

300 300 ns max

2.7/5.25 2.7/5.25 V min/max

2.7/5.25 2.7/5.25 V min/max
Digital I/Ps = 0 V or V

Typical if Using Internal Reference

2.8 2.8 mA max V

= 2.7 V to 3.6 V. Add 0.35 mA

DD

Typical if Using Internal Reference

Typical if Using Internal Reference

3.8 3.8 mA max V

= 2.7 V to 3.6 V. Add 0.5 mA

DD

Typical if Using Internal Reference

= 100 kSPS, f

S

SCLK

Add 0.2 mA Typ if Using Internal Reference

Reference

11.4 11.4 mW max V

1.68 1.68 mW max V

= 3 V

DD

= 5 V. SCLK On or Off.

DD

= 3 V. SCLK On or Off.

DD

= 5 V. SCLK On or Off.

DD

33 µW max VDD = 3 V. SCLK On or Off.

, D

REF

CAP

A, or D

CAP

B.

DRIVE

= 20 MHz

REV. 0

–3–

AD7866

WARNING!

ESD SENSITIVE DEVICE

TIMING SPECIFICATIONS

1

(VDD = 2.7 V to 5.25 V, V

= 2.7 V to 5.25 V, V

DRIVE

= 2.5 V; TA = T

REF

MIN

to T

, unless otherwise noted.)

MAX

Limit at

Parameter T

2

f

SCLK

MIN

, T

MAX

Unit Description

10 kHz min
20 MHz max

t

CONVERT

16 × t

SCLK

800 ns max f

t

QUIET

t

2

3

t

3

3

t

4

t

5

t

6

t

7

4

t

8

4

t

9

50 ns max Minimum Time Between End of Serial Read and Next Falling Edge of CS
10 ns min CS to SCLK Setup Time
25 ns max Delay from CS Until D
40 ns max Data Access Time After SCLK Falling Edge. V

0.4 t

SCLK

0.4 t

SCLK

10 ns min SCLK to Data Valid Hold Time
25 ns max CS Rising Edge to D
10 ns min SCLK Falling Edge to D
50 ns max SCLK Falling Edge to D

NOTES

1

Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V

2

Mark/Space ratio for the CLK input is 40/60 to 60/40.

3

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.

4

t

are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated

8, t9

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times t
relinquish times of the part and are independent of the bus loading.

Specifications subject to change without notice.

ns max t

= 1/f

SCLK

SCLK

V

DRIVE

SCLK

= 20 MHz

< 3 V, CL = 25 pF
ns min SCLK Low Pulsewidth
ns min SCLK High Pulsewidth

OUT

A and D

OUT

A, D

OUT

A, D

OUT

A, D

OUT

and t9 quoted in the timing characteristics are the true bus

8

B Three-State Disabled

OUT

DRIVE

B, High Impedance

B, High Impedance

OUT

B, High Impedance

OUT

) and timed from a voltage level of 1.6 V.

DRIVE

ⱖ 3 V, CL = 50 pF;

200␮AI

TO

OUTPUT

PIN

C

L

50pF

200␮A

Figure 1. Load Circuit for Digital Output
Timing Specifications

ABSOLUTE MAXIMUM RATINGS

(TA = 25oC unless otherwise noted)

AV

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

DV

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

to DGND . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V

V

DRIVE

V

to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

DRIVE

AV

to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

DD

1

AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Analog Input Voltage to AGND . . . . –0.3 V to AV

+ 0.3 V

DD

Digital Input Voltage to DGND . . . . . . . . . . . –0.3 V to +7 V

to AGND . . . . . . . . . . . . . . . . . –0.3 V to AV

V

REF

Digital Output Voltage to DGND . . –0.3 V to V
Input Current to Any Pin Except Supplies

2

. . . . . . . . ± 10 mA

Operating Temperature Range

Commercial (A, B Versions) . . . . . . . . . . . . . –40

+ 0.3 V

DD

+ 0.3 V

DRIVE

o

C to +85oC

OL

1.6V

I

OH

o

Storage Temperature Range . . . . . . . . . . . . –65

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150

C to +150oC

o

C

TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW

␪

Thermal Impedance . . . . . . . . . . . . 143°C/W (TSSOP)

JA

Thermal Impedance . . . . . . . . . . . . . 45°C/W (TSSOP)

␪

JC

Lead Temperature, Soldering

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 kV

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch up.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7866 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–4–

REV. 0

AD7866

ORDERING GUIDE

Resolution Package

Model Temperature Range (Bits) Package Description Option

AD7866ARU –40°C to +85°C 12 Thin Shrink SO (TSSOP) RU-20
AD7866BRU –40°C to +85°C 12 Thin Shrink SO (TSSOP) RU-20
EVAL-AD7866CB
EVAL-CONTROL BRD22Controller Board

NOTES

1

This can be used as a stand-alone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes.

2

This evaluation board controller is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

1

Evaluation Board (TSSOP)

PIN CONFIGURATION

REF SELECT

D

CAP

AGND

V

V

V

V

AGND

D

CAP

V

REF

1

2

B

3

4

B2

5

B1

6

A2

7

A1

8

9

A

10

AD7866

TOP VIEW

(Not to Scale)

20

19

18

17

16

15

14

13

12

11

A0

CS

SCLK

V

DRIVE

D

OUT

D

OUT

DGND

DV

DD

AV

DD

RANGE

B

A

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 REF SELECT Internal/External Reference Selection Pin. Logic Input. If this pin is tied to GND, the on-chip

2.5 V reference is used as the reference source for both ADC A and ADC B. In addition, pins V
D

A, and D

CAP

logic high, an external reference can be supplied to the AD7866 through the V
case decoupling capacitors are required on D

B must be tied to decoupling capacitors. If the REF SELECT pin is tied to a

CAP

A and D

CAP

B. However, if the V

CAP

pin, in which

REF

pin is tied to

REF

REF

,

AGND while REF SELECT is tied to a logic low, an individual external reference can be applied

2, 9 D

CAP

B, D

to both ADC A and ADC B through pins D

A Decoupling capacitors are connected to these pins to decouple the reference buffer for each respective

CAP

A and D

CAP

B, respectively. See Reference section.

CAP

ADC. The on-chip reference can be taken from these pins and applied externally to the rest of a
system. Depending on the polarity of the REF SELECT pin and the configuration of the V

REF

pin,
these pins can also be used to input a separate external reference to each ADC. The range of the
external reference is dependent on the analog input range selected. See Reference section.

3, 8 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7866. All analog input

signals and any external reference signal should be referred to this AGND voltage. Both of these
pins should connect to the AGND plane of a system. The AGND and DGND voltages should
ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis.

4, 5 V

6, 7 V

10 V

B2, VB1

A2, VA1

REF

Analog Inputs of ADC B. Single-ended analog input channels. The input range on each channel is 0 V
to V

or a 2 × V

REF

range depending on the polarity of the RANGE pin upon the falling edge of CS.

REF

Analog Inputs of ADC A. Single-ended analog input channels. The input range on each channel is 0 V
to V

or a 2 × V

REF

range depending on the polarity of the RANGE pin upon the falling edge of CS.

REF

Reference Decoupling Pin and External Reference Selection Pin. This pin is connected to the inter­nal reference and requires a decoupling capacitor. The nominal reference voltage is 2.5 V and this
appears at the pin; however, if the internal reference is to be used externally in a system, it must be
taken from either the D

CAP

A or D

B pins. This pin is also used in conjunction with the REF SELECT

CAP

pin when applying an external reference to the AD7866. See REF SELECT pin description.

REV. 0

–5–

AD7866

PIN FUNCTION DESCRIPTIONS (continued)

Pin No. Mnemonic Function

11 RANGE Analog Input Range and Output Coding Selection Pin. Logic Input. The polarity on this pin will

determine what input range the analog input channels on the AD7866 will have, and it will also
select what type of output coding the ADC will use for the conversion result. On the falling edge of
CS, the polarity of this pin is checked to determine the analog input range of the next conversion. If
this pin is tied to a logic low, the analog input range is 0 V to V
part will be straight binary (for the next conversion). If this pin is tied to a logic high when CS goes
low, the analog input range is 2 × V

and the output coding for the part will be two’s complement.

REF

However, if after the falling edge of CS the logic level of the RANGE pin has changed upon the eighth
SCLK falling edge, the output coding will change to the other option without any change in the
analog input range. (See Analog Input and ADC Transfer Function sections.)

12 AV

DD

Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on
the AD7866. The AV

and DV

DD

voltages should ideally be at the same potential and must not

DD

be more than 0.3 V apart even on a transient basis. This supply should be decoupled to AGND.

13 DV

DD

Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the
AD7866. The DV

and AV

DD

voltages should ideally be at the same potential and must not be

DD

more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND.

14 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7866. The

DGND and AGND voltages should ideally be at the same potential and must not be more than

0.3 V apart even on a transient basis.

15, 16 D

OUT

A, D

B Serial Data Outputs. The data output is supplied to this pin as a serial data stream. The bits are

OUT

clocked out on the falling edge of the SCLK input. The data appears on both pins simultaneously
from the simultaneous conversions of both ADCs. The data stream consists of one leading zero
followed by three STATUS bits, followed by the 12 bits of conversion data. The data is provided
MSB first. If CS is held low for a further 16 SCLK cycles after the conversion data has been output
on either D

OUT

A or D

B, the data from the other ADC follows on the D

OUT

data from a simultaneous conversion on both ADCs to be gathered in serial format on either D

17 V

DRIVE

or D

Logic Power Supply Input. The voltage supplied at this pin determines what voltage the interface

B alone using only one serial port. See Serial Interface section.

OUT

will operate at. This pin should be decoupled to DGND.

18 SCLK Serial Clock. Logic Input. A serial clock input provides the SCLK for accessing the data from the

AD7866. This clock is also used as the clock source for the conversion process.

19 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions

on the AD7866 and also frames the serial data transfer.

20 A0 Multiplexer Select. Logic Input. This input is used to select the pair of channels to be converted

simultaneously, i.e. Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and
ADC B. The logic state of this pin is checked upon the falling edge of CS and the multiplexer is set
up for the next conversion. If it is low, the following conversion will be performed on Channel 1 of
each ADC; if it is high, the following conversion will be performed on Channel 2 of each ADC.

and the output coding from the

REF

pin. This allows

OUT

OUT

A

–6–

REV. 0