ANALOG DEVICES AD7866 Service Manual
Dual 1 MSPS, 12-Bit, 2-Channel
www.BDTIC.com/ADI
SAR ADC with Serial Interface
AD7866
FEATURES
Dual 12-Bit, 2-Channel ADC
Fast Throughput Rate: 1 MSPS
Specified for V
of 2.7 V to 5.25 V
DD
Low Power
11.4 mW Max at 1 MSPS with 3 V Supplies
24 mW Max at 1 MSPS with 5 V Supplies
Wide Input Bandwidth
70 dB SNR at 300 kHz Input Frequency
On-Board Reference 2.5 V
–40ⴗC to +125ⴗC Operation
Flexible Power/Throughput Rate Management
Simultaneous Conversion/Read
No Pipeline Delays
High Speed Serial Interface SPI
MICROWIRE
TM
/DSP Compatible
TM
/QSPITM/
Shutdown Mode: 1 A Max
20-Lead TSSOP Package
GENERAL DESCRIPTION
The AD7866 is a dual 12-bit high speed, low power, successive
approximation ADC. The part operates from a single 2.7 V to
5.25 V power supply and features throughput rates up to 1 MSPS.
The device contains two ADCs, each preceded by a low noise,
wide bandwidth track-and-hold amplifier that can handle
input frequencies in excess of 10 MHz.
The conversion process and data acquisition are controlled
using standard control inputs, allowing easy interfacing to
microprocessors or DSPs. The input signal is sampled on the
falling edge of CS; conversion is also initiated at this point.
The conversion time is determined by the SCLK frequency.
There are no pipelined delays associated with the part.
The AD7866 uses advanced design techniques to achieve
very low power dissipation at high throughput rates. With 3 V
supplies and 1 MSPS throughput rate, the part consumes a
maximum of 3.8 mA. With 5 V supplies and 1 MSPS, the
current consumption is a maximum of 4.8 mA. The part also
offers flexible power/throughput rate management when
operating in sleep mode.
The analog input range for the part can be selected to be a 0 V
range or a 2 ⫻ V
to V
REF
range with either straight binary or
REF
twos complement output coding. The AD7866 has an on-chip
2.5 V reference that can be overdriven if an external reference
is preferred. Each on-board ADC can also be supplied with a
separate individual external reference.
The AD7866 is available in a 20-lead thin shrink small outline
(TSSOP) package.
FUNCTIONAL BLOCK DIAGRAM
BUF
T/H
T/H
BUF
D
AAV
CAP
REF SELECT
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
D
B
CAP
AD7866
DGND
DDDVDD
OUTPUT
DRIVERS
OUTPUT
DRIVERS
D
OUT
A0
RANGE
SCLK
CS
V
DRIVE
D
OUT
A
B
V
A1
V
A2
V
B1
V
B2
V
REF
2.5V
REF
MUX
MUX
AGND AGND
PRODUCT HIGHLIGHTS
1. The AD7866 features two complete ADC functions, allowing
simultaneous sampling and conversion of two channels. Each
ADC has a 2-channel input multiplexer. The conversion result
of both channels is available simultaneously on separate data
lines, or may be taken on one data line if only one serial port
is available.
2. High Throughput with Low Power Consumption—The
AD7866 offers a 1 MSPS throughput rate with 11.4 mW
maximum power consumption when operating at 3 V.
3. Flexible Power/Throughput Rate Management—The conversion rate is determined by the serial clock, allowing the power
consumption to be reduced as the conversion time is reduced
through a SCLK frequency increase. Power efficiency can be
maximized at lower throughput rates if the part enters sleep
during conversions.
4. No Pipeline Delay—The part features two standard successive
approximation ADCs with accurate control of the sampling
instant via a CS input and once off conversion control.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
AD7866–SPECIFICATIONS
www.BDTIC.com/ADI
(TA = T
External on D
MIN
to T
, VDD = 2.7 V to 5.25 V, V
MAX
A and D
CAP
CAP
= 2.7 V to 5.25 V, Reference = 2.5 V
B, f
SCLK
DRIVE
= 20 MHz, unless otherwise noted.)
Parameter A Version1B Version1Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion (SINAD)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
2
2
2
68 68 dB min fIN = 300 kHz Sine Wave, fS = 1 MSPS
–75 –75 dB max f
2
–76 –76 dB max fIN = 300 kHz Sine Wave, fS = 1 MSPS
= 300 kHz Sine Wave, fS = 1 MSPS
IN
Second Order Terms –88 –88 dB typ
Third Order Terms –88 –88 dB typ
Channel-to-Channel Isolation –88 –88 dB typ
SAMPLE AND HOLD
Aperture Delay
Aperture Jitter
Aperture Delay Matching
3
3
3
10 10 ns max
50 50 ps typ
200 200 ps max
Full Power Bandwidth 12 12 MHz typ @ 3 dB
22MHz typ @ 0.1 dB
DC ACCURACY
Resolution 12 12 Bits
Integral Nonlinearity ± 1.5 ± 1 LSB max B Grade, 0 V to V
± 1.5 LSB max 0 V to 2 V
Range Only; ±0.5 LSB typ
REF
Range; ± 0.5 LSB typ
REF
Differential Nonlinearity –0.95/+1.25 –0.95/+1.25 LSB max Guaranteed No Missed Codes to 12 Bits
0 V to V
Input Range Straight Binary Output Coding
REF
Offset Error ± 8 ± 8 LSB max
Offset Error Match ± 1.2 ± 1.2 LSB typ
Gain Error ± 2.5 ± 2.5 LSB max
Gain Error Match ± 0.2 ± 0.2 LSB typ
2 V
Input Range –V
REF
REF
to +V
Biased about V
REF
REF
with
Positive Gain Error ± 2.5 ± 2.5 LSB max Twos Complement Output Coding
Zero Code Error ± 8 ± 8 LSB max
Zero Code Error Match ± 0.2 ± 0.2 LSB typ
Negative Gain Error ± 2.5 ± 2.5 LSB max
ANALOG INPUT
Input Voltage Ranges 0 to V
REF
0 to 2 V
DC Leakage Current ± 500 ± 500 nA max T
REF
0 to V
REF
0 to 2 V
V RANGE Pin Low upon CS Falling Edge
V RANGE Pin High upon CS Falling Edge
REF
= –40C to +85C
A
11µA max 85C < TA ≤ 125C
Input Capacitance 30 30 pF typ When in Track
10 10 pF typ When in Hold
REFERENCE INPUT/OUTPUT
Reference Input Voltage 2.5 2.5 V ± 1% for Specified Performance
Reference Input Voltage Range
DC Leakage Current ± 30 ±30 µA max V
Input Capacitance 20 20 pF typ
Reference Output Voltage
V
Output Impedance
REF
4
5
6
2/3 2/3 V min/V max REF SELECT Pin Tied High
Pin
± 160 ± 160 µA max D
REF
CAP
A, D
CAP
B Pins
2.45/2.55 2.45/2.55 V min/V max
25 25 Ω typ VDD = 5 V
45 45 Ω typ VDD = 3 V
Reference Temperature Coefficient 50 50 ppm/°C typ
REF OUT Error (T
MIN
to T
) ± 15 ±15 mV typ
MAX
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C
INL
IN
IN
INH
3
0.7 V
0.3 V
DRIVE
DRIVE
0.7 V
0.3 V
DRIVE
DRIVE
V min
V max
± 1 ± 1 µA max Typically 15 nA, V
10 10 pF max
= 0 V or V
IN
DRIVE
LOGIC OUTPUTS
V
Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ± 1 ± 1 µA max V
Floating-State Output Capacitance
OH
OL
3
– 0.2 V
DRIVE
0.4 0.4 V max I
10 10 pF max
– 0.2 V min I
DRIVE
= 200 µA
SOURCE
= 200 µA
SINK
= 2.7 V to 5.25 V
DD
Output Coding Straight (Natural) Binary Selectable with Either Input Range
Twos Complement
REV. A–2–
AD7866
www.BDTIC.com/ADI
Parameter A Version1B Version1Unit Test Conditions/Comments
CONVERSION RATE
Conversion Time 16 16 SCLK cycles 800 ns with SCLK = 20 MHz
Track/Hold Acquisition Time
Throughput Rate 1 1 MSPS max See Serial Interface Section
POWER REQUIREMENTS
V
DD
V
DRIVE
7
I
DD
Normal Mode (Static) 3.1 3.1 mA max VDD = 4.75 V to 5.25 V. Add 0.5 mA
Operational, f
= 1 MSPS 4.8 4.8 mA max VDD = 4.75 V to 5.25 V. Add 0.5 mA
S
Partial Power-Down Mode 1.6 1.6 mA max f
Partial Power-Down Mode 560 560 µA max (Static) Add 100 µA Typical if Using
Full Power-Down Mode 1 1 µA max SCLK On or Off. T
Power Dissipation
7
Normal Mode (Operational) 24 24 mW max VDD = 5 V
Partial Power-Down (Static) 2.8 2.8 mW max V
Full Power-Down (Static) 5 5 µW max V
NOTES
1
Temperature ranges as follows: A, B Versions: –40°C to +125°C.
2
See Terminology section.
3
Sample tested @ 25°C to ensure compliance.
4
External reference range that may be applied at V
5
Relates to pins V
6
See Reference section for D
7
See Power vs. Throughput Rate section.
Specifications subject to change without notice.
REF
, D
CAP
A, or D
CAP
3
B.
CAP
A, D
B output impedances.
CAP
300 300 ns max
2.7/5.25 2.7/5.25 V min/max
2.7/5.25 2.7/5.25 V min/max
Digital I/Ps = 0 V or V
Typical if Using Internal Reference.
2.8 2.8 mA max V
= 2.7 V to 3.6 V. Add 0.35 mA
DD
Typical if Using Internal Reference.
Typical if Using Internal Reference.
3.8 3.8 mA max V
= 2.7 V to 3.6 V. Add 0.5 mA
DD
Typical if Using Internal Reference.
= 100 kSPS, f
S
SCLK
Add 0.2 mA Typ if Using Internal
Reference.
Internal Reference.
22 µA max SCLK On or Off. 85C < T
A
11.4 11.4 mW max V
1.68 1.68 mW max V
= 3 V
DD
= 5 V. SCLK On or Off.
DD
= 3 V. SCLK On or Off.
DD
= 5 V. SCLK On or Off.
DD
33 µW max VDD = 3 V. SCLK On or Off.
, D
REF
CAP
A, or D
CAP
B.
DRIVE
= 20 MHz
= –40C to +85C
≤ 125C
A
REV. A
–3–
AD7866
www.BDTIC.com/ADI
1
TIMING SPECIFICATIONS
(VDD = 2.7 V to 5.25 V, V
Limit at
Parameter T
2
f
SCLK
MIN
, T
MAX
Unit Description
10 kHz min
20 MHz max
t
CONVERT
t
QUIET
t
2
3
t
3
3
t
4
t
5
t
6
t
7
4
t
8
4
t
9
16 t
SCLK
800 ns max f
ns max t
SCLK
SCLK
50 ns max Minimum Time between End of Serial Read and Next Falling Edge of CS
10 ns min CS to SCLK Setup Time
25 ns max Delay from CS until D
40 ns max Data Access Time after SCLK Falling Edge. V
V
0.4 t
0.4 t
SCLK
SCLK
ns min SCLK Low Pulsewidth
ns min SCLK High Pulsewidth
DRIVE
10 ns min SCLK to Data Valid Hold Time
25 ns max CS Rising Edge to D
10 ns min SCLK Falling Edge to D
50 ns max SCLK Falling Edge to D
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of V
2
Mark/Space ratio for the CLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
8, t9
lated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times t8 and t9 quoted in the timing characteristics are the true
bus relinquish times of the part and are independent of the bus loading.
Specifications subject to change without notice.
= 2.7 V to 5.25 V, V
DRIVE
= 1/f
SCLK
= 20 MHz
< 3 V, CL = 25 pF
OUT
OUT
A, D
OUT
OUT
A and D
= 2.5 V; TA = T
REF
B Three-State Disabled
OUT
B, High Impedance
OUT
A, D
A, D
B, High Impedance
OUT
B, High Impedance
OUT
) and timed from a voltage level of 1.6 V.
DRIVE
to T
MIN
, unless otherwise noted.)
MAX
3 V, CL = 50 pF;
DRIVE
OUTPUT
PIN
TO
50pF
C
L
200AI
200A
OL
1.6V
I
OH
Figure 1. Load Circuit for Digital Output Timing Specifications
REV. A–4–
AD7866
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
(TA = 25oC, unless otherwise noted.)
AV
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DD
DV
to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DD
to DGND . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
V
DRIVE
to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
V
DRIVE
AV
to DVDD . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
DD
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . . –0.3 V to AV
Digital Input Voltage to DGND . . . . . . . . . . . . –0.3 V to +7 V
to AGND . . . . . . . . . . . . . . . . . . –0.3 V to AV
V
REF
Digital Output Voltage to DGND . . . –0.3 V to V
Input Current to Any Pin Except Supplies
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . . . –40C to +125C
1
2
DRIVE
. . . . . . . . . 10 mA
+ 0.3 V
DD
+ 0.3 V
DD
+ 0.3 V
Storage Temperature Range . . . . . . . . . . . . –65C to +150C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW
Thermal Impedance (TSSOP) . . . . . . . . . . . . . 143C/W
JA
Thermal Impedance (TSSOP) . . . . . . . . . . . . . . 45C/W
JC
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 kV
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch up.
ORDERING GUIDE
Resolution Package
Model Temperature Range (Bits) Package Description Option
AD7866ARU –40°C to +125°C12Thin Shrink SOC (TSSOP) RU-20
AD7866BRU –40°C to +125°C12Thin Shrink SOC (TSSOP) RU-20
EVAL-AD7866CB
EVAL-CONTROL BRD2
NOTES
1
This can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes.
2
This evaluation board controller is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB design ators.
To order a complete evaluation kit, the particular ADC evaluation board, e.g., EVAL-AD7866CB, the EVAL-CONTROL BRD2, and a 12 V transformer must be
ordered. See relevant Evaluation Board Technical note for more information.
1
2
Evaluation Board
Controller Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7866 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. A
–5–
AD7866
www.BDTIC.com/ADI
PIN CONFIGURATION
REF SELECT
D
CAP
AGND
V
V
V
V
AGND
D
CAP
V
REF
1
2
B
3
4
B2
5
B1
6
A2
7
A1
8
9
A
10
AD7866
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
A0
CS
SCLK
V
DRIVE
D
OUT
D
OUT
DGND
DV
DD
AV
DD
RANGE
B
A
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
1 REF SELECT Internal/External Reference Selection. Logic input. If this pin is tied to GND, the on-chip 2.5 V reference
is used as the reference source for both ADC A and ADC B. In addition, pins V
REF
, D
A, and D
CAP
CAP
B
must be tied to decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7866 through the V
required on D
A and D
CAP
B. However, if the V
CAP
pin, in which case decoupling capacitors are
REF
pin is tied to AGND while REF SELECT is tied to
REF
a logic low, an individual external reference can be applied to both ADC A and ADC B through pins
2, 9 D
CAP
B, D
A and D
D
CAP
A Decoupling capacitors are connected to these pins to decouple the reference buffer for each respective
CAP
B, respectively. See the Reference Configuration Options section.
CAP
ADC. The on-chip reference can be taken from these pins and applied externally to the rest of a system.
Depending on the polarity of the REF SELECT pin and the configuration of the V
pin, these
REF
pins can also be used to input a separate external reference to each ADC. The range of the external
reference is dependent on the analog input range selected. See the Reference Configuration
Options section.
3, 8 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7866. All analog input signals
and any external reference signal should be referred to this AGND voltage. Both of these pins should
connect to the AGND plane of a system. The AGND and DGND voltages ideally should be at the
same potential and must not be more than 0.3 V apart, even on a transient basis.
4, 5 V
6, 7 V
10 V
B2, VB1
A2, VA1
REF
Analog Inputs of ADC B. Single-ended analog input channels. The input range on each channel is 0 V
to V
or a 2 V
REF
range depending on the polarity of the RANGE pin upon the falling edge of CS .
REF
Analog Inputs of ADC A. Single-ended analog input channels. The input range on each channel is 0 V
to V
or a 2 V
REF
range depending on the polarity of the RANGE pin upon the falling edge of CS .
REF
Reference Decoupling and External Reference Selection. This pin is connected to the internal reference
and requires a decoupling capacitor. The nominal reference voltage is 2.5 V, which appears at the pin;
however, if the internal reference is to be used externally in a system, it must be taken from either the
A or D
D
CAP
applying an external ref
B pins. This pin is also used in conjunction with the REF SELECT pin when
CAP
erence to the AD7866. See the REF SELECT pin description.
REV. A–6–
AD7866
www.BDTIC.com/ADI
PIN FUNCTION DESCRIPTIONS (continued)
Pin No. Mnemonic Function
11 RANGE Analog Input Range and Output Coding Selection. Logic input. The polarity on this pin will
determine what input range the analog input channels on the AD7866 will have, and will also select
the type of output coding the ADC will use for the conversion result. On the falling edge of CS, the
polarity of this pin is checked to determine the analog input range of the next conversion. If this pin
is tied to a logic low, the analog input range is 0 V to V
be straight binary (for the next conversion). If this pin is tied to a logic high when CS goes low, the
analog input range is 2 V
and the output coding for the part will be twos complement. How-
REF
ever, if after the falling edge of CS the logic level of the RANGE pin has changed upon the eighth
SCLK falling edge, the output coding will change to the other option without any change in the
analog input range. (See the Analog Input and ADC Transfer Function sections.)
12 AV
DD
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the
AD7866. The AV
and DV
DD
voltages ideally should be at the same potential and must not be
DD
more than 0.3 V apart even on a transient basis. This supply should be decoupled to AGND.
13 DV
DD
Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the
AD7866. The DV
and AV
DD
voltages should ideally be at the same potential and must not be
DD
more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND.
14 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7866. The
DGND and AGND voltages ideally should be at the same potential and must not be more than 0.3 V
apart even on a transient basis.
15, 16 D
OUT
A, D
B Serial Data Outputs. The data output is supplied to this pin as a serial data stream. The bits are
OUT
clocked out on the falling edge of the SCLK input. The data appears on both pins simultaneously
from the simultaneous conversions of both ADCs. The data stream consists of one leading zero
followed by three STATUS bits, followed by the 12 bits of conversion data. The data is provided
MSB first. If CS is held low for another 16 SCLK cycles after the conversion data has been output
on either D
OUT
A or D
B, the data from the other ADC follows on the D
OUT
from a simultaneous conversion on both ADCs to be gathered in serial format on either D
B alone using only one serial port. See the Serial Interface section.
D
OUT
17 V
DRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
will operate. This pin should be decoupled to DGND.
18 SCLK Serial Clock. Logic Input. A serial clock input provides the SCLK for accessing the data from the
AD7866. This clock is also used as the clock source for the conversion process.
19 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7866 and frames the serial data transfer.
20 A0 Multiplexer Select. Logic input. This input is used to select the pair of channels to be converted
simultaneously, i.e., Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADC B.
The logic state of this pin is checked upon the falling edge of CS, and the multiplexer is set up for
the next conversion. If it is low, the following conversion will be performed on Channel 1 of each ADC;
if it is high, the following conversion will be performed on Channel 2 of each ADC.
and the output coding from the part will
REF
pin. This allows data
OUT
OUT
A or
REV. A
–7–
AD7866
www.BDTIC.com/ADI
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB above
the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This applies to Straight Binary output coding. It is the deviation
of the first code transition (00 . . . 000) to (00 . . . 001) from the
ideal, i.e., AGND + 1 LSB.
Offset Error Match
This is the difference in Offset Error between the two channels.
Gain Error
This applies to Straight Binary output coding. It is the deviation
of the last code transition (111 . . . 110) to (111 . . . 111) from
the ideal (i.e., V
– 1 LSB) after the offset error has been
REF
adjusted out.
Gain Error Match
This is the difference in Gain Error between the two channels.
Zero Code Error
This applies when using the twos complement output coding
option, in particular with the 2 V
biased about the V
+V
REF
point. It is the deviation of the
REF
midscale transition (all 1s to all 0s) from the ideal V
i.e., V
Zero Code Error Match
– 1 LSB.
REF
input range as –V
REF
REF
voltage,
IN
to
This refers to the difference in Zero Code Error between the
two channels.
Positive Gain Error
This applies when using the twos complement output coding
option, in particular with the 2 V
biased about the V
+V
REF
point. It is the deviation of the last
REF
input range as –V
REF
REF
to
code transition (011 . . . 110) to (011 . . . 111) from the ideal
(i.e., +V
– 1 LSB) after the Zero Code Error has been
REF
adjusted out.
Negative Gain Error
This applies when using the twos complement output coding
option, in particular with the 2 V
biased about the V
+V
REF
point. It is the deviation of the first
REF
input range as –V
REF
REF
to
code transition (100 . . . 000) to (100 . . . 001) from the ideal
(i.e., –V
+ 1 LSB) after the Zero Code Error has been
REF
adjusted out.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode after the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.
Signal-to-(Noise + Distortion) Ratio (SNDR)
This is the measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f
/2), excluding dc. The
S
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. For the AD7866, it is defined as:
2
THD db
()
VVVVV
++++
=
20
223242526
log
V
1
where V1 is the rms amplitude of the fundamental and V2, V3,
, V5, and V6 are the rms amplitudes of the second through the
V
4
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic, or spurious noise, is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
/2 and excluding dc) to the rms value of the
S
fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum. But for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities will create distortion products
at sum and difference frequencies of mfa ± nfb where m, n = 0,
1, 2, 3, and so on. Intermodulation distortion terms are those for
which neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb).
The AD7866 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum
of the individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in dB.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk
between channels. It is measured by applying a full-scale
(2 V
), 455 kHz sine wave signal to all unselected input
REF
channels and determining how much that signal is attenuated in the
selected channel with a 10 kHz signal (0 V to V
). The figure
REF
given is the worst-case across all four channels for the AD7866.
PSR (Power Supply Rejection)
See the Performance Curves section.
REV. A–8–
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