Analog Devices AD7864 b Datasheet

4-Channel, Simultaneous

Sampling, High Speed, 12-Bit ADC

AD7864

FEATURES
High Speed (1.65 s) 12-Bit ADC
4 Simultaneously Sampled Inputs
4 Track/Hold Amplifiers

0.35 s Track/Hold Acquisition Time

1.65 s Conversion Time per Channel
HW/SW Select of Channel Sequence for Conversion
Single-Supply Operation
Selection of Input Ranges:

10 V, 5 V for AD7864-1
2.5 V for AD7864-3

0 V to 2.5 V, 0 V to 5 V for AD7864-2

High Speed Parallel Interface that Allows

Interfacing to 3 V Processors
Low Power, 90 mW Typ
Power Saving Mode, 20 W Typ
Overvoltage Protection on Analog Inputs

APPLICATIONS
AC Motor Control
Uninterrupted Power Supplies
Data Acquisition Systems
Communications

GENERAL DESCRIPTION

The AD7864 is a high speed, low power, 4-channel simulta­neous sampling 12-bit A/D converter that operates from a single
5V supply. The part contains a 1.65 ms successive approxima-
tion ADC, four track/hold amplifiers, a 2.5 V reference, an
on-chip clock oscillator, signal conditioning circuitry, and a high
speed parallel interface. The input signals on four channels
are sampled simultaneously, thus preserving the relative phase
information of the signals on the four analog inputs. The part
accepts analog input ranges of ± 10 V, ± 5 V (AD7864-1), 0 V to
+2.5 V, 0 V to +5 V (AD7864-2), and ± 2.5 V (AD7864-3).

The part allows any subset of the four channels to be converted
in order to maximize the throughput rate on the selected sequence.
The channels to be converted can be selected via hardware
(channel select input pins) or software (programming the channel
select register).

A single conversion start signal (CONVST) simultaneously
places all the track/holds into hold and initiates a conversion
sequence for the selected channels. The EOC signal indicates the
end of each individual conversion in the selected conversion
sequence. The BUSY signal indicates the end of the conver­sion sequence.

REV. B

FUNCTIONAL BLOCK DIAGRAM

V

DV

2.5V

REFERENCE

AD7864

OUTPUT

DATA

REGISTERS

DB0 TO DB3

INT/EXT

CLK

DRIVE

DD

INT

CLOCK

AGND AGND

DGND

AGND

RD

DB11

DB0

CS

WR

STBY

V

IN1A

V

IN1B

V

IN2A

V

IN2B

V

IN3A

V

IN3B

V

IN4A

V

IN4B

FRSTDATA

BUSY

EOC

SIGNAL

SCALING

SIGNAL

SCALING

SIGNAL

SCALING

SIGNAL

SCALING

CONVST

AV

DD

TRACK/HOLD



4

CONVERSION

CONTROL LOGIC

SL1 SL2 SL3 SL4

MUX

V

H/S

SEL

REF

6k

V

REF GND

12-BIT

ADC

SOFTWARE

LATCH

INT/EXT CLOCK

SELECT

CLKIN

Data is read from the part by means of a 12-bit parallel data
bus using the standard CS and RD signals. Maximum through­put for a single channel is 500 kSPS. For all four channels, the
maximum throughput is 130 kSPS for the read during conver­sion sequence operation. The throughput rate for the read after
conversion sequence operation depends on the read cycle time
of the processor. See the Timing and Control section.

The AD7864 is available in a small (0.3 sq. inch area) 44-lead
MQFP.

PRODUCT HIGHLIGHTS

1. The AD7864 features four track/hold amplifiers and a fast

(1.65 ms) ADC allowing simultaneous sampling and then
conversion of any subset of the four channels.

2. The AD7864 operates from a single 5 V supply and consumes
only 90 mW typ, making it ideal for low power and portable
applications. Also see the Standby Mode Operation section.

3. The part offers a high speed parallel interface for easy con­nection to microprocessors, microcontrollers, and digital
signal processors.

4. The part is offered in three versions with different analog
input ranges. The AD7864-1 offers the standard industrial
input ranges of ± 10 V and ± 5 V; the AD7864-3 offers the
common signal processing input range of ± 2.5 V; the
AD7864-2 can be used in unipolar 0 V to 2.5 V, 0 V to 5 V
applications.

5. The part features very tight aperture delay matching between
the four input sample-and-hold amplifiers.

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

(VDD = 5 V  5%, AGND = DGND = 0 V, V

AD7864–SPECIFICATIONS

cations T

Parameter A Version

to T

MIN

1

, unless otherwise noted.)

MAX

B Version Unit Test Conditions/Comments

= Internal, Clock = Internal; all specifi-

REF

SAMPLE AND HOLD

–3 dB Full Power Bandwidth 3 3 MHz typ
Aperture Delay 20 20 ns max
Aperture Jitter 50 50 ps typ
Aperture Delay Matching 4 4 ns max

DYNAMIC PERFORMANCE

2

Signal-to-(Noise + Distortion) Ratio

3

fIN = 100.0 kHz, fS = 500 kSPS

@ 25∞C7072dB min
T

to T

MIN

Total Harmonic Distortion
Peak Harmonic or Spurious Noise
Intermodulation Distortion

MAX

3

3

3

70 70 dB min

–80 –80 dB max
–80 –80 dB max

fa = 49 kHz, fb = 50 kHz
Second-Order Terms –80 –80 dB typ
Third-Order Terms –80 –80 dB typ

Channel-to-Channel Isolation

3

–80 –80 dB max fIN = 50 kHz Sine Wave

DC ACCURACY Any Channel

Resolution 12 12 Bits
Relative Accuracy
Differential Nonlinearity
AD7864-1

Positive Gain Error
Positive Gain Error Match
Negative Gain Error
Negative Gain Error Match

3

3

3

3

3

3

± 1 ± 1/2 LSB max
± 0.9 ± 0.9 LSB max No Missing Codes

± 3 ± 3LSB max
3 ± 3LSB max
± 3 ± 3LSB max

3 ± 3LSB max
Bipolar Zero Error ± 4 ± 3LSB max
Bipolar Zero Error Match 2 ± 2LSB max

AD7864-3

Positive Gain Error
Positive Gain Error Match
Negative Gain Error
Negative Gain Error Match

3

3

3

3

± 3LSB max

2LSB max

± 3LSB max

2LSB max
Bipolar Zero Error ± 3LSB max
Bipolar Zero Error Match 2 LSB max

AD7864-2

Positive Gain Error
Positive Gain Error Match

3

3

± 3LSB max

3LSB max
Unipolar Offset Error ± 3LSB max
Unipolar Offset Error Match 2 LSB max

ANALOG INPUTS

AD7864-1

Input Voltage Range ± 5, ± 10 ± 5, ± 10 V
Input Resistance 9, 18 9, 18 kW min

AD7864-3

Input Voltage Range ± 2.5 ± 2.5 V
Input Resistance 4.5 4.5 kW min

AD7864-2

Input Voltage Range 0 to 2.5, 0 to 5 0 to 2.5, 0 to 5 V
Input Current (0 V to 2.5 V Option) ± 100 ± 100 nA max
Input Resistance (0 V to 5 V Option) 9 9 kW min

REFERENCE INPUT/OUTPUT

IN Input Voltage Range 2.375/2.625 2.375/2.625 V

V

REF

IN Input Capacitance

V

REF

V

OUT Output Voltage 2.5 2.5 V nom

REF

OUT Error @ 25∞C ± 10 ± 10 mV max

V

REF

OUT Error T

V

REF

V

OUT Temperature Coefficient 25 25 ppm/∞C typ

REF

V

OUT Output Impedance 6 6 kW typ See the Reference Section

REF

MIN

to T

4

MAX

10 10 pF max

± 20 ± 20 mV max

MIN/VMAX

2.5 V ± 5%

–2–

REV. B

AD7864

Parameter A Version

1

B Version Unit Test Conditions/Comments

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

4

2.4 2.4 V min VDD = 5 V ± 5%

0.8 0.8 V max VDD = 5 V ± 5%
± 10 ± 10 mA max
10 10 pF max

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OL

OH

4.0 4.0 V min I

0.4 0.4 V max I

SOURCE

= 1.6 mA

SINK

= 400 mA

DB11 to DB0

High Impedance

Leakage Current ± 10 ± 10 mA max
Capacitance

4

10 10 pF max

Output Coding

AD7864-1, AD7864-3 Twos Complement
AD7864-2 Straight (Natural) Binary

CONVERSION RATE

Conversion Time 1.65 1.65 ms max For One Channel
Track/Hold Acquisition Time

2, 3

0.35 0.35 ms max

Throughput Time 130 130 kSPS max For All Four Channels

POWER REQUIREMENTS

V

DD

I

DD

55 V nom ± 5% for Specified Performance

(5 mA typ) Logic Inputs = 0 V or V

Normal Mode 24 24 mA max
Standby Mode 20 20 mA max Typically 4 mA

Power Dissipation

Normal Mode 120 120 mW max Typically 90 mW
Standby Mode 100 100 mW max Typically 20 mW

NOTES

1

Temperature ranges are as follows: A, B Versions: –40∞ C to +85∞C. The A Version is fully specified up to 105∞C with a maximum sample rate of 450 kSPS and I
maximum (normal mode) of 26 mA.

2

Performance measured through full channel (SHA and ADC).

3

See Terminology section.

4

Sample tested at initial release to ensure compliance.

Specifications subject to change without notice.

DD

DD

REV. B

–3–

AD7864

(V

= 5 V  5%, AGND = DGND = 0 V, V

DRIVE

1, 2

T

to T

TIMING CHARACTERISTICS

MIN

, unless otherwise noted.)

MAX

Parameter A, B Versions Unit Test Conditions/Comments

t

CONV

1.65 ms max Conversion Time, Internal Clock
13 Clock Cycles Conversion Time, External Clock

2.6 ms max CLKIN = 5 MHz

t

ACQ

t

BUSY

t

WAKE-UP

t

WAKE-UP

t

1

t

2

—External V
—Internal V

REF

REF

3

0.34 ms max Acquisition Time
No. of Channels Selected Number of Channels Multiplied by
⫻ (t

+ t9) – t9ms max (t

CONV

CONV

2 ms max STBY Rising Edge to CONVST Rising Edge
6ms maxSTBY Rising Edge to CONVST Rising Edge

35 ns min CONVST Pulse Width
70 ns min CONVST Rising Edge to BUSY Rising Edge

Read Operation

t

3

t

4

t

5

4

t

6

5

t

7

0 ns min CS to RD Setup Time
0 ns min CS to RD Hold Time
35 ns min Read Pulse Width
35 ns max Data Access Time after Falling Edge of RD, V
40 ns max Data Access Time after Falling Edge of RD, V
5 ns min Bus Relinquish Time after Rising Edge of RD
30 ns max

t

8

t

9

10 ns min Time between Consecutive Reads
75 ns min EOC Pulse Width
180 ns max

t

10

t

11

t

12

70 ns max RD Rising Edge to FRSTDATA Edge (Rising or Falling)
15 ns max EOC Falling Edge to FRSTDATA Falling Delay
0 ns min EOC to RD Delay

Write Operation

t

13

t

14

t

15

t

16

t

17

NOTES

1

Sample tested at initial release to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

See Figures 7, 8, and 9.

3

Refer to the Standby Mode Operation section. The maximum specification of 6 ms is valid when using a 0.1 mF decoupling capacitor on the V

4

Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

5

These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part, and as such are independent of external bus loading capacitances.

Specifications subject to change without notice.

20 ns min WR Pulse Width
0 ns min CS to WR Setup Time
0 ns min WR to CS Hold Time
5 ns min Input Data Setup Time of Rising Edge of WR
5 ns min Input Data Hold Time

= Internal, Clock = Internal; all specifications

REF

+ EOC Pulse Width)—EOC Pulse Width

DRIVE

DRIVE

pin.

REF

= 5 V
= 3 V

1.6mA

TO

OUTPUT

50pF

400A

1.6V

Figure 1. Load Circuit for Access Time and Bus Relinquish Time

–4–

REV. B

AD7864

12 13 14 15 16 17 18 19 2 0 21 22

3

4

5

6

7

1

2

10

11

8

9

40 39 3841

42

4344 36 35 3437

29

30

31

32

27

28

25

26

23

24

33

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

DB7

DB8

DB9

DB10

DB11

CLKIN

INT/EXT CLK

BUSY

FRSTDATA

CONVST

CS

RD

WR

SL1

SL2

SL3

SL4

H/S SEL

AGND

AV

DD

V

REF

V

REF

GND

V

IN2A

V

IN1B

V

IN1A

STBY

AD7864

EOC

DB0

DB1

DB3

DB4

DB5

DGND

AGND

V

DRIVE

V

IN4B

DV

DD

V

IN2B

DB2

AGND

V

IN4A

DB6

V

IN3B

V

IN3A

ABSOLUTE MAXIMUM RATINGS*

(TA = 25∞C, unless otherwise noted)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV

DD

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

TO DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

AV

DD

Analog Input Voltage to AGND

AD7864-1 (± 10 V Input Range) . . . . . . . . . . . . . . . . ± 20 V

AD7864-1 (± 5 V Input Range) . . . . . . . . . . . –7 V to +20 V

AD7864-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V to +20 V

AD7864-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to +20 V

Reference Input Voltage to AGND . . . –0.3 V to V

+ 0.3 V

DD

Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V

Digital Output Voltage to DGND . . . . –0.3 V to V

to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

V

DRIVE

V

to DGND . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V

DRIVE

+ 0.3 V

DD

Operating Temperature Range

Commercial (A, B Version) . . . . . . . . . . . . –40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C

MQFP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95∞C/W

q

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215∞C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

PIN CONFIGURATION

ORDERING GUIDE

Input Relative Temperature Package Package

Model Ranges Accuracy Range

1

Description Option

AD7864AS-1 ±5 V, ± 10 V ±1 LSB –40∞C to +85∞CMetric Quad Flatpack S-44-2
AD7864AS-1 Reel ± 5 V, ± 10 V ± 1 LSB –40∞C to +85∞CMetric Quad Flatpack S-44-2
AD7864BS-1 ± 5 V, ± 10 V ± 0.5 LSB –40∞C to +85∞CMetric Quad Flatpack S-44-2
AD7864BS-1 Reel ± 5 V, ± 10 V ± 0.5 LSB –40∞C to +85∞CMetric Quad Flatpack S-44-2
AD7864AS-2 0 V to 2.5 V, 0 V to 5 V ± 1 LSB –40∞C to +85∞CMetric Quad Flatpack S-44-2
AD7864AS-2 Reel 0 V to 2.5 V, 0 V to 5 V ± 1 LSB –40∞C to +85∞CMetric Quad Flatpack S-44-2
AD7864AS-3 ±2.5 V ± 1 LSB –40∞C to +85∞CMetric Quad Flatpack S-44-2
AD7864AS-3 Reel ± 2.5 V ± 1 LSB –40∞C to +85∞CMetric Quad Flatpack S-44-2
EVAL-AD7864-1CB
EVAL-AD7864-2CB
EVAL-AD7864-3CB
EVAL-CONTROL BRD2

NOTES

1

The A Version is fully specified up to 105∞C with a maximum sample rate of 450 kSPS and IDD maximum (normal mode) of 26 mA.

2

This can be used as a stand alone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes.

3

This board is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a com­plete evaluation kit, the particular ADC evaluation board needs to be ordered, for example, EVAL-AD7864-1CB, the EVAL-CONTROL BRD2, and a 12 V ac
transformer. See the Evaluation Board application note for more information.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7864 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. B

2

2

2

3

Evaluation Board
Evaluation Board
Evaluation Board
Controller Board

–5–

AD7864

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 BUSY Busy Output. The busy output is triggered high by the rising edge of CONVST and remains high until

conversion is completed on all selected channels.

2 FRSTDATA First Data Output. FRSTDATA is a logic output which, when high, indicates that the output data

register pointer is addressing Register 1—See the Accessing the Output Data Registers section.

3 CONVST Convert Start Input. Logic input. A low-to-high transition on this input puts all track/holds into their

hold mode and starts conversion on the selected channels. In addition, the state of the channel sequence

selection is also latched on the rising edge of CONVST.
4 CS Chip Select Input. Active low logic input. The device is selected when this input is active.
5 RD Read Input. Active low logic input that is used in conjunction with CS low to enable the data outputs.

Ensure the WR pin is at logic high while performing a read operation.
6 WR Write Input. A rising edge on the WR input, with CS low and RD high, latches the logic state on DB0

to DB3 into the channel select register.
7 to 10 SL1 to SL4 Hardware Channel Select. Conversion sequence selection can also be made via the SL1 to SL4 pins if

H/S SEL is Logic 0. The selection is latched on the rising edge of CONVST. See the Selecting a Con-

version Sequence section.
11 H/S SEL Hardware/Software Select Input. When this pin is at Logic 0, the AD7864 conversion sequence selec-

tion is controlled via the SL1 to SL4 input pins. When this pin is at Logic 1, the sequence is controlled

via the channel select register. See the Selecting a Conversion Sequence section.
12 AGND Analog Ground. General analog ground. This AGND pin should be connected to the system’s

plane.

AGND
13 to 16 V
17 AGND Analog Ground. Analog ground reference for the attenuator circuitry. This AGND pin should be con-

18 to 21 V
22 STBY Standby Mode Input. TTL compatible input that is used to put the device into the power save or

23 V

24 V

25 AV
26 AGND Analog Ground. Analog ground reference for the DAC circuitry.
27 INT/EXT CLK Internal/External Clock Select Input. When this pin is at Logic 0, the AD7864 uses its internally gener-

28 CLKIN Conversion Clock Input. This is an externally applied clock that allows the user to control the conversion

29 to 34 DB11 to DB6 Data Bit 11 is the MSB, followed by Data Bit 10 to Data Bit 6. Three-state TTL outputs. Output

35 DV

36 V

37 DGND Digital Ground. Ground reference for digital circuitry. This DGND pin should be connected to the

38, 39 DB5, DB4 Data Bit 5 to Data Bit 4. Three-state TTL outputs.
40 to 43 DB3 to DB0 Data Bit 3 to Data Bit 0. Bidirectional data pins. When a read operation takes place, these pins are three-

44 EOC End-of-Conversion. Active low logic output indicating conversion status. The end of each conversion in

IN4x

IN2x

, V

, V

IN3x

IN1x

Analog Inputs. See the Analog Input section.

nected to the system’s AGND

plane.

Analog Inputs. See the Analog Input section.

standby mode. The STBY input is high for normal operation and low for standby operation.

GND Reference Ground. Ground reference for the part’s on-chip reference buffer. The V

REF

REF

should be connected to the system’s AGND

Reference Input/Output. This pin provides access to the internal reference (2.5 V ± 5%) and also

plane.

allows the internal reference to be overdriven by an external reference source (2.5 V). A 0.1 mF decoupling

capacitor should be connected between this pin and AGND.

DD

Analog Positive Supply Voltage, 5.0 V ± 5%.

ated master clock. When this pin is at Logic 1, the master clock is generated externally to the device.

rate of the AD7864. Each conversion needs 14 clock cycles in order for the conversion to be completed

and an EOC pulse to be generated. The clock should have a duty cycle that is no worse than 60/40. See

the Using an External Clock section.

coding is twos complement for the AD7864-1 and AD7864-3. Output coding is straight (natural)

binary for the AD7864-2.

DD

DRIVE

Positive Supply Voltage for Digital Section, 5.0 V ± 5%. A 0.1 mF decoupling capacitor should be

connected between this pin and AGND. Both DV

and AVDD should be externally tied together.

DD

This pin provides the positive supply voltage for the output drivers (DB0 to DB11), BUSY, EOC, and

. V

FRSTDATA. It is normally tied to DV

DD

should be decoupled with a 0.1 mF capacitor. It allows

DRIVE

improved performance when reading during the conversion sequence. To facilitate interfacing to 3 V proces-

sors and DSPs, the output data drivers can also be powered by a 3 V ± 10% supply.

system’s AGND

plane at the AGND pin.

state TTL outputs. The channel select register is programmed with the data on the DB0 to DB3 pins with

standard CS and WR signals. DB0 represents Channel 1, and DB3 represents Channel 4.

a conversion sequence is indicated by a low-going pulse on this line.

GND pin

REF

–6–

REV. B