Analog Devices AD7863BR-3, AD7863BR-10, AD7863ARS-3, AD7863ARS-2, AD7863ARS-10 Datasheet

REV. A

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a

AD7863

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

Simultaneous Sampling

Dual 175 kSPS 14-Bit ADC

FUNCTIONAL BLOCK DIAGRAM

DGND

DB0

BUSY

CS

CONVST

AD7863

AGND

V

REF

2k

AGND

TRACK/

HOLD

V

DD

DB13

A0

14-BIT

ADC

TRACK/

HOLD

MUX

SIGNAL

SCALING

+2.5V

REFERENCE

OUTPUT

LATCH

RD

CONVERSION

CONTROL LOGIC

SIGNAL

SCALING

SIGNAL

SCALING

SIGNAL

SCALING

MUX

14-BIT

ADC

CLOCK

V

A1

V

B1

V

A2

V

B2

FEATURES
Two Fast 14-Bit ADCs
Four Input Channels
Simultaneous Sampling and Conversion

5.2 s Conversion Time
Single Supply Operation
Selection of Input Ranges

10 V for AD7863-10
2.5 V for AD7863-3

0 V to 2.5 V for AD7863-2
High Speed Parallel Interface
Low Power, 70 mW Typ
Power Saving Mode, 105 W Max
Overvoltage Protection on Analog Inputs
14-Bit Lead Compatible Upgrade to AD7862

APPLICATIONS
AC Motor Control
Uninterrupted Power Supplies
Data Acquisition Systems
Communications

GENERAL DESCRIPTION

The AD7863 is a high speed, low power, dual 14-bit A/D con­verter that operates from a single +5 V supply. The part contains
two 5.2 µs successive approximation ADCs, two track/hold amplifi-
ers, an internal +2.5 V reference and a high speed parallel inter­face. Four analog inputs are grouped into two channels (A and
B) selected by the A0 input. Each channel has two inputs (V

A1

and VA2 or VB1 and VB2), which can be sampled and converted
simultaneously thus preserving the relative phase information of
the signals on both analog inputs. The part accepts an analog
input range of ±10 V (AD7863-10), ±2.5 V (AD7863-3) and
0 V–2.5 V (AD7863-2). Overvoltage protection on the analog
inputs for the part allows the input voltage to go to ±17 V, ±7 V
or +7 V respectively, without causing damage.

A single conversion start signal (CONVST) simultaneously
places both track/holds into hold and initiates conversion on
both channels. The BUSY signal indicates the end of conversion
and at this time the conversion results for both channels are
available to be read. The first read after a conversion accesses
the result from V

A1

or VB1, while the second read accesses the

result from V

A2

or VB2, depending on whether the multiplexer

select A0 is low or high respectively. Data is read from the part
via a 14-bit parallel data bus with standard CS and RD signals.

In addition to the traditional dc accuracy specifications such as
linearity, gain and offset errors, the part is also specified for
dynamic performance parameters including harmonic distortion
and signal-to-noise ratio.

The AD7863 is fabricated in Analog Devices’ Linear Compat­ible CMOS (LC

2

MOS) process, a mixed technology process
that combines precision bipolar circuits with low power CMOS
logic. It is available in 28-lead SOIC and SSOP.

PRODUCT HIGHLIGHTS

1. The AD7863 features two complete ADC functions allowing

simultaneous sampling and conversion of two channels.
Each ADC has a two-channel input mux. The conversion
result for both channels is available 5.2 µs after initiating
conversion.

2. The AD7863 operates from a single +5 V supply and

consumes 70 mW typ. The automatic power-down mode,
where the part goes into power down once conversion is
complete and “wakes up” before the next conversion cycle,
makes the AD7863 ideal for battery-powered or portable
applications.

3. The part offers a high speed parallel interface for easy

connection to microprocessors, microcontrollers and digital
signal processors.

4. The part is offered in three versions with different analog

input ranges. The AD7863-10 offers the standard industrial
input range of ±10 V; the AD7863-3 offers the common
signal processing input range of ±2.5 V, while the AD7863-2
can be used in unipolar 0 V–2.5 V applications.

5. The part features very tight aperture delay matching between

the two input sample and hold amplifiers.

–2–

REV. A

AD7863–SPECIFICATIONS

(VDD = +5 V  5%, AGND = DGND = 0 V, REF = Internal. All specifications T

MIN

to T

MAX

unless otherwise noted.)

AB

Parameter Version

1

Version

1

Units Test Conditions/Comments

SAMPLE AND HOLD

–3 dB Small Signal Bandwidth 7 7 MHz typ
Aperture Delay

2

35 35 ns max

Aperture Jitter

2

50 50 ps typ

Aperture Delay Matching

2

350 350 ps max

DYNAMIC PERFORMANCE

3

fIN = 80.0 kHz, fS = 175 kSPS

Signal to (Noise + Distortion) Ratio

4

@ +25°C 7878dB min
T

MIN

to T

MAX

77 77 dB min

Total Harmonic Distortion

4

–82 –82 dB max Typically –87 dB

Peak Harmonic or Spurious Noise

4

–82 –82 dB max Typically –90 dB

Intermodulation Distortion

4

fa = 49 kHz, fb = 50 kHz
2nd Order Terms –93 –93 dB typ
3rd Order Terms –89 –89 dB typ

Channel-to-Channel Isolation

4

–86 –86 dB typ fIN = 50 kHz Sine Wave

DC ACCURACY Any Channel

Resolution 14 14 Bits
Minimum Resolution for Which No

Missing Codes are Guaranteed 14 14 Bits

Relative Accuracy

4

± 2.5 ± 2LSB max

Differential Nonlinearity

4

+2 to –1 +2 to –1LSB max

AD7863-10, AD7863-3

Positive Gain Error

4

± 10 ±8LSB max

Positive Gain Error Match

4

10 10 LSB max

Negative Gain Error

4

± 10 ±8LSB max

Negative Gain Error Match

4

10 10 LSB max
Bipolar Zero Error ± 10 ±8LSB max
Bipolar Zero Error Match 8 6 LSB max

AD7863-2

Positive Gain Error

4

± 14 LSB max
Positive Gain Error Match

4

16 LSB max
Unipolar Offset Error ± 14 LSB max
Unipolar Offset Error Match 10 LSB max

ANALOG INPUTS

AD7863-10

Input Voltage Range ± 10 ±10 Volts
Input Resistance 9 9 kΩ typ

AD7863-3

Input Voltage Range ± 2.5 ± 2.5 Volts
Input Resistance 3 3 kΩ typ

AD7863-2

Input Voltage Range +2.5 +2.5 Volts
Input Current 100 100 nA max

REFERENCE INPUT/OUTPUT

REF IN Input Voltage Range 2.375/2.625 2.375/2.625 2.5 V ± 5%
REF IN Input Current ± 100 ±100 µA max
REF OUT Output Voltage 2.5 2.5 V nom
REF OUT Error @ +25°C ± 10 ±10 mV max
REF OUT Error T

MIN

to T

MAX

± 20 ± 20 mV max

REF OUT Temperature Coefficient 25 25 ppm/°C typ

LOGIC INPUTS

Input High Voltage, V

INH

2.4 2.4 V min VDD = 5 V ± 5%

Input Low Voltage, V

INL

0.8 0.8 V max VDD = 5 V ± 5%

Input Current, I

IN

± 10 ± 10 µA max

Input Capacitance, C

IN

5

10 10 pF max

AD7863

–3–REV. A

AB

Parameter Version

1

Version

1

Units Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, V

OH

4.0 4.0 V min I

SOURCE

= 200 µA

Output Low Voltage, V

OL

0.4 0.4 V max I

SINK

= 1.6 mA

DB11–DB0

Floating-State Leakage Current ±10 ± 10 µA max
Floating-State Capacitance

5

10 10 pF max

Output Coding

AD7863-10, AD7863-3 Twos Complement
AD7863-2 Straight (Natural) Binary

CONVERSION RATE

Conversion Time

Mode 1 Operation 5.2 5.2 µs max For Both Channels
Mode 2 Operation

6

10.0 10.0 µs max For Both Channels

Track/Hold Acquisition Time

4, 7

0.5 0.5 µs max

POWER REQUIREMENTS

V

DD

+5 +5 V nom ± 5% for Specified Performance

I

DD

Normal Mode (Mode 1)

AD7863-10 17 17 mA max
AD7863-3 15 15 mA max
AD7863-2 10 10 mA max

Power-Down Mode (Mode 2)

I

DD

@ +25°C

8

20 20 µA max 40 nA typ. Logic Inputs = 0 V or V

DD

Power Dissipation

Normal Mode (Mode 1)

AD7863-10 89.25 89.25 mW max V

DD

= 5.25 V, Typically 70 mW

AD7863-3 78.75 78.75 mW max V

DD

= 5.25 V, Typically 70 mW

AD7863-2 52.5 52.5 mW max V

DD

= 5.25 V, Typically 45 mW

Power-Down Mode @ +25°C 105 105 µW max Typically 210 nW, VDD = 5.25 V

NOTES

1

Temperature ranges are as follows: A, B Versions: – 40°C to +85°C.

2

Sample tested during initial release.

3

Applies to Mode 1 operation. See section on operating modes.

4

See Terminology.

5

Sample tested @ +25°C to ensure compliance.

6

This 10 µs includes the “wake-up” time from standby. This “wake-up” time is timed from the rising edge of CONVST, whereas conversion is timed from the falling

edge of CONVST, for a narrow CONVST pulsewidth the conversion time is effectively the “wake-up” time plus conversion time, hence 10 µs. This can be seen from
Figure 6. Note that if the CONVST pulsewidth is greater than 5.2 µs, the effective conversion time will increase beyond 10 µs.

7

Performance measured through full channel (multiplexer, SHA and ADC).

8

For best dynamic performance of the AD7863, ATE device testing has to be performed with power supply decoupling in place. In the AD7863 power-down mode of

operation, the leakage current associated with these decoupling capacitors is greater than that of the AD7863 supply current. Therefore the 40 nA typical figure shown
is a characterized and guaranteed by design figure, which reflects the supply current of the AD7863 without decoupling in place. The max figure shown in the Conditions/
Comments column reflects the AD7863 with supply decoupling in place—0.1 µF in parallel with a 10 µF disc ceramic capacitors on the VDD pin and 2 × 0.1 µF disc
ceramic capacitors on the V

REF

pin, in both cases to the AGND plane.

Specifications subject to change without notice.

AD7863

–4–

REV. A

TIMING CHARACTERISTICS

1, 2

A, B

Parameter Versions Units Test Conditions/Comments

t

CONV

5.2 µs max Conversion Time

t

ACQ

0.5 µs max Acquisition Time

Parallel Interface

t

1

0 ns min CS to RD Setup Time

t

2

0 ns min CS to RD Hold Time

t

3

35 ns min CONVST Pulsewidth

t

4

45 ns min Read Pulsewidth

t

5

3

30 ns min Data Access Time after Falling Edge of RD

t

6

4

5 ns min Bus Relinquish Time after Rising Edge of RD
30 ns max

t

7

10 ns min Time Between Consecutive Reads

t

8

400 ns min Quiet Time

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.

2

See Figure 1.

3

Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.0 V.

4

These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.

Specifications subject to change without notice.

(VDD = +5 V  5%, AGND = DGND = 0 V, REF = Internal. All specifications T

MIN

to T

MAX

unless

otherwise noted.)

t

3

t

1

t

4

t

5

t

2

t

6

V

A1

V

A2

V

B1

V

B2

CONVST

BUSY

A0

CS

RD

DATA

t

7

t

CONV

= 5.2s

t

ACQ

t

8

Figure 1. Timing Diagram

TO OUTPUT

PIN

1.6mA

200A

50pF

Figure 2. Load Circuit for Access Time and Bus Relinquish Time

AD7863

–5–REV. A

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

DD

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Analog Input Voltage to AGND

AD7863-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 17 V

AD7863-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 7V

AD7863-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V

Reference Input Voltage to AGND . . . .–0.3 V to V

DD

+ 0.3 V

Digital Input Voltage to DGND . . . . . –0.3 V to V

DD

+ 0.3 V

Digital Output Voltage to DGND . . . . –0.3 V to V

DD

+ 0.3 V

Operating Temperature Range

Commercial (A, B Version) . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 110°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

θ

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 110°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7863 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Model Input Ranges Relative Accuracy Temperature Range Package Options*

AD7863AR-10 ± 10 V ± 2.5 LSB –40°C to +85°C R-28
AD7863BR-10 ± 10 V ± 2.0 LSB –40°C to +85°C R-28
AD7863ARS-10 ± 10 V ± 2.5 LSB –40°C to +85°C RS-28
AD7863AR-3 ± 2.5 V ±2.5 LSB –40°C to +85°C R-28
AD7863ARS-3 ±2.5 V ± 2.5 LSB –40°C to +85°C RS-28
AD7863BR-3 ± 2.5 V ±2.0 LSB –40°C to +85°C R-28
AD7863AR-2 0 V to 2.5 V ±2.5 LSB –40°C to +85°C R-28
AD7863ARS-2 0 V to 2.5 V ± 2.5 LSB –40°C to +85°C RS-28

*R = Small Outline (SOIC), RS = Shrink Small Outline (SSOP).

WARNING!

ESD SENSITIVE DEVICE

AD7863

–6–

REV. A

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

1–6 DB12–DB7 Data Bit 12 to Data Bit 7. Three-state TTL outputs.
7 DGND Digital Ground. Ground reference for digital circuitry.
8 CONVST Convert Start Input. Logic Input. A high to low transition on this input puts both track/holds into their hold

mode and starts conversion on both channels.
9–15 DB6–DB0 Data Bit 6 to Data Bit 0. Three-state TTL outputs.
16 AGND Analog Ground. Ground reference for Mux, track/hold, reference and DAC circuitry.
17 V

B2

Input Number 2 of Channel B. Analog Input voltage ranges of ±10 V (AD7863-10), ± 2.5 V (AD7863-3)

and 0 V–2.5 V (AD7863-2).
18 V

A2

Input Number 2 of Channel A. Analog Input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3)

and 0 V–2.5 V (AD7863-2).
19 V

REF

Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the

output reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this

appears at the pin.
20 A0 Multiplexer Select. This input is used in conjunction with CONVST to determine on which pair of channels

the conversion is to be performed. If A0 is low when the conversion is initiated then channels V

A1, VA2

will

be selected. If A0 is high when the conversion is initiated, channels V

B1, VB2

will be selected.

21 CS Chip Select Input. Active low logic input. The device is selected when this input is active.
22 RD Read Input. Active low logic input. This input is used in conjunction with CS low to enable the data out-

puts and read a conversion result from the AD7863.
23 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVST and remains high until

conversion is completed.
24 V

DD

Analog and Digital Positive Supply Voltage, +5.0 V ± 5%.
25 V

A1

Input Number 1 of Channel A. Analog Input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3)

and 0 V–2.5 V (AD7863-2).
26 V

B1

Input Number 1 of Channel B. Analog Input voltage ranges of ±10 V (AD7863-10), ± 2.5 V (AD7863-3)

and 0 V–2.5 V (AD7863-2).
27 AGND Analog Ground. Ground reference for Mux, track/hold, reference and DAC circuitry.
28 DB13 Data Bit 13 (MSB). Three-state TTL output. Output coding is twos complement for the AD7863-10 and

AD7863-3. Output coding is straight (natural) binary for the AD7863-2.

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

AD7863

DB1

DB2

DB3

DB4

DB5

DB6

CONVST

DB12

DB11

DB10

DB9

DGND

DB7

DB8

V

A2

V

REF

A0

CS

DB13

AGND

V

B1

V

A1

RD

BUSY

V

DD

V

B2

AGND

DB0