REV. B
–2–
AD7814–SPECIFICATIONS
1, 2
Parameter Min Typ Max Units Test Conditions/Comments
TEMPERATURE SENSOR AND ADC
Accuracy ± 2.0 °CT
A
= 0°C to +85°C. VDD = +3 V to +5.5 V
3
± 2.5 °CT
A
= –40°C to 0°C. VDD = +3 V to +5.5 V
3
± 2.0 ± 3.5 °CT
A
= –55°C to +125°C. VDD = +3 V to +5.5 V
Resolution 10 Bits
Update Rate, t
R
400 µs
Temperature Conversion Time 25 µs
SUPPLIES
Supply Voltage 2.7 5.5 V For Specified Performance
Supply Current
Normal Mode 250 400 µA
Shutdown Mode 1 3 µA
Power Dissipation 80 µWV
DD
= +3 V. Using Normal Mode
Power Dissipation V
DD
= +3 V. Using Shutdown Mode
1 sps 3 µW
10 sps 3.3 µW
100 sps 6 µW
DIGITAL INPUT
Input High Voltage, V
IH
2.4 V
Input Low Voltage, V
IL
0.8 V
Input Current, I
IN
± 1 µAV
IN
= 0 V to V
DD
Input Capacitance, C
IN
10 pF All Digital Inputs
DIGITAL OUTPUT
Output High Voltage, V
OH
VDD – 0.3 V I
SOURCE
= I
SINK
= 200 µA
Output Low Voltage, V
OL
0.4 V IOL = 200 µA
Output Capacitance, C
OUT
50 pF
NOTES
1
All specifications apply for –55°C to +125°C unless otherwise stated.
2
Guaranteed by design and characterization, not production tested.
3
For VDD = +2.7 V to +3 V and TA = –40°C to +85°C, the typical temperature error is ±2°C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2, 3
Parameter Limit Units Comments
t
1
0 ns min CS to SCLK Setup Time
t
2
50 ns min SCLK High Pulsewidth
t
3
50 ns min SCLK Low Pulsewidth
t
4
4
35 ns max Data Access Time After SCLK Falling Edge
t
5
20 ns min Data Setup Time Prior to SCLK Rising Edge
t
6
0 ns min Data Hold Time After SCLK Rising Edge
t
7
0 ns min CS to SCLK Hold Time
t
8
4
40 ns max CS to DOUT High Impedance
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
3
See Figure 2.
4
Measured with the load circuit of Figure 1.
(TA = T
MIN
to T
MAX
, VDD = +2.7 V to +5.5 V, unless otherwise noted)
(TA = T
MIN
to T
MAX
, VDD = +2.7 V to +5.5 V, unless otherwise noted)