Analog Devices AD7811YRU, AD7811YR, AD7811YN, AD7812YRU, AD7812YR Datasheet

2.7 V to 5.5 V, 350 kSPS, 10-Bit

a

FEATURES
10-Bit ADC with 2.3 ␮s Conversion Time
The AD7811 has Four Single-Ended Inputs that

Can Be Configured as Three Pseudo Differential
Inputs with Respect to a Common, or as Two Inde­pendent Pseudo Differential Channels

The AD7812 has Eight Single-Ended Inputs that Can

Be Configured as Seven Pseudo Differential Inputs
with Respect to a Common, or as Four Independent

Pseudo Differential Channels
Onboard Track and Hold
Onboard Reference 2.5 V ⴞ 2.5%
Operating Supply Range: 2.7 V to 5.5 V
Specifications at 2.7 V–3.6 V and 5 V ⴞ 10%
DSP-/Microcontroller-Compatible Serial Interface
High Speed Sampling and Automatic Power-Down Modes
Package Address Pin on the AD7811 and AD7812 Allows

Sharing of the Serial Bus in Multipackage Applications
Input Signal Range: 0 V to V
Reference Input Range: 1.2 V to V

GENERAL DESCRIPTION

The AD7811 and AD7812 are high speed, low power, 10-bit
A/D converters that operate from a single 2.7 V to 5.5 V supply.
The devices contain a 2.3 µs successive approximation A/D
converter, an on-chip track/hold amplifier, a 2.5 V on-chip refer­ence and a high speed serial interface that is compatible with the
serial interfaces of most DSPs (Digital Signal Processors) and
microcontrollers. The user also has the option of using an exter­nal reference by connecting it to the V
EXTREF bit in the control register. The V
to V

. At slower throughput rates the power-down mode may

DD

be used to automatically power down between conversions.

REF

DD

pin and setting the

REF

REF

pin may be tied

4-/8-Channel Sampling ADCs

AD7811/AD7812

The control registers of the AD7811 and AD7812 allow the
input channels to be configured as single-ended or pseudo
differential. The control register also features a software convert
start and a software power-down. Two of these devices can
share the same serial bus and may be individually addressed in
a multipackage application by hardwiring the device address pin.
The AD7811 is available in a small, 16-lead 0.3" wide, plastic
dual-in-line package (mini-DIP), in a 16-lead 0.15" wide, Small
Outline IC (SOIC) and in a 16-lead, Thin Shrink Small Out­line Package (TSSOP). The AD7812 is available in a small,
20-lead 0.3" wide, plastic dual-in-line package (mini-DIP), in a
20-lead, Small Outline IC (SOIC) and in a 20-lead, Thin Shrink
Small Outline Package (TSSOP).

PRODUCT HIGHLIGHTS

1. Low Power, Single Supply Operation
Both the AD7811 and AD7812 operate from a single 2.7 V
to 5.5 V supply and typically consume only 10 mW of power.
The power dissipation can be significantly reduced at
lower throughput rates by using the automatic power­down mode e.g., 315 µW @ 10 kSPS, V
Power vs. Throughput.

2. 4-/8-Channel, 10-Bit ADC
The AD7811 and AD7812 have four and eight single-ended
input channels respectively. These inputs can be configured
as pseudo differential inputs by using the Control Register.

3. On-chip 2.5 V (±2.5%) reference circuit that is powered
down when using an external reference.

4. Hardware and Software Control
The AD7811 and AD7812 provide for both hardware and
software control of Convert Start and Power-Down.

= 3 V—see

DD

FUNCTIONAL BLOCK DIAGRAMS

IN

CLOCK

CHARGE

DAC

COMP

OSC

V

AGND

DD

DGND

AD7811

DOUT

SERIAL

PORT

CONTROL

LOGIC

CONVST

A0

DIN

RFS

TFS

SCLK

BUF

VDD/3

1.23V
REF

REF

REDISTRIBUTION

C

REF

V

IN1

V

IN2

V

IN3

V

IN4

MUX

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

IN

CLOCK

CHARGE

DAC

COMP

OSC

V

AGND

DD

DGND

AD7812

DOUT

SERIAL

PORT

CONTROL

LOGIC

A0

CONVST

DIN
RFS

TFS
SCLK

1.23V

BUF

VDD/3

REF

REF

REDISTRIBUTION

C

REF

V

IN1

V

IN2

V

IN3

V

IN4

V

IN5

V

IN6

V

IN7

V

IN8

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

MUX

(VDD = 2.7 V to 3.6 V, VDD = 5 V ⴞ 10%, GND = 0 V, V

AD7811/AD7812–SPECIFICATIONS

[EXT]. All specifications –40ⴗC to +105ⴗC unless otherwise noted.)

Parameter Y Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE f

Signal to (Noise + Distortion) Ratio
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion

1, 2

1

1

1

58 dB min V
–66 dB max
–80 dB typ

= 30 kHz Any Channel, f

IN

Internal or External

REF

fa = 29 kHz, fb = 30 kHz

SAMPLE

Second Order Terms –67 dB max
Third Order Terms –67 dB max

Channel-to-Channel Isolation

1, 2

–80 dB typ fIN = 20 kHz

DC ACCURACY Any Channel

Resolution 10 Bits
Minimum Resolution for Which

No Missing Codes are Guaranteed 10 Bits
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Match
Offset Error
Offset Error Match

1

1

1

1

1

1

± 1 LSB max
± 1 LSB max
± 2 LSB max
± 0.75 LSB max
± 2 LSB max
± 0.75 LSB max

ANALOG INPUT

Input Voltage Range 0 V min

V
Input Leakage Current
Input Capacitance

REFERENCE INPUTS

V

Input Voltage Range 1.2 V min

REF

2

2

2

REF

± 1 µA max

20 pF max

V

DD

V max

V max
Input Leakage Current ± 3 µA max
Input Capacitance 20 pF max

ON-CHIP REFERENCE Nominal 2.5 V

Reference Error ± 2.5 % max
Temperature Coefficient 50 ppm/°C typ

LOGIC INPUTS

V

Input High Voltage 2.4 V min VDD = 5 V ± 10%

INH,

V

, Input Low Voltage 0.8 V max VDD = 5 V ± 10%

INL

V

Input High Voltage 2 V min VDD = 3 V ± 10%

INH,

, Input Low Voltage 0.4 V max VDD = 3 V ± 10%

V

INL

Input Current, I
Input Capacitance, C

2

IN

IN

± 1 µA max Typically 10 nA, VIN = 0 V to V
8 pF max

LOGIC OUTPUTS

Output High Voltage, V

Output Low Voltage, V

OL

OH

4V minV

2.4 V min V

I

= 200 µA

SOURCE

= 5 V ± 10%

DD

= 3 V ± 10%

DD

I

= 200 µA

SINK

0.4 V max
High Impedance Leakage Current ± 1 µA max
High Impedance Capacitance 15 pF max

CONVERSION RATE

Conversion time 2.3 µs max
Track/Hold Acquisition Time

1

200 ns max

= V

REF

= 350 kHz

DD

DD

–2–

REV. B

AD7811/AD7812

Parameter Y Version Unit Test Conditions/Comments

POWER SUPPLY

V

DD

I

DD

Normal Operation 3.5 mA max
Power-Down
Full Power-Down 1 µA max
Partial Power-Down (Internal Ref) 350 µA max See Power-Up Times Section

Power Dissipation V

Normal Operation 10.5 mW max
Auto Full Power-Down See Power vs. Throughput Section

Throughput 1 kSPS 31.5 µW max
Throughput 10 kSPS 315 µW max

Throughput 100 kSPS 3.15 mW max
Partial Power-Down (Internal Ref) 1.05 mW max
Full Power-Down 3 µW max

NOTES

1

See Terminology.

2

Sample tested during initial release and after any redesign or process change that may affect this parameter.

Specifications subject to change without notice.

TIMING CHARACTERISTICS

1, 2

2.7 V min For Specified Performance

5.5 V max
Digital Inputs = 0 V or V

= 3 V

DD

(VDD = 2.7 V to 5.5 V, V

= VDD [EXT] unless otherwise noted)

REF

DD

Parameter Y Version Unit Conditions/Comments

t

POWER-UP

t

1

t

2

t

3

t

4

3

t

5

3

t

6

3

t

7

t

8

t

9

3, 4

t

10

t

11

NOTES

1

Sample tested to ensure compliance.

2

See Figures 16, 17 and 18.

3

These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V

0.4 V or 2 V for VDD = 3 V ± 10%.

4

Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t11, quoted in the Timing Characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.

Specifications subject to change without notice.

1.5 µs (max) Power-Up Time of AD7811/AD7812 after Rising Edge of CONVST

2.3 µs (max) Conversion Time
20 ns (min) CONVST Pulsewidth
25 ns (min) SCLK High Pulsewidth
25 ns (min) SCLK Low Pulsewidth
5 ns (min) RFS Rising Edge to SCLK Rising Edge Setup Time
5 ns (min) TFS Falling Edge to SCLK Falling Edge Setup Time
10 ns (max) SCLK Rising Edge to Data Out Valid
10 ns (min) DIN Data Valid to SCLK Falling Edge Setup Time
5 ns (min) DIN Data Valid after SCLK Falling Edge Hold Time
20 ns (max) SCLK Rising Edge to D

OUT

High Impedance

100 ns (min) DOUT High Impedance to CONVST Falling Edge

= 5 V ± 10% and

DD

I

OL

2.1V

I

OH

TO

OUTPUT

PIN

50pF

200␮A

C

L

200␮A

Figure 1. Load Circuit for Digital Output Timing Specifications

–3–REV. B

AD7811/AD7812

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to DGND (CONVST, SCLK, RFS, TFS,

DIN, A0) . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V

DD

+ 0.3 V

Digital Output Voltage to DGND (DOUT)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V

REF

to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, V

IN

+ 0.3 V

DD

+ 0.3 V

DD

Analog Inputs

V

IN1–VIN4

V

IN1–VIN8

(AD7811) . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V

(AD7812) . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W

θ

JA

Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . . 260°C

ORDERING GUIDE

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

Linearity Package Package

Model Error Descriptions Options

AD7811YN ± 1 LSB 16-Lead Plastic DIP N-16
AD7811YR ± 1 LSB 16-Lead Small Outline IC (SOIC) R-16A
AD7811YRU ± 1 LSB 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16

AD7812YN ± 1 LSB 20-Lead Plastic DIP N-20
AD7812YR ± 1 LSB 20-Lead Small Outline IC (SOIC) R-20A
AD7812YRU ± 1 LSB 20-Lead Thin Shrink Small Outline Package (TSSOP) RU-20

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7811/AD7812 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

–4–

REV. B

PIN CONFIGURATIONS

14

13

12

11

17

16

15

20

19

18

10

9

8

1

2

3

4

7

6

5

TOP VIEW

(Not to Scale)

AD7812

V

REF

DIN

SCLK

V

DD

C

REF

V

IN1

AGND

TFS

RFS

DOUT

V

IN2

V

IN3

V

IN4

V

IN5

V

IN6

V

IN7

V

IN8

A0

DGND

CONVST

DIP/SOIC/TSSOP

AD7811/AD7812

V

REF

C

REF

V

AGND

V

V

V

IN1

IN2

IN3

IN4

A0

1

2

3

AD7811

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

15

14

13

12

11

10

9

V

DD

CONVST

SCLK

DIN

DOUT

RFS

TFS

DGND

PIN FUNCTION DESCRIPTIONS

Pin(s) Pin(s)
AD7811 AD7812 Mnemonic Description

11 V

22 C

REF

REF

An external reference input can be applied here. When using an external precision
reference or V
external reference input range is 1.2 V to V

the EXTREF bit in the control register must be set to logic one. The

DD

DD

.

Reference Capacitor. A capacitor (10 nF) is connected here to improve the noise
performance of the on-chip reference.

3, 5–7 3, 5–11 V

IN1–VIN4(8)

Analog Inputs. The analog input range is 0 V to V

REF

.

4 4 AGND Analog Ground. Ground reference for track/hold, comparator, on-chip reference and

DAC.

8 12 A0 Package Address Pin. This Logic Input can be hardwired high or low. When used in

conjunction with the package address bit in the control register this input allows two
devices to share the same serial bus. For example a twelve channel solution can be

achieved by using the AD7811 and the AD7812 on the same serial bus.
9 13 DGND Digital Ground. Ground reference for digital circuitry.
10 14 TFS Transmit Frame Sync. The falling edge of this Logic Input tells the part that a new

control byte should be shifted in on the next 10 falling edges of SCLK.
11 15 RFS Receive Frame Sync. The rising edge of this Logic Input is used to enable a counter in

the serial interface. It is used to provide compatibility with DSPs which use a continuous

serial clock and framing signal. In multipackage applications the RFS Pin can also be

used as a serial bus select pin. The serial interface will ignore the SCLK until it receives a

rising edge on this input. The counter is reset at the end of a serial read operation.
12 16 DOUT Serial Data Output. Serial data is shifted out on this pin on the rising edge of the serial

clock. The output enters a High impedance condition on the rising edge of the 11th

SCLK pulse.
13 17 DIN Serial Data Input. The control byte is read in at this input. In order to complete a

serial write operation 13 SCLK pulses need to be provided. Only the first 10 bits are

shifted in—see Serial Interface section.
14 18 SCLK Serial Clock Input. An external serial clock is applied to this input to obtain serial data

15 19 CONVST Convert Start. This is an edge triggered logic input. The Track/Hold goes into its Hold

16 20 V

DD

from the AD7811/AD7812 and also to latch data into the AD7811/AD7812. Data is

clocked out on the rising edge of SCLK and latched in on the falling edge of SCLK.

Mode on the falling edge of this signal and a conversion is initiated. The state of this

pin at the end of conversion also determines whether the part is powered down or not.

See operating modes section of this data sheet.

Positive Supply Voltage 2.7 V to 5.5 V.

–5–REV. B

AD7811/AD7812

TERMINOLOGY
Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f

/2), excluding dc.

S

The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distor­tion) ratio for an ideal N-bit converter with a sine wave input
is given by:

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

Thus for a 10-bit converter, this is 62 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7811 and AD7812
it is defined as:

2

2

2

2

2

+V

5

6

THD (dB) = 20 log

V

+V

+V

2

+V

3

4

V

1

where V1 is the rms amplitude of the fundamental and V2, V3,

V

, V5 and V6 are the rms amplitudes of the second through the

4

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f

/2 and excluding dc) to the rms value of the

S

fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor, it will
be a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for
which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).

The AD7811 and AD7812 are tested using the CCIF standard
where two input frequencies near the top end of the input
bandwidth are used. In this case, the second and third order
terms are of different significance. The second order terms are

usually distanced in frequency from the original sine waves
while the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third order
terms are specified separately. The calculation of the inter­modulation distortion is as per the THD specification where it is
the ratio of the rms sum of the individual distortion products to
the rms amplitude of the fundamental expressed in dBs.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full­scale 20 kHz sine wave signal to all nonselected input channels
and determining how much that signal is attenuated in the selected
channel. The figure given is the worst case across all four or
eight channels for the AD7811 and AD7812 respectively.

Relative Accuracy

Relative accuracy, or endpoint nonlinearity, is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.

Differential Nonlinearity

This is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (0000 . . . 000)
to (0000 ...001) from the ideal, i.e., AGND + 1 LSB.

Offset Error Match

This is the difference in Offset Error between any two channels.

Gain Error

This is the deviation of the last code transition (1111 . . . 110)
to (1111 ...111) from the ideal, i.e., V

– 1 LSB, after the

REF

offset error has been adjusted out.

Gain Error Match

This is the difference in Gain Error between any two channels.

Track/Hold Acquisition Time

Track/hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
± 1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where a change in the selected input channel takes place or
where there is a step input change on the input voltage applied
to the selected V

input of the AD7811 or AD7812. It means

IN

that the user must wait for the duration of the track/hold acquisi­tion time after the end of conversion or after a channel change/
step input change to V

before starting another conversion, to

IN

ensure that the part operates to specification.

–6–

REV. B