Analog Devices AD7783 b Datasheet

Read-Only, Pin Configured 24-Bit ⌺-⌬ ADC

with Excitation Current Sources

AD7783

FEATURES
Single-Channel, 24-Bit ⌺-⌬ ADC
Pin Configurable (No Programmable Registers)

ISOURCE Select

™

Pin Programmable Input Ranges (±2.56 V or ± 160 mV)

Fixed 19.79 Hz Update Rate
Simultaneous 50 Hz and 60 Hz Rejection
24-Bit No Missing Codes

18.5-Bit p-p Resolution (±2.56 V Range)

16.5-Bit p-p Resolution (±160 mV Range)

INTERFACE
Master or Slave Mode of Operation
Slave Mode

3-Wire Serial

®

, QSPI™, MICROWIRE™, and DSP-Compatible

SPI
Schmitt Trigger on SCLK

POWER
Specified for Single 3 V and 5 V Operation
Normal: 1.3 mA @ 3 V
Power-Down: 9 ␮A

ON-CHIP FUNCTIONS
Rail-to-Rail Input Buffer and PGA

APPLICATIONS
Sensor Measurement
Industrial Process Control
Temperature Measurement
Pressure Measurement
Weigh Scales
Portable Instrumentation

IOUT1

IOUT2

IPIN

AIN(+)

AIN(–)

FUNCTIONAL BLOCK DIAGRAM

V

DD

IEXC1

200␮A

MUX

AD7783

BUF

GND

V

DD

IEXC2
200␮A

PGA

RANGE

REFIN(+)

24-BIT ⌺-⌬

REFIN(–)

ADC

BASIC CONNECTION DIAGRAM

POWER SUPPLY

V

DD

AD7783

ANALOG

INPUT

CURRENT
SOURCES

REFERENCE

INPUT

AIN(+)
AIN(–)

IOUT1
IOUT2

REFIN(+)
REFIN(–)

CS

DOUT/RDY

SCLK

XTAL1

XTAL2

GND

XTAL1

XTAL2

OSCILLATOR

AND

PLL

SERIAL

INTERFACE

AND

CONTROL

LOGIC

DIGITAL
INTERFACE

32.768kHz
CRYSTAL

DOUT/RDY

SCLK

MODE

CS

GENERAL DESCRIPTION

The AD7783 is a complete analog front end for low frequency
measurement applications. The 24-bit sigma-delta ADC con­tains one fully differential input channel that can be configured
with a gain of 1 or 16 allowing full-scale input signal ranges of
± 2.56 V or ± 160 mV from a +2.5 V differential reference input.
It also contains two 200 mA integrated current sources.

The AD7783 has an extremely simple, read-only digital inter­face that can be operated in master mode or slave mode.
There are no on-chip registers to be programmed. The input
signal range and current source selection are configured using
two external pins.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

The device operates from a 32.768 kHz crystal with an on-chip
PLL generating the required internal operating frequency. The
output data rate from the part is fixed via the master clock at

19.79 Hz and provides simultaneous 50 Hz and 60 Hz rejection
at this update rate. At this update rate, 18-bit p-p resolution can
be obtained.

The part operates from a single 3 V or 5 V supply. When oper­ating from 3 V supplies, the power dissipation for the part is

3.9 mW. The AD7783 is available in a 16-lead TSSOP.

Another part in the AD778x family is the AD7782. It is similar
to the AD7783 except it has no integrated current sources and
two differential input channels.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

1

AD7783–SPECIFICATIONS

GND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications T

Parameter AD7783B Unit Test Conditions

ADC CHANNEL SPECIFICATION

Output Update Rate 19.79 Hz nom

ADC CHANNEL

No Missing Codes
Resolution 16 Bits p-p ± 160 mV Range, RANGE = 0

Output Noise See Table I
Integral Nonlinearity ± 10 ppm of FSR max Typically 2 ppm,
Offset Error ± 3 mV typ AIN(+) = AIN(–) = 2.5 V
Offset Error Drift versus Temperature ± 10 nV/∞C typ
Full-Scale Error ± 10 mV typ V
Gain Drift versus Temperature ± 0.5 ppm/∞C typ
Power Supply Rejection (PSR) 100 dB typ Input Range = ± 160 mV, V

ANALOG INPUTS

Differential Input Voltage Ranges ± 160 mV nom Range = 0

ADC Range Matching ± 2 mV typ Input Voltage = 159 mV on Both Ranges
Absolute AIN Voltage Limits GND + 100 mV V min

Analog Input Current

DC Input Current ± 1nA max
DC Input Current Drift ± 5pA/∞C typ

Normal-Mode Rejection

@ 50 Hz 60 dB min 50 Hz ± 1 Hz
@ 60 Hz 94 dB min 60 Hz ± 1 Hz

Common-Mode Rejection Input Range = ± 160 mV, V

@ DC 105 dB min 125 dB typ,

@ 50 Hz
@ 60 Hz

REFERENCE INPUT

REFIN Voltage 2.5 V nom REFIN = REFIN(+) – REFIN(–)
REFIN Voltage Range

Absolute REFIN Voltage Limits

Average Reference Input Current 0.5 mA/V typ
Average Reference Input Current Drift ± 0.01 nA/V/∞C typ
Normal-Mode Rejection

@ 50 Hz 60 dB min 50 Hz ± 1 Hz
@ 60 Hz 94 dB min 60 Hz ± 1 Hz

Common-Mode Rejection Input Range = ± 160 mV, V

@ DC 100 dB typ
@ 50 Hz 110 dB typ 50 Hz ± 1 Hz
@ 60 Hz 110 dB typ 60 Hz ± 1 Hz

EXCITATION CURRENT SOURCES
(IEXC1, IEXC2)

Output Current 200 mA
Initial Tolerance at 25∞C ± 10 % typ
Drift 200 ppm/∞C typ
Initial Current Matching at 25∞C ± 2.5 % max No Load
Drift Matching 20 ppm/∞C typ
Line Regulation 2.5 mA/V max V
Load Regulation 300 nA/V typ
Output Compliance V

2

24 Bits min

18 Bits p-p ± 2.56 V Range, RANGE = 1

85 dB typ Input Range = ± 2.56 V, VIN = 1 V

± 2.56 V nom Range = 1

V

2

2, 3

2

2

2

2

2, 3

DD

100 dB min 50 Hz ± 1 Hz
100 dB min 60 Hz ± 1 Hz

1V min
V

DD

GND – 30 mV V min
V

DD

DD

GND – 30 mV V min

(VDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = GND;

to T

MIN

, unless otherwise noted.)

MAX

DD

= 3 V

FSR

=

– 100 mV V max

110 dB typ when Input Range = ± 2.56 V

V max

+ 30 mV V max

= 5 V ± 5%. Typically 1.25 mA/V.

DD

– 0.6 V max

¥21024.

Gain

= 1/16 V

IN

= 1/16 V

IN

= 1/16 V

IN

REFIN

REV. B–2–

Parameter AD7783B Unit Test Conditions

LOGIC INPUTS

All Inputs Except SCLK and XTAL1

V

, Input Low Voltage 0.8 V max VDD = 5 V

INL

, Input High Voltage 2.0 V min VDD = 3 V or 5 V

V

INH

SCLK Only (Schmitt-Triggered Input)

V

T(+)

V

T(–)

– V

V

T(+)

V
V
V

XTAL1 Only

V
V
V
V

T(–)

T(+)

T(–)

– V

T(+)

T(–)

2

, Input Low Voltage 0.8 V max VDD = 5 V

INL

, Input High Voltage 3.5 V min VDD = 5 V

INH

, Input Low Voltage 0.4 V max VDD = 3 V

INL

, Input High Voltage 2.5 V min VDD = 3 V

INH

Input Currents ± 1 mA max V

2

0.4 V max V

2

1.4/2 V min/V max VDD = 5 V

0.8/1.4 V min/V max VDD = 5 V

0.3/0.85 V min/V max VDD = 5 V

0.95/2 V min/V max VDD = 3 V

0.4/1.1 V min/V max VDD = 3 V

0.3/0.85 V min/V max VDD = 3 V

DD

IN

= V

= 3 V

DD

–70 mA max VIN = GND, Typically –40 mA at 5 V and

–20 mA at 3 V

Input Capacitance 10 pF typ All Digital Inputs

LOGIC OUTPUTS (Excluding XTAL2)

, Output High Voltage

V

OH

V

, Output Low Voltage

OL

, Output High Voltage

V

OH

, Output Low Voltage

V

OL

2

2

2

2

VDD – 0.6 V min VDD = 3 V, I

0.4 V max VDD = 3 V, I
4V minV

= 5 V, I

DD

0.4 V max VDD = 5 V, I

SOURCE

= 100 mA

SINK

SOURCE

= 1.6 mA

SINK

= 100 mA

= 200 mA

Floating-State Leakage Current ± 10 mA max
Floating-State Output Capacitance ± 10 pF typ
Data Output Coding Offset Binary

START-UP TIME

From Power-On 300 ms typ

POWER REQUIREMENTS

Power Supply Voltage

– GND 2.7/3.6 V min/V max VDD = 3 V nom

V

DD

Power Supply Currents

Current (Normal Mode)

I

DD

(Power-Down Mode, CS = 1) 9 mA max VDD = 3 V, 6 mA typ

I

DD

4

4.75/5.25 V min/V max V

= 5 V nom

DD

1.5 mA max VDD = 3 V, 1.3 mA typ

1.7 mA max V

= 5 V, 1.5 mA typ

DD

24 mA max VDD = 5 V, 20 mA typ

NOTES

1

Temperature range –40∞C to +85∞C.

2

Guaranteed by design and/or characterization data on production release.

3

When a 28.8 kHz crystal is used, normal-mode rejection is improved so that the rejection equals 75 dB at 50 Hz ± 1 Hz and equals 66 dB at 60 Hz ± 1 Hz.

4

Normal mode refers to the case where the ADC is running.

Specifications subject to change without notice.

AD7783

REV. B

–3–

AD7783

TIMING CHARACTERISTICS

1, 2

(VDD = 2.7 V to 3.6 V or VDD = 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz;

Input Logic 0 = 0 V, Logic 1 = VDD, unless otherwise noted.)

Limit at T

MIN

, T

MAX

Parameter (B Version) Unit Conditions/Comments

t

1

t

ADC

t

2

t

3

t

4

3

30.5176 ms typ Crystal Oscillator Period

50.54 ms typ 19.79 Hz Update Rate
0 ns min CS Falling Edge to DOUT Active
60 ns max V
80 ns max V
2 ¥ t

ADC

ns typ Channel Settling Time

0 ns min SCLK Active Edge to Data Valid Delay

= 4.75 V to 5.25 V

DD

= 2.7 V to 3.6 V

DD

4

60 ns max VDD = 4.75 V to 5.25 V

5

t

7

80 ns max V
10 ns min Bus Relinquish Time after CS Inactive Edge

= 2.7 V to 3.6 V

DD

80 ns max

t

8

t

9

0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time
10 ns min SCLK Inactive to DOUT High
80 ns max

Slave Mode Timing

t

5

t

6

100 ns min SCLK High Pulse Width
100 ns min SCLK Low Pulse Width

Master Mode Timing

t

5

t

6

t

10

t1/2 ms typ SCLK High Pulse Width
t1/2 ms typ SCLK Low Pulse Width
t1/2 ms min DOUT Low to First SCLK Active Edge

4

3t1/2 ms max

NOTES

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2

See Figure 2.

3

These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.

4

SCLK active edge is falling edge of SCLK.

5

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means the times quoted in the timing characteristics are the true bus relin­quish times of the part and as such are independent of external bus loading capacitances.

I

(1.6mA WITH VDD = 5V

TO OUTPUT

PIN

50pF

SINK

100␮A WITH V

I

( 200␮A WITH VDD = 5V

SOURCE

100␮A WITH V

1.6V

DD

= 3V)

DD

= 3V)

Figure 1. Load Circuit for Timing Characterization

REV. B–4–