Analog Devices AD7760 prn Datasheet

2.5 MSPS, 20-Bit

Σ∆

ADC

Preliminary Technical Data

FEATURES

High performance 20-bit Sigma-Delta ADC 118dB SNR at 78kHz output data rate 100dB SNR at 2.5MHz output data rate

2.5 MHz maximum fully filtered output word rate Programmable over-sampling rate (8x to 256x) Flexible parallel interface Fully differential modulator input On-chip differential amplifier for signal buffering Low pass FIR filter with default or user programmable

coefficients Over-range alert bit Digital offset and gain correction registers Filter bypass modes Low power and power down modes

SYNC

Synchronization of multiple devices via

APPLICATIONS

Data acquisition systems Vibration analysis Instrumentation

PRODUCT OVERVIEW

The AD7760 high performance 20-bit sigma delta analog to digital converter combines wide input bandwidth and high speed with the benefits of sigma delta conversion with performance of 100dB SNR at 2.5MSPS making it ideal for high speed data acquisition. Wide dynamic range combined with significantly reduced anti-aliasing requirements simplify the design process. An integrated buffer to drive the reference, a differential amplifier for signal buffering and level shifting, an over-range flag, internal gain & offset registers and a low-pass digital FIR filter make the AD7760 a compact highly integrated data acquisition device requiring minimal peripheral component selection. In addition the device offers programmable decimation rates and the digital FIR filter can be adjusted if the default characteristics are not appropriate to the application. The AD7760 is ideal for applications demanding high SNR without necessitating design of complex front end signal processing.

AD7760

FUNCTIONAL BLOCK DIAGRAM

VIN+VIN-

AV

Multi-Bit

Sigma-Delta

Modulator

Reconstruction

VREF+

+ BUF

-

DIFF

AD7760

MCLK

SYNC

RESET

Control Logic,

I/O and

Registers

DB0 - DB15

CS

DRDY

RD/WR

Figure 1.

The differential input is sampled at up to 40MS/s by an analog modulator. The modulator output is processed by a series of low-pass filters, the final one having default or user programmable coefficients. The sample rate, filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7760.

The reference voltage supplied to the AD7760 determines the analog input range. With a 4V reference, the analog input range is ±3.2V differential biased around a common mode of 2V. This common mode biasing can be achieved using the on-chip differential amplifiers, further reducing the external signal conditioning requirements.

The AD7760 is available in an exposed paddle 64-lead TQFP and 48-lead CSP packages and is specified over the industrial temperature range from -40°C to +85°C.

Programmable

Decimation

FIR Filter

Engine

DD1

AV

DD2

AV

DD3

AV

DD4

DECAP

R

BIAS

AGND

V

DRIVE

DV

DD

DGND

Rev. PrN

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7760 Preliminary Technical Data

AD7760—SPECIFICATIONS

Table 1. V

Parameter Test Conditions/Comments Specifcation Unit

DYNAMIC PERFORMANCE Decimate by 256 MCLK = 24.576MHz, ODR = 48kHz, FIN = 1kHz Sine Wave

Signal to Noise Ratio (SNR) Spurious Free Dynamic Range (SFDR) 1 Non-harmonic 118 dBFS typ Total Harmonic Distortion (THD) Intermodulation Distortion (IMD)

Decimate by 16 MCLK = 40MHz, ODR = 1.25MHz, FIN =100kHz Sine Wave

Signal to Noise Ratio (SNR) Spurious Free Dynamic Range (SFDR) 1 Non-harmonic 103 dBFS typ Total Harmonic Distortion (THD) Intermodulation Distortion (IMD)

Decimate by 8 MCLK = 40MHz, ODR = 2.5MHz, FIN = 100kHz Sine Wave

Signal to Noise Ratio (SNR) Spurious Free Dynamic Range (SFDR) 1 Non-harmonic 100 dBFS typ Total Harmonic Distortion (THD) Intermodulation Distortion (IMD) Intermodulation Distortion (IMD)

DC ACCURACY

Resolution 20 Bits Integral Nonlinearity Differential Nonlinearity Offset Error1 0.03 % typ Gain Error1 5 LSB typ Offset Error Drift 0.0006 % /°C

Gain Error Drift 0.1 LSB /°C DIGITAL FILTER RESPONSE Decimate by 8

Group Delay MCLK = 40MHz 12 µS typ Decimate by 16

Group Delay MCLK = 40MHz 24 µS typ Decimate by 128

Group Delay MCLK = 24.576MHz 480 µS typ ANALOG INPUT

Differential Input Voltage Vin(+) – Vin(-), V

Vin(+) – Vin(-), V

DC Leakage Current ±2 µA max

Input Capacitance With internal buffer 5 pF typ

With external buffer 55 pF typ REFERENCE INPUT/OUTPUT

V

REF

V

REF

V

REF

POWER REQUIREMENTS

AV

DV

V

DRIVE

= 2.5 V, V

DD1

Input Voltage V

DD2

1

= 5 V, V

1

= 4.096 V, TA = +25°C, Full Power Mode, unless otherwise noted

REF

118 dB typ

1

Input Amplitude = -6dB -100 dB typ

-100 dB typ

103 dB typ

1

Input Amplitude = -6dB -100 dB typ

-100 dB typ

100 dB typ

1

Input Amplitude = -6dB -100 dB typ FIN = 100kHz Sine Wave -100 dB typ FIN = 1MHz Sine Wave -100 dB typ

At 18 bits 1 LSB typ Guaranteed monotonic to 20 bits 1 LSB typ

= 2.5V ±2 V pk-pk

REF

= 4.096V ±3.25 V pk-pk

REF

= 3.3V +2.5 Volts

DD3

= 5V +4.096 Volts

DD3

Input DC Leakage Current ±1 µA max Input Capacitance 5 pF max

(Modulator Supply) ±5% +2.5 Volts

DD1

(General Supply) ±5% +5 Volts

DD2

(Diff-Amp Supply) +3.0/+5.5 V min/max

DD3

(Ref Buffer Supply) +3.15/+5.25 V min/max

DD4

DD

±5% +2.5 Volts +1.65/+2.7 V min/max

Rev. PrN | Page 3 of 22

AD7760 Preliminary Technical Data

Parameter Test Conditions/Comments Specifcation Unit

Full Power Mode

AI

(Modulator) 50 mA typ

DD1

AI

(General) 35 mA typ

DD2

AI

(Reference Buffer) AV

DD4

Low Power Mode

AI

(Modulator) 26 mA typ

DD1

AI

(General) 20 mA typ

DD2

AI

(Reference Buffer) AV

DD4

AI

(Diff Amp) AV

DD3

D

IDD

Standby Mode

AI

(Modulator) 210 µA typ

DD1

AI

(General) 30 nA typ

DD2

AI

(Diff Amp) AV

DD3

AI

(Reference Buffer) AV

DD4

D

IDD

Clock Running 690 µA typ POWER DISSIPATION Full Power Mode

Modulator (P1) 125 mW typ

General (P2) 175 mW typ

Reference Buffer (P4) AV

AV

Low Power Mode

Modulator (P1) 65 mW typ

General (P2) 100 mW typ

Reference Buffer (P4) AV

AV Differential Amplifier (P3) AV

AV Digital Power 112.5 mW typ Standby Mode Clock Stopped 1.2 mW typ Clock Running 2.3 mW typ

1

See Terminology

= +5V 35 mA typ

DD4

= +5V 10 mA typ

DD4

= +5V, Both Modes 42 mA typ

DD3

Both Modes 45 mA typ

= +5V 30 nA typ

DD3

= +5V 30 nA typ

DD4

Clock Stopped 250 µA typ

= +3.3V 101 mW typ

DD4

= +5V 175 mW typ

DD4

= +3.3V 27 mW typ

DD4

= +5V 50 mW typ

DD4

= +3.3V 116 mW typ

DD3

= +5V 210 mW typ

DD3

Rev. PrN | Page 4 of 22

Preliminary Technical Data AD7760

TIMING SPECIFICATIONS

Tabl e 2. V

Parameter Limit at T

f

MCLK

80 MHz max f

ICLK

20 MHz max

1

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

t

14

t

15

t

16

t

17

t

18

1

t

= 1/f

ICLK

DD1

ICLK

= 2.5 V, V

= 5 V, V

DD2

MIN

= 4.096 V, V

REF

, T

Unit Description

MAX

= TBD V, TA = +25°C, C

DRIVE

= 25pF, Full Power Mode, unless otherwise noted

LOAD

12.288 MHz min Applied Master Clock Frequency

12.288 MHz min Internal Modulator Clock Derived from MCLK.

0.5 × t

ICLK

10 nS min

2 nS min

typ

DRDY Pulse Width

DRDY Falling Edge to CS falling Edge

RD/WR Setup Time to CS Falling Edge

10 nS typ Data Access Time t

ICLK

t

ICLK

2 nS min

min

CS Low Pulse Width

CS High Pulse Width Between Reads

RD/WR Hold Time to CS Rising Edge

10 nS max Bus Relinquish Time

0.5 × t

ICLK

typ

DRDY High Period

DRDY Low Period

15 nS typ Data Access Time TBD xS min

TBD xS min

Data Valid Prior to

Data Valid After

DRDY Rising Edge

10 nS max Bus Relinquish Time t

ICLK

t

ICLK

xS min

CS Low Pulse Width

CS High Period Between Address and Data

10 nS min Data Setup Time 10 nS min Data Hold Time

Rev. PrN | Page 5 of 22

AD7760 Preliminary Technical Data

TIMING DIAGRAMS

t

1

t

2

5

t

3

t

4

Figure 2. Parallel Interface Timing Diagram

t

12t13

11

t

9

10

Figure 3. 20MHz Modulator Data Output Mode

t

6

t

7

t

8

t

14

t

15

t

17

t

16

t

18

Figure 4. AD7760 Register Write

Rev. PrN | Page 6 of 22

Preliminary Technical Data AD7760

ABSOLUTE MAXIMUM RATINGS

Table 3. T

Parameters Rating

VDD to GND TBD V

to GND TBD

IN+

V

to GND TBD

IN–

Digital input voltage to GND TBD Digital output voltage to GND TBD V

to GND TBD

REF

Input current to any pin except supplies1TBD Operating temperature range

Commercial (A, B version) −40°C to +85°C Storage temperature range −65°C to +150°C Junction temperature 150°C TQFP Exposed Paddle Package θJA thermal impedance 92.7 °C/W θJC thermal impedance 5.1 °C/W CSP Package θJA thermal impedance 26.7 °C/W θJC thermal impedance 30 °C/W Lead temperature, soldering

Vapor phase (60 secs) 215°C

Infrared (15 secs) 220°C ESD TBD kV

1

Transient currents of up to TBD mA do not cause SCR latch-up.

= 25°C, unless otherwise noted.

A

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. PrN | Page 7 of 22

Analog Devices AD7760 prn Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

TABLE OF CONTENTS

AD7760—SPECIFICATIONS

TIMING SPECIFICATIONS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION