ANALOG DEVICES AD7760 Service Manual

2.5 MSPS, 24-Bit, 100 dB

V

VIN–

www.BDTIC.com/ADI

Sigma-Delta ADC with On-Chip Buffer

FEATURES

120 dB dynamic range at 78 kHz output data rate
100 dB dynamic range at 2.5 MHz output data rate
112 dB SNR at 78 kHz output data rate
100 dB SNR at 2.5 MHz output data rate

2.5 MHz maximum fully filtered output word rate
Programmable oversampling rate (8× to 256×)
Fully differential modulator input
On-chip differential amplifier for signal buffering
Low-pass finite impulse response (FIR) filter with default or

ogrammable coefficients

user-pr
Modulator output mode
Overrange alert bit
Digital offset and gain correction registers
Filter bypass modes
Low power and power-down modes
Synchronization of multiple devices via

APPLICATIONS

Data acquisition systems
Vibration analysis
Instrumentation

GENERAL DESCRIPTION

SYNC

pin

V

REF+

MCLK

SYNC

RESET

FUNCTIONAL BLOCK DIAGRAM

+

IN

MULTIBIT

Σ-Δ

MODULATO R

RECONSTRUCT ION

PROGRAMMABLE

DECIMATI ON

FIR FILTER

ENGINE

BUF

AD7760

CONTROL LOGIC

OFFSET AND GAIN

REGISTERS

DIFF

I/O

DB0 TO DB 15CS DRDYRD/WR

Figure 1.

AD7760

AVDD1

AVDD2

3

AV

DD

4

AV

DD

DECAPA/B

R

BIAS

AGND

V

DRIVE

DV

DD

DGND

4975-001

The AD7760 is a high performance, 24-bit Σ- analog-to-digital
converter (ADC). It combines wide input bandwidth and high
speed with the benefits of Σ- conversion to achieve a perfor­mance of 100 dB SNR at 2.5 MSPS, making it ideal for high
speed data acquisition. Wide dynamic range combined with
significantly reduced antialiasing requirements simplify the
design process. An integrated buffer to drive the reference, a
differential amplifier for signal buffering and level shifting, an
overrange flag, internal gain and offset registers, and a low-pass
digital FIR filter make the AD7760 a compact, highly integrated
data acquisition device requiring minimal peripheral component
selection. In addition, the device offers programmable decimation
rates, and the digital FIR filter can be adjusted if the default
characteristics are not appropriate for the application. The
AD7760 is ideal for applications demanding high SNR
without a complex front-end signal processing design.

The differential input is sampled at up to 40 MSPS by an analog

odulator. The modulator output is processed by a series of low-

m
pass filters, with the final filter having default or user-programmable

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

coefficients. The sample rate, filter corner frequencies, and output
w

ord rate are set by a combination of the external clock frequency

and the configuration registers of the AD7760.

The reference voltage supplied to the AD7760 determines the

alog input range. With a 4 V reference, the analog input range

an
is ±3.2 V differential biased around a common mode of 2 V.
This common-mode biasing can be achieved using the on-chip
differential amplifier, further reducing the external signal
conditioning requirements.

The AD7760 is available in an exposed paddle, 64-lead TQFP
a

nd is specified over the industrial temperature range from

−40°C to +85°C.

Table 1. Related Devices

Part No. Description

AD7762 24-bit, 625 kSPS, 109 dB, Σ-∆ parallel interface
AD7763 24-bit, 625 kSPS, 109 dB, Σ-∆ serial interface

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD7760

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TABLE OF CONTENTS

Features.............................................................................................. 1

Writing to the AD7760.............................................................. 23

Applications....................................................................................... 1

Functional Block Diagram ..............................................................1

General Description......................................................................... 1

Revision History ...............................................................................3

Specifications..................................................................................... 4

Timing Specifications ..................................................................6

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Terminology ....................................................................................11

Typical Performance Characteristics........................................... 12

Theory of Operation ......................................................................18

Modulator Data Output Mode...................................................... 19

Modulator Inputs........................................................................ 19

Clocking the AD7760 .................................................................... 24

Buffering the MCLK signal....................................................... 24

MCLK Jitter Requirements ....................................................... 24

Driving the AD7760....................................................................... 26

Using the AD7760...................................................................... 27

Decoupling and Layout Recommendations................................ 28

Supply Decoupling..................................................................... 29

Additional Decoupling.............................................................. 29

Reference Voltage Filtering .......................................................29

Differential Amplifier Components ........................................29

Bias Resistor Selection............................................................... 29

Layout Considerations............................................................... 29

Exposed Paddle........................................................................... 29

Programmable FIR Filter............................................................... 30

Downloading a User-Defined Filter ............................................ 31

Modulator Data Output Scaling............................................... 19

Modulator Data Output Mode Interface..................................... 20

Clock Divide-by-1 Mode (

Clock Divide-by-2 Mode (

Using the AD7760 in Modulator Output Mode..................... 21

AD7760 Interface............................................................................ 22

Reading Data............................................................................... 22

Reading Status and Other Registers......................................... 22

Sharing the Parallel Bus............................................................. 22

Synchronization.......................................................................... 22

CDIV

= 1) .....................................20

CDIV

= 0) .....................................20

Example Filter Download ......................................................... 31

AD7760 Registers........................................................................... 33

Control Register 1—Address 0x0001 ...................................... 33

Control Register 2—Address 0x0002 ...................................... 33

Status Register (Read Only)...................................................... 34

Offset Register—Address 0x0003............................................. 34

Gain Register—Address 0x0004............................................... 34

Overrange Register—Address 0x0005..................................... 34

Outline Dimensions....................................................................... 35

Ordering Guide .......................................................................... 35

Rev. A | Page 2 of 36

AD7760

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REVISION HISTORY

8/06—Rev. 0 to Rev. A

Updated Package Option................................................... Universal

Change to Features............................................................................1

Changes to Specifications.................................................................4

Changes to Absolute Maximum Ratings........................................8

Changes to Terminology Section ..................................................11

Added Figure 36 Through Figure 39............................................17

Added Modulator Data Output Mode Section ...........................19

Added Figure 41 Through Figure 47............................................19

Added Modulator Data Output Mode Interface Section...........20

Changes to Reading Data Section.................................................22

Added Synchronization Section....................................................22

Changes to Clocking the AD7760 Section...................................24

Added Buffering the MCLK Signal Section.................................24

A

dded MCLK Jitter Requirements Heading ...............................24

Changes to Driving the AD7760 Section.....................................26

Changes to Figure 51......................................................................26

Added Figure 52..............................................................................26

Changes to Figure 55......................................................................28

Changes to Figure 56......................................................................29

Added Exposed Paddle Section.....................................................29

Change to Control Register 2—Address 0x0002 Section ..........33

Changes to Status Register (Read Only) Section........................34

7/05—Revision 0: Initial Version

Rev. A | Page 3 of 36

AD7760

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SPECIFICATIONS

AVDD1 = DVDD = V
the on-chip amplifier with components as shown in Tabl e 8, unless otherwise noted.

Table 2.

Parameter Test Conditions/Comments Specification Unit

DYNAMIC PERFORMANCE

Decimate by 256 MCLK = 40 MHz, ODR = 78 kHz, fIN = 1 kHz

Dynamic Range Modulator inputs shorted 119 dB min

120.5 dB typ
Signal-to-Noise Ratio (SNR)
Input amplitude = −60 dBFS 59 dB typ
Spurious-Free Dynamic Range (SFDR) Nonharmonic, input amplitude = −6 dBFS 126 dBc typ
Input amplitude = −60 dBFS 77 dBc typ
Total Harmonic Distortion (THD) Input amplitude = −0.5 dBFS −105 dB typ
Input amplitude = −6 dBFS −106 dB typ
Input amplitude = −60 dBFS −75 dB typ

Decimate by 32 MCLK = 40 MHz, ODR = 625 kHz, fIN =100 kHz

Dynamic Range Modulator inputs shorted 108 dB min

109.5 dB typ
Signal-to-Noise Ratio (SNR)2 Input amplitude = −0.5 dBFS 107 dB typ
Spurious-Free Dynamic Range (SFDR) Nonharmonic, input amplitude = −6 dBFS 120 dBc typ
Total Harmonic Distortion (THD) Input amplitude = −0.5 dBFS −105 dB typ
Input amplitude = −6 dBFS −106 dB typ

Decimate by 8 MCLK = 40 MHz, ODR = 2.5 MHz

Dynamic Range Modulator inputs shorted 99 dB min

100.5 dB typ
Signal-to-Noise Ratio (SNR)2 f
f
f
Spurious-Free Dynamic Range (SFDR) Nonharmonic, fIN = 100 kHz, input amplitude = −6 dBFS 120 dBc typ
Nonharmonic, fIN = 1 MHz, input amplitude = −6 dBFS 114 dBc typ
Total Harmonic Distortion (THD) Input amplitude = −0.5 dBFS, fIN = 100 kHz −103 dB typ
Input amplitude = −6 dBFS, fIN = 100 kHz −102 dB typ
IMD Second Order fIN A = 989.95 kHz, fIN B = 999.95 kHz −115 dB typ
IMD Third Order fIN A = 989.95 kHz, fIN B = 999.95 kHz −89 dB typ

DC ACCURACY

Resolution 24 Bits
Differential Nonlinearity Guaranteed monotonic to 24 bits
Integral Nonlinearity 0.00076 % typ
Zero Error 0.014 % typ

0.02 % max
Gain Error 0.016 % typ
Zero Error Drift 0.00001 % FS/°C typ
Gain Error Drift 0.0002 % FS/°C typ

DIGITAL FILTER RESPONSE

Decimate by 8

Group Delay MCLK = 40 MHz 12 µs typ

Decimate by 32

Group Delay MCLK = 40 MHz 47 µs typ

Decimate by 256

Group Delay MCLK = 40 MHz 358 µs typ

= 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, V

DRIVE

2

Input amplitude = −0.5 dBFS 112 dB typ

= 1 kHz, input amplitude = −0.5 dBFS 100 dB typ

IN

= 100 kHz, input amplitude = −0.5 dBFS 99 dB typ

IN

= 1 MHz, input amplitude = −0.5 dBFS 98 dB typ

IN

= 4.096 V, MCLK amplitude = 5 V, TA = 25°C, normal mode, using

REF+

1

Rev. A | Page 4 of 36

AD7760

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Parameter Test Conditions/Comments Specification Unit

ANALOG INPUT

Differential Input Voltage VIN(+) – VIN(−), V
V

(+) – VIN(−), V

IN

Input Capacitance At internal buffer inputs 5 pF typ
At modulator inputs 55 pF typ
REFERENCE INPUT/OUTPUT

V

Input Voltage VDD3 = 3.3 V ± 5% +2.5 V max

REF

V

V

Input DC Leakage Current ±6 µA max

REF

V

Input Capacitance 5 pF max

REF

3 = 5 V ± 5% +4.096 V max

DD

POWER DISSIPATION

Total Power Dissipation Normal mode 958 mW max

Low power mode 661 mW max

Standby Mode Clock stopped 6.35 mW max
POWER REQUIREMENTS

AVDD1 (Modulator Supply) ±5% +2.5 V

AVDD2 (General Supply) ±5% +5 V

AVDD3 (Differential Amplifier Supply) +3.15/+5.25 V min/max

AVDD4 (Reference Buffer Supply) +3.15/+5.25 V min/max

DVDD ±5% +2.5 V

V

+1.65/+2.7 V min/max

DRIVE

Normal Mode

AIDD1 (Modulator) 49/51 mA typ/max
AIDD2 (General)

3

40/42 mA typ/max

AIDD4 (Reference Buffer) AVDD4 = 5 V 34/36 mA typ/max

Low Power Mode

AIDD1 (Modulator) 26/28 mA typ/max
AIDD2 (General)

3

20/23 mA typ/max
AIDD4 (Reference Buffer) AVDD4 = 5 V 9/10 mA typ/max
AIDD3 (Differential Amplifier) AVDD3 = 5 V, both modes 41/44 mA typ/max
DIDD Both modes 63/70 mA typ/max

DIGITAL I/O

MCLK Input Amplitude

4

5 V typ

Input Capacitance 7.3 pF typ
Input Leakage Current ±5 A max
Three-State Leakage Current (D15:D0) ±5 A max
V

0.7 × V

INH

V

0.3 × V

INL

5

V

OH

6

V

OH

4

V

0.1 V max

OL

1

See the Terminology section.

2

SNR specifications in decibels are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

3

Current scales with ICLK frequency. See the Typical Performance Characteristics section.

4

Although the AD7760 can function with an MCLK amplitude of less than 5 V, this is the recommended amplitude to achieve the performance as stated.

5

Tested using the minimum V

6

Tested using V

= 2.5 V with a 400 A load current.

DRIVE

voltage of 1.65 V with a 400 µA load current.

DRIVE

1.5 V min

2.4 V typ

= 2.5 V ±2 V p-p

REF

= 4.096 V ±3.25 V p-p

REF

V min

DRIVE

V max

DRIVE

Rev. A | Page 5 of 36

AD7760

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TIMING SPECIFICATIONS

AVDD1 = DVDD = V

Table 3.

Parameter Limit at T

f

1 MHz min Applied master clock frequency

MCLK

40 MHz max
f

500 kHz min Internal modulator clock derived from MCLK

ICLK

20 MHz max

1, 2

t

1

t2 10 ns min
t3 3 ns min
t4 (0.5 × t

t5 t
t6 t
t7 3 ns min
t8 11 ns max Bus relinquish time

2

t

0.5 × t

9

2

t

0.5 × t

10

t11 (0.5 × t

3, 4

t

12

3, 4

t

13

t14 11 ns max Bus relinquish time
t15 4 × t

t16 4 × t
t17 5 ns min Data setup time
t18 0 ns min Data hold time

4, 5

t

19

4, 5

t

20

1

t

= 1/f

ICLK

.

ICLK

2

When ICLK = MCLK,

3

Valid when using the modulator output mode with

4

See the Modulator Data Output Mode section for timing diagrams.

5

Valid when using the modulator output mode with

= 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted.

DRIVE

, T

MIN

0.5 × t

typ

ICLK

) + 16 ns max Data access time

ICLK

min

ICLK

min

ICLK

typ

ICLK

typ

ICLK

) + 16 ns max Data access time

ICLK

23 ns min
19 ns min

min

ICLK

min

ICLK

23 ns min
19 ns min

DRDY

pulse width depends on the mark-space ratio of applied MCLK.

Unit Description

MAX

DRDY
DRDY

/WR setup time to CS falling edge

RD

low read pulse width

CS

high pulse width between reads

CS

/WR hold time to CS rising edge

RD

DRDY
DRDY

Data valid prior to DRDY
Data valid after DRDY

low write pulse width

CS

high period between address and data

CS

Data valid prior to MCLK falling edge while DRDY
Data valid after MCLK falling edge while DRDY

CDIV

= 1.

CDIV

= 0.

pulse width
falling edge to CS falling edge

high period
low period

rising edge

rising edge

is logic low

is logic low

Rev. A | Page 6 of 36

AD7760

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TIMING DIAGRAMS

DRDY

t

1

t

5

t

6

CS

RD/WR

D[0:15]

t

2

t

3

t

4

DATA MSW LSW + STATUS

Figure 2. Filtered Output—Para

llel Interface Timing Diagram

t

7

t

8

04975-002

CS

RD/WR

D[0:15]

t

15

t

17

REGISTER ADDRESS REGISTER DAT A

t

16

t

18

04975-004

Figure 3. AD7760 Register Write

Rev. A | Page 7 of 36

AD7760

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameters Rating

AV

1 to GND −0.3 V to +3 V

DD

AVDD2:AV
DV
V

DRIVE

VIN+, VIN– to GND
VINA+, VINA− to GND

4 to GND −0.3 V to +6 V

DD

to GND −0.3 V to +3 V

DD

to GND −0.3 V to +3 V

1

−0.3 V to +6 V

1

−0.3 V to +6 V

Digital Input Voltage to GND2 −0.3 V to DVDD + 0.3 V
MCLK to MCLKGND −0.3 V to +6 V

to GND

3

−0.3 V to AVDD4 + 0.3 V

V

REF+

AGND to DGND −0.3 V to +0.3 V

Input Current to Any Pin Except

Supplies

4

Operating Temperature Range

±10 mA

Commercial −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TQFP Exposed Paddle Package

θ

Thermal Impedance 92.7°C/W

JA

θ

Thermal Impedance 5.1°C/W

JC

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C
ESD 600 V

1

Absolute maximum voltage for VIN−, VIN+ and V

whichever is lower.

2

Absolute maximum voltage on digital inputs is 3.0 V or DVDD + 0.3 V,

whichever is lower.

3

Absolute maximum voltage on V

whichever is lower.

4

Transient currents of up to 200 mA do not cause SCR latch-up.

input is 6.0 V or AVDD4 + 0.3 V,

REF+

−, V

+ is 6.0 V or AVDD3 + 0.3 V,

INA

INA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 8 of 36

AD7760

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DRIVE

DGND63V

DGND61DB060DB159DB258DB357DB456DB555DB654DB753DGND52DB851DB950DB1049DB11

64

62

1

DGND

MCLKGND

MCLK

AVDD2

AGND2

AVDD1

AGND1

DECAPA

REFGND

V

REF+

AGND4

AVDD4

AGND2

AVDD2

AVDD2

AGND2

PIN 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

A+

BIAS

IN

R

V

AGND2

Figure 4. 64-Lead TQFP Pin

21

A–

IN

V

AD7760

TOP VIEW

(Not to Scale)

22

23

A–

A+

OUT

OUT

V

V

24

25

26

27

28

3

–

+

IN

IN

DD

V

V

AV

AGND3

2

AV

30

DD

AGND229AGND3

Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

6, 33 AVDD1

2.5 V Power Supply for Modulator. These pins should be decoupled t
with 100 nF and 10 µF capacitors on each pin. See the Decoupling and Layout Recommendations section
fo

r details.

4, 14, 15, 27 AVDD2

5 V Power Supply. These pins should be decoupled to A
on each of Pin 4, Pin 14, and Pin 15). Pin 27 should be connected to Pin 14 via a 15 nH inductor. See the
Decoupling and Layout Recommendations section for details.

24 AVDD3

3.3 V to 5 V Power Supply for Differential Amplifier. This pin shou
100 nF capacitor. See the Decoupling and Layout Recommendations section for details.

12 AVDD4

3.3 V to 5 V Power Supply for Reference Buffer. This pin s

in series with a 10 Ω resistor.
7, 34 AGND1 Power Supply Ground for Analog Circuitry Powered by AVDD1.
5, 13, 16, 18, 28 AGND2 Power Supply Ground for Analog Circuitry Powered by AVDD2.
23, 29, 31, 32 AGND3 Power Supply Ground for Analog Circuitry Powered by AVDD3.
11 AGND4 Power Supply Ground for Analog Circuitry Powered by AVDD4.
9 REFGND Reference Ground. Ground connection for the reference voltage.
41 DVDD

2.5 V Power Supply for Digital Circuitry and FIR Filter.

capacitor.
44, 63 V

DRIVE

Logic Power Supply Input, 1.8 V to 2.5 V. The voltage supplied at these pins determines the operating

oltage of the logic interface. Both of these pins must be connected together and tied to the same supply.

v

Each pin should also be decoupled to DGND with a 100 nF capacitor.
1, 35, 42, 43,

DGND Ground Reference for Digital Circuitry.

53, 62, 64
19 VINA+ Positive Input to Differential Amplifier.
20 VINA− Negative Input to Differential Amplifier.
21 V
22 V

A− Negative Output from Differential Amplifier.

OUT

A+ Positive Output from Differential Amplifier.

OUT

25 VIN+ Positive Input to the Modulator.
26 VIN− Negative Input to the Modulator.
10 V

REF+

Reference Input. The input range of this pin is determined by the reference buffer supply voltage (AV

See the Reference Voltage Filtering section for more details.
8 DECAPA Decoupling Pin. A 100 nF capacitor must be inserted between this pin and AGND.

48

DB12

47

DB13

46

DB14

45

DB15

44

V

DRIVE

43

DGND

42

DGND

41

DV

DD

40

CS

39

RD/WR

38

DRDY

37

RESET

36

SYNC

35

DGND

34

AGND1

33

AVDD1

31

AGND332AGND3

DECAPB

4975-005

o AGND1 (Pin 7 and Pin 34, respectively)

GND2 (Pin 5 and Pin 13, with 100 nF capacitors

ld be decoupled to AGND3 (Pin 23) with a

hould be decoupled to Pin 9 with a 10 nF capacitor

This pin should be decoupled to DGND with a 100 nF

4).

DD

Rev. A | Page 9 of 36

AD7760

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Pin No. Mnemonic Description

30 DECAPB Decoupling Pin. A 33 pF capacitor must be inserted between this pin and AGND3.
17 R

45 to 52,
54 to 61

37

3 MCLK

2 MCLKGND Master Clock Ground Sensing Pin.
36

39

38

40

BIAS

DB15:DB8,
DB7:DB0

RESET

SYNC

/WR Read/Write Input. This pin, in conjunction with the chip select pin, is used to read and write data to and

RD

DRDY

CS

Bias Current Setting Pin. A resistor must be inserted bet
Bias Resistor Selection section.

16-Bit Bidirectional Data Bus. These are three-state pins that are controlled by the CS pin and the RD/WR
pin. The operating voltage for these pins is determined by the V
Output Mode and AD7760 Interface sections for more details.

A falling edge on this pin resets all internal digital circuitry and powers down the part. Holding this pin low
keeps the AD7760 in a reset state.

Master Clock Input. A low jitter, buffered digital clock must be applied t
depends on the frequency of this clock. See the Clocking the AD7760 section for more details.

Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize
multiple devices in a system. See the Synchronization section for more details.

from the AD7760. If this pin is low when CS is low, a read takes place. If this pin is high when CS is low, a
write occurs. See the Modulator Data Output Mode and AD7760 Interface sections for more details.

Data Ready Output. Each time new conversion data is available, an active low pulse, ½ ICLK period wide, is
produced on this pin. See the Modulator Data Output Mode and AD7760 Interface sections for more details.

Chip Select Input. Used in conjunction with the RD/WR pin to read and write data from and to the AD7760.
See the Modulator Data Output Mode and AD7760 Interface sections for more details.

ween this pin and AGND. For more details, see the

voltage. See the Modulator Data

DRIVE

o this pin. The output data rate

Rev. A | Page 10 of 36

AD7760

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TERMINOLOGY

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the

ms sum of all other spectral components below the Nyquist

r
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of harmonics to the fundamental.

or the AD7760, it is defined as

F

22222

++++

VVVVV

54

()

THD

where:

V

is the rms amplitude of the fundamental.

1

, V3, V4, V5, and V6 are the rms amplitudes of the second to

V

2

the sixth harmonics.

log20dB

=

32

V

1

6

Integral Nonlinearity (INL)

INL is the maximum deviation from a straight line passing

rough the endpoints of the ADC transfer function.

th

Differential Nonlinearity (DNL)

DNL is the difference between the measured and the ideal

B change between any two adjacent codes in the ADC.

1 LS

Zero Error

Zero error is the difference between the ideal midscale input
voltage (w
voltage producing the midscale output code.

Zero Error Drift

Zero error drift is the change in the actual zero error value due

o a temperature change of 1°C. It is expressed as a percentage

t
of full scale at room temperature.

hen both inputs are shorted together) and the actual

Nonharmonic Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of the rms signal amplitude to the rms value

f the peak spurious spectral component, excluding harmonics.

o

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to

he rms noise measured with the inputs shorted together. The

t
value for the dynamic range is expressed in decibels.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb

, any active device with nonlinearities creates distortion products
at sum and difference frequencies of mfa ± nfb, where m, n = 0,
1, 2, 3, and so on. Intermodulation distortion terms are those
for which neither m nor n are equal to 0. For example, the second­order terms include (fa + fb) and (fa − fb), and the third-order
terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

The AD7760 is tested using the CCIF standard, where two input

requencies near the top end of the input bandwidth are used.

f
In this case, the second-order terms are usually distanced in

f

requency from the original sine waves, and the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification, where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in decibels.

Gain Error

The first transition (from 100 … 000 to 100 … 001) should
occur for an an
full scale. The last transition (from 011 … 110 to 011 … 111)
should occur for an analog voltage 1½ LSB below the nominal
full scale. The gain error is the deviation of the difference
between the actual level of the last transition and the actual
level of the first transition, from the difference between the
ideal levels.

Gain Error Drift

Gain error drift is the change in the actual gain error value due

o a temperature change of 1°C. It is expressed as a percentage

t
of full scale at room temperature.

alog voltage ½ LSB above the nominal negative

Rev. A | Page 11 of 36