Analog Devices AD774B, AD674B Datasheet

Complete

a

FEATURES
Complete Monolithic 12-Bit A/D Converters with

Reference, Clock, and Three-State Output Buffers
Industry Standard Pinout
High Speed Upgrades for AD574A
8- and 16-Bit Microprocessor Interface
8 ms (max) Conversion Time (AD774B)
15 ms (max) Conversion Time (AD674B)
65 V, 610 V, 0-10 V, 0-20 V Input Ranges
Commercial, Industrial and Military Temperature

Range Grades
MIL-STD-883 Compliant Versions Available

PRODUCT DESCRIPTION

The AD674B and AD774B are complete 12-bit successive­approximation analog-to-digital converters with three-state
output buffer circuitry for direct interface to 8- and 16-bit
microprocessor busses. A high precision voltage reference and
clock are included on chip, and the circuit requires only power
supplies and control signals for operation.

The AD674B and AD774B are pin compatible with the industry
standard AD574A, but offer faster conversion time and bus­access speed than the AD574A and lower power consumption.
The AD674B converts in 15 µs (maximum) and the AD774B
converts in 8 µs (maximum).

The monolithic design is implemented using Analog Devices’
BiMOS II process allowing high performance bipolar analog cir­cuitry to be combined on the same die with digital CMOS logic.
Offset, linearity and scaling errors are minimized by active laser­trimming of thin-film resistors.

Five different grades are available. The J and K grades are speci­fied for operation over the 0°C to +70°C temperature range.
The A and B grades are specified from –40°C to +85°C, the T
grade is specified from –55°C to +125°C. The J and K grades
are available in a 28-pin plastic DIP or 28-lead SOIC. All other
grades are available in a 28-pin hermetically sealed ceramic
DIP.

12-Bit A/D Converters

AD674B*/AD774B*

FUNCTIONAL BLOCK DIAGRAM

+5V SUPPLY

DATA MODE SELECT

CHIP SELECT

BYTE ADDRESS/

SHORT CYCLE

READ/ CONVERT

CHIP ENABLE

+12/+15V SUPPLY

+10V REFERENCE

ANALOG COMMON

REFERENCE INPUT

_

_

12/ 15V SUPPLY

BIPOLAR OFFSET

10V SPAN INPUT

20V SPAN INPUT

V

LOGIC

V

REF OUT

REF IN

BIPOFF

10V

20V

1

2

12/8

3

CS

4

A

0

5

R/C

6

CE

7

CC

8
9

AC

10

11

V

EE

12

13

IN

14

IN

19.95k

10V
REF

VOLTAGE

DIVIDER

CONTROL

CLOCK

DAC

REF

I

SAR

COMP

I DAC

N

12

AD674B/AD774B

MSB

3
S

T
A
T
E

12

O
U
T
P

12

U
T

B
U
F
F
E
R
S

V

EE

LSB

PRODUCT HIGHLIGHTS

1. Industry Standard Pinout: The AD674B and AD774B utilize
the pinout established by the industry standard AD574A.

2. Analog Operation: The precision, laser-trimmed scaling and
bipolar offset resistors provide four calibrated ranges: 0 to
+10 V and 0 to +20 V unipolar; –5 V to +5 V and –10 V to
+10 V bipolar. The AD674B and AD774B operate on +5 V
and ±12 V or ±15 V power supplies.

3. Flexible Digital Interface: On-chip multiple-mode three-state
output buffers and interface logic allow direct connection to
most microprocessors. The 12 bits of output data can be
read either as one 12-bit word or as two 8-bit bytes (one with
8 data bits, the other with 4 data bits and 4 trailing zeros).

4. The internal reference is trimmed to 10.00 volts with 1%
maximum error and 10 ppm/°C typical temperature coeffi­cient. The reference is available externally and can drive up
to 2.0 mA beyond the requirements of the converter and bi­polar offset resistors.

5. The AD674B and AD774B are available in versions compli­ant with MIL-STD-883. Refer to the Analog Devices Mili­tary Products Databook or current AD674B/AD774B/883B
data sheet for detailed specifications.

N
Y
B
B
L
E

A

N
Y
B
B
L
E

B

N
Y
B
B
L
E

C

STATUS

28

STS

DB11 (MSB)

27

DB10

26

DB9

25

DB8

24

DB7

23

22

DB6

DB5

21

DB4

20

DB3

19

DB2

18

DB1

17

DB0 (LSB)

16

DIGITAL COMMON DC

15

DIGITAL
DATA
OUTPUTS

*Protected by U.S. Patent Nos. 4,250,445; 4,808,908; RE30586.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

AD674B/AD774B—SPECIFICATIONS

(T
V

= +5 V 6 10%, VEE = –15 V 6 10% or –12 V 6 5% unless otherwise noted)

LOGIC

MIN

to T

with VCC = +15 V 6 10% or +12 V 6 5%,

MAX

J Grade K Grade

Model (AD674B or AD774B) Min Typ Max Min Typ Max

RESOLUTION 12 12
LINEARITY ERROR @ +25°C 61 61/2

T

MIN

to T

MAX

61 61/2

DIFFERENTIAL LINEARITY ERROR

(Minimum Resolution for Which No
Missing Codes are Guaranteed) 12 12

UNIPOLAR OFFSET

BIPOLAR OFFSET

FULL-SCALE CALIBRATION ERROR

1

@ +25°C 62 62

1

@ +25°C 66 63

1, 2

@ +25°C

(with Fixed 50 Ω Resistor from REF OUT to REF IN) 0.1 0.25 0.1 0.125

TEMPERATURE RANGE 0 +70 0 +70

TEMPERATURE DRIFT

3

(Using Internal Reference)

Unipolar 62 61
Bipolar Offset 62 61
Full-Scale Calibration 66 62

POWER SUPPLY REJECTION

Max Change in Full-Scale Calibration

V

= 15 V ± 1.5 V or 12 V ± 0.6 V 62 61

CC

= 5 V ± 0.5 V 61/2 61/2

V

LOGIC

V

= –15 V ± 1.5 V or –12 V ± 0.6 V 62 61

EE

ANALOG INPUT

Input Ranges

Bipolar –5 +5 –5 +5

–10 +10 –10 +10

Unipolar 0 +10 0 +10

0 +20 0 +20

Input Impedance

10 Volt Span 3 5 7357
20 Volt Span 6 10 14 6 10 14

POWER SUPPLIES

Operating Range

V

LOGIC

V

CC

V

EE

+4.5 +5.5 +4.5 +5.5
+11.4 +16.5 +11.4 +16.5
–16.5 –11.4 –16.5 –11.4

Operating Current

I

LOGIC

I

CC

I

EE

3.5 7 3.5 7

3.5 7 3.5 7
10 14 10 14

POWER CONSUMPTION 220 375 220 375

175 175

INTERNAL REFERENCE VOLTAGE 9.9 10.0 10.1 9.9 10.0 10.1

Output Current (Available for External Loads) 2.0 2.0
(External Load Should Not Change During the Conversion)

NOTES

1

Adjustable to zero.

2

Includes internal voltage reference error.

3

Maximum change from +25°C value to the value at T

4

Tested with REF OUT tied to REF IN through 50 Ω resistor, VCC = +16.5 V, VEE = –16.5 V, V

5

Tested with REF OUT tied to REF IN through 50 Ω resistor, VCC = +12 V, VEE = –12 V, V

Specifications subject to change without notice.

Specifications shown in boldface are tested on all devices at final electrical test at T
quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.

MIN

or T

MAX

.

, +25°C, and T

MIN

–2–

= +5.5 V, and outputs in high-Z mode.

LOGIC

= +5 V, and outputs in high-Z mode.

LOGIC

, and results from those tests are used to calculate outgoing

MAX

REV. B

AD674B/AD774B

A Grade B Grade T Grade

Min Typ Max Min Typ Max Min Typ Max Units

12 12 12 Bits

61 61/2 61/2 LSB
61 61/2 61 LSB

12 12 12 Bits

62 62 62 LSB

66 63 63 LSB

0.1 0.25 0.1 0.125 0.1 0.125 % of FS

–40 +85 –40 +85 –55 +125 °C

62 61 61 LSB
62 61 62 LSB
68 65 67 LSB

62 61 61 LSB
61/2 61/2 61/2 LSB
62 61 61 LSB

–5 +5 –5 +5 –5 +5 Volts
–10 +10 –10 +10 –10 +10 Volts
0 +10 0 +10 0 +10 Volts
0 +20 0 +20 0 +20 Volts

3 5 7357357kΩ
6 10 14 6 10 14 6 10 14 kΩ

+4.5 +5.5 +4.5 +5.5 +4.5 +5.5 Volts
+11.4 +16.5 +11.4 +16.5 +11.4 +16.5 Volts
–16.5 –11.4 –16.5 –11.4 –16.5 –11.4 Volts

3.5 7 3.5 7 3.5 7 mA

3.5 7 3.5 7 3.5 7 mA
10 14 10 14 10 14 mA

220 375 220 375 220 375 mW
175 175 175 mW

9.9 10.0 10.1 9.9 10.0 10.1 9.9 10.0 10.1 Volts

2.0 2.0 2.0 mA

4
5

REV. B

–3–

AD674B/AD774B

3k

100pF

+5V

3k

100pF

DB

N

DB

N

10pF

10pF

3k

+5V

3k

DB

N

DB

N

(for all grades T

DIGITAL SPECIFICATIONS

VEE = –15 V 6 10% or –12 V 6 5%)

Parameter Test Conditions Min Max Units

LOGIC INPUTS
V

IH

V

IL

I

IH

I

IL

C

IN

High Level Input Voltage +2.0 V
Low Level Input Voltage –0.5 +0.8 V
High Level Input Current VIN = V
Low Level Input Current V
Input Capacitance 10 pF

LOGIC OUTPUTS
V

OH

V

OL

I

OZ

C

OZ

High Level Output Voltage IOH = 0.5 mA +2.4 V
Low Level Output Voltage IOL = 1.6 mA +0.4 V
High-Z Leakage Current VIN = 0 to V
High-Z Output Capacitance 10 pF

(for all grades T

SWITCHING SPECIFICATIONS

V

LOGIC

to T

MIN

IN

with VCC = +15 V 6 10% or +12 V 6 5%, V

MAX

LOGIC

–10 +10 µA

= 0 V –10 +10 µA

–10 +10 µA

MIN

LOGIC

to T

with VCC = +15 V 6 10% or +12 V 6 5%,

MAX

= +5 V 6 10%,

LOGIC

+0.5 V V

LOGIC

= +5 V 6 10%, VEE = –15 V 6 10% or –12 V 6 5%; unless otherwise noted)

CONVERTER START TIMING (Figure 1)

J, K, A, B Grades T Grade

Parameter Symbol Min Typ Max Min Typ Max Units

Conversion Time

8-Bit Cycle (AD674B) t
12-Bit Cycle (AD674B) t
8-Bit Cycle (AD774B) t

12-Bit Cycle (AD774B) t
STS Delay from CE t
CE Pulse Width t

CS to CE Setup t
CS Low During CE High t

R/C to CE Setup t
R/C LOW During CE High t
A0 to CE Setup t
A

Valid During CE High t

0

C
C
C
C
DSC
HEC
SSC
HSC
SRC

HRC

SAC

HAC

6810 6810 µs
91215 91215 µs
456 456 µs
6 7.3 8 6 7.3 8 µs

200 225 ns
50 50 ns
50 50 ns
50 50 ns
50 50 ns
50 50 ns
00ns
50 50 ns

READ TIMING—FULL CONTROL MODE (Figure 2)

J, K, A, B Grades T Grade

Parameter Symbol Min Typ Max Min Typ Max Units

Access Time

CL = 100 pF t

Data Valid After CE Low t

Output Float Delay t
CS to CE Setup t
R/C to CE Setup t
A

to CE Setup t

0

CS Valid After CE Low t
R/C High After CE Low t
A

Valid After CE Low t

0

NOTES

1

tDD is measured with the load circuit of Figure 3a and is defined as the time required

for an output to cross 0.4 V or 2.4 V.

2

0°C to T

3

At –40°C.

4

At –55°C.

5

tHL is defined as the time required for the data lines to change 0.5 V when loaded with

MAX

.

the circuit of Figure 3b.
Specifications shown in boldface are tested on all devices at final electrical test with

worst case supply voltages at T
to calculate outgoing quality levels. All min and max specifications are guaranteed, al­though only those shown in boldface are tested.
Specifications subject to change without notice.

DD
HD

HL
SSR
SRR
SAR
HSR
HRR
HAR

MIN

1

5

75 150 75 150 ns
25
20

2
3

25
15

2
4

150 150 ns
50 50 ns
00ns
50 50 ns
00ns
00ns
50 50 ns

, +25°C, and T

. Results from those tests are used

MAX

t

t

SRC

t

HSC

t

HRC

t

HEC

t

HAC

C

DSC

HIGH IMPEDANCE

t

CE

__

CS

R/C

A

STS

DB11 – DB0

t

SSC

_

t

SAC

0

Figure 1. Convert Start Timing

CE
CS

_

R/C

A

0

STS

ns

DB11 – DB0

ns

t

SSR

t

SRR

HIGH

IMPEDANCE

t

HSR

t

HRR

t

DATA
VALID

HAR

t

HD

HIGH

IMP.

t

HL

t

SAR

t

DD

Figure 2. Read Cycle Timing

High-Z to Logic 1 High-Z to Logic 0

Figure 3a. Load Circuit for Access Time Test

Logic 1 to High-Z Logic 0 to High-Z

Figure 3b. Load Circuit for Output Float Delay Test

REV. B–4–