ANALOG DEVICES AD7747 Service Manual

24-Bit Capacitance-to-Digital Converter

FEATURES

Capacitance-to-digital converter

New standard in single chip solutions Interfaces to single or differential grounded sensors Resolution down to 20 aF (that is, up to 19.5-bit ENOB) Accuracy: 10 fF Linearity: 0.01% Common-mode (not changing) capacitance up to 17 pF Full-scale (changing) capacitance range ±8 pF Update rate: 5 Hz to 45 Hz Simultaneous 50 Hz and 60 Hz rejection at 8.1 Hz update Active shield for shielding sensor connection

Temperature sensor on-chip

Resolution: 0.1°C, accuracy: ±2°C Voltage input channel Internal clock oscillator 2-wire serial interface (I Power

2.7 V to 5.25 V single-supply operation

0.7 mA current consumption Operating temperature: −40°C to +125°C 16-lead TSSOP package

APPLICATIONS

Automotive, industrial, and medical systems for

Pressure measurement Position sensing Proximity sensing Level sensing Flow metering Impurity detection

C® compatible)

with Temperature Sensor

AD7747

GENERAL DESCRIPTION

The AD7747 is a high-resolution, Σ- capacitance-to-digital converter (CDC). The capacitance to be measured is connected directly to the device inputs. The architecture features inherent high resolution (24-bit no missing codes, up to 19.5-bit effective resolution), high linearity (±0.01%), and high accuracy (±10 fF factory calibrated). The AD7747 capacitance input range is ±8 pF (changing), and it can accept up to 17 pF common-mode capacitance (not changing), which can be balanced by a programmable on-chip digital-to-capacitance converter (CAPDAC).

The AD7747 is designed for single-ended or differential capacitive sensors with one plate connected to ground. For floating (not grounded) capacitive sensors, the AD7745 or

AD7746 are recommended.

The part has an on-chip temperature sensor with a resolution of

0.1°C and accuracy of ±2°C. The on-chip voltage reference and the on-chip clock generator eliminate the need for any external components in capacitive sensor applications. The part has a standard voltage input that, together with the differential reference input, allows easy interface to an external temperature sensor, such as an RTD, thermistor, or diode.

The AD7747 has a 2-wire, I part can operate with a single power supply of 2.7 V to 5.25 V. It is specified over the automotive temperature range of

−40°C to +125°C and is housed in a 16-lead TSSOP package.

C-compatible serial interface. The

FUNCTIONAL BLOCK DIAGRAM

TEMP

SENSOR

VIN(+)

VIN(–)

CIN1(+)

CIN1(–)

SHLD

EXCITATION

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

MUX

CAP DAC 1

CAP DAC 2

CLOCK

GENERATOR

24-BIT Σ-Δ

GENERATOR

REFIN( +) REFIN( –)

Figure 1.

AD7747

DIGITAL

FILTER

CONTROL LOG IC

CALIBRATION

VOLTAGE

REFERENCE

GND

I2C

SERIAL

INTERFACE

SDA

SCL

RDY

05469-001

AD7747

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Output Noise and Resolution Specifications ..............................11

Serial Interface ................................................................................ 12

Read Operation........................................................................... 12

Write Operation.......................................................................... 12

AD7747 Reset.............................................................................. 13

General Call................................................................................. 13

Status Register............................................................................. 15

Cap Data Register....................................................................... 15

VT Data Register ........................................................................15

Cap Setup Register ..................................................................... 16

VT Setup Register....................................................................... 16

EXC Setup Register ....................................................................17

Configuration Register .............................................................. 18

Cap DAC A Register .................................................................. 19

Cap DAC B Register................................................................... 19

Cap Offset Calibration Register ............................................... 20

Cap Gain Calibration Register.................................................. 20

Volt Gain Calibration Register ................................................. 20

Circuit Description......................................................................... 21

Overview ..................................................................................... 21

Capacitance-to-Digital Converter............................................ 21

Active AC Shield Concept......................................................... 21

CAPDAC..................................................................................... 21

Single-Ended Capacitive Configuration ................................. 22

Differential Capacitive Configuration..................................... 22

Parasitic Capacitance................................................................. 23

Parasitic Resistance.................................................................... 23

Parasitic Serial Resistance ......................................................... 23

Capacitive Gain Calibration ..................................................... 23

Capacitive System Offset Calibration...................................... 24

Internal Temperature Sensor .................................................... 24

External Temperature Sensor ................................................... 24

Voltage Input............................................................................... 25

Monitor................................................................................ 25

Typical Application Diagram.................................................... 26

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 27

REVISION HISTORY

1/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

AD7747

SPECIFICATIONS

VDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; GND = 0 V; EXC = ±V

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

CAPACITIVE INPUT

Conversion Input Range ±8.192 pF1 Factory calibrated Integral Nonlinearity (INL)2 ±0.01 % of FSR1 No Missing Codes2 24 Bit Conversion time ≥ 124 ms Resolution, p-p 16.5 Bit Conversion time 124 ms, see Table 5 Resolution Effective 19.1 Bit Conversion time 124 ms, see Table 5 Output Noise, rms 11.0

Absolute Error3 ±10 fF1 25°C, VDD = 5 V, after offset calibration Offset Error

4, 5

32 aF1

System Offset Calibration Range5 ±1 pF Offset Deviation over Temperature2 0.4 fF See Figure 6 Gain Error6 0.02 0.11 % of FS1 25°C, VDD = 5 V Gain Drift vs. Temperature2 −23 −26 −29 ppm of FS/°C Power Supply Rejection2 0.5 4 fF/V Normal Mode Rejection5 72 dB 50 Hz ± 1%, conversion time 124 ms 60 dB 60 Hz ± 1%, conversion time 124 ms

CAPDAC

Full Range 17 21 pF 6-bit CAPDAC Differential Nonlinearity (DNL) 0.3 LSB See Figure 16 Drift vs. Temperature2 26 ppm of FS/°C

EXCITATION

Frequency 16 kHz AC Voltage Across Capacitance ±VDD × 3/8 V To be configured via digital interface Average DC Voltage Across Capacitance VDD/2 V

TEMPERATURE SENSOR7 V

Resolution 0.1 °C Error2 ±0.5 ±2 °C Internal temperature sensor ±2 °C External sensing diode8

VOLTAGE INPUT7 V

Differential VIN Voltage Range ±V Absolute VIN Voltage2 GND − 0.03 VDD + 0.03 V Integral Nonlinearity (INL) ±3 ±15 ppm of FS No Missing Codes2 24 Bit Conversion time = 122.1 ms Resolution, p-p 16 Bits

Output Noise 3 μV rms

Offset Error ±3 μV Offset Drift vs. Temperature 15 nV/°C Full-Scale Error

2, 9

0.025 0.1 % of FS

Full-Scale Drift vs. Temperature 5 ppm of FS/°C Internal reference

0.5 ppm of FS/°C External reference Average VIN Input Current 300 nA/V Analog VIN Input Current Drift ±50 pA/V/°C Power Supply Rejection 80 dB Internal reference, VIN = V 90 dB External reference, VIN = V

× 3/8; −40°C to +125°C, unless otherwise noted.

aF/√Hz

Conversion time 124 ms, see Table 5

After system offset calibration, excluding effect of noise

REF

Conversion time = 62 ms, see Table 6 and Table 7

internal

internal or V

= 2.5 V

REF

Rev. 0 | Page 3 of 28

AD7747

Parameter Min Typ Max Unit Test Conditions/Comments

Normal Mode Rejection5 75 dB 50 Hz ± 1%, conversion time = 122.1 ms

50 dB 60 Hz ± 1%, conversion time = 122.1 ms

Common-Mode Rejection2 95 dB VIN = 1 V INTERNAL VOLTAGE REFERENCE

Voltage 1.169 1.17 1.171 V TA = 25°C

Drift vs. Temperature 5 ppm/°C EXTERNAL VOLTAGE REFERENCE INPUT

Differential REFIN Voltage2 0.1 2.5 VDD V

Absolute REFIN Voltage2 GND − 0.03 VDD + 0.03 V

Average REFIN Input Current 400 nA/V

Average REFIN Input Current Drift ±50 pA/V/°C

Common-Mode Rejection 80 dB SERIAL INTERFACE LOGIC INPUTS (SCL, SDA)

VIH Input High Voltage 2.1 V

VIL Input Low Voltage 0.8 V

Hysteresis 150 mV

Input Leakage Current (SCL) ±0.1 ±1 μA OPEN-DRAIN OUTPUT (SDA)

VOL Output Low Voltage 0.4 V I

IOH Output High Leakage Current 0.1 1 μA V

LOGIC OUTPUT (

RDY

) VOL Output Low Voltage 0.4 V I VOH Output High Voltage 4.0 V I VOL Output Low Voltage 0.4 V I VOH Output High Voltage VDD − 0.6 V I

POWER REQUIREMENTS

VDD-to-GND Voltage 4.75 5.25 V VDD = 5 V, nominal

2.7 3.6 V VDD = 3.3 V, nominal IDD Current 850 μA Digital inputs equal to VDD or GND 750 μA VDD = 5 V 700 μA VDD = 3.3 V IDD Current Power-Down Mode 0.5 2 μA Digital inputs equal to VDD or GND

Capacitance units: 1 pF = 10

Specification is not production tested, but is supported by characterization data at initial product release.

Factory calibrated. The absolute error includes factory gain calibration error, integral nonlinearity error, and offset error after system offset calibration, all at 25°C.

At different temperatures, compensation for gain drift over temperature is required.

The capacitive input offset can be eliminated using a system offset calibration. The accuracy of the system offset calibration is limited by the offset calibration register

LSB size (32 aF) or by converter + system p-p noise during the system capacitive offset calibration, whichever is greater. To minimize the effect of the converter + system noise, longer conversion times should be used for system capacitive offset calibration. The system capacitance offset calibration range is ±1 pF; the larger offset can be removed using CAPDACs.

Specification is not production tested, but guaranteed by design.

The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required.

The VTCHOP bit in the VT SETUP register must be set to 1 for the specified temperature sensor and voltage input performance.

Using an external temperature sensing diode 2N3906, with nonideality factor nf = 1.008, connected as in Figure 37, with total serial resistance <100 Ω.

Full-scale error applies to both positive and negative full scale.

−12

F; 1 fF = 10

−15

F; 1 aF = 10

−18

F. Full scale (FS) = 8.192 pF; full-scale range (FSR) = ±8.192 pF.

= −6.0 mA

SINK

= VDD

OUT

= 1.6 mA, VDD = 5 V

SINK

= 200 μA, VDD = 5 V

SOURCE

= 100 μA, VDD = 3 V

SINK

= 100 μA, VDD = 3 V

SOURCE

Rev. 0 | Page 4 of 28

AD7747

TIMING SPECIFICATIONS

VDD = 2.7 V to 3.6 V, or 4.75 V to 5.25 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; −40°C to +125°C, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

SERIAL INTERFACE

SCL Frequency 0 400 kHz SCL High Pulse Width, t SCL Low Pulse Width, t SCL, SDA Rise Time, tR 0.3 μs SCL, SDA Fall Time, t Hold Time (Start Condition), t Setup Time (Start Condition), t Data Setup Time, t Setup Time (Stop Condition), t Data Hold Time, t Bus-Free Time (Between Stop and Start Condition, t

Sample tested during initial release to ensure compliance.

All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.

Output load = 10 pF.

1, 2

See Figure 2

0.6 μs

HIGH

1.3 μs

LOW

0.6 μs After this period, the first clock is generated

HD;STA

0.6 μs Relevant for repeated start condition

SU;STA

0.1 μs

SU;DAT

0.6 μs

SU;STO

(Master) 0 μs

HD;DAT

LOW

0.3 μs

) 1.3 μs

BUF

HD;STA

SCL

SDA

BUF

HD;STA

HD;DAT

HIGH

SU;DAT

SU;STA

SU;STO

05469-002

Figure 2. Serial Interface Timing Diagram

Rev. 0 | Page 5 of 28

AD7747

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

Positive Supply Voltage VDD to GND −0.3 V to +6.5 V Voltage on any Input or Output Pin to

GND

ESD Rating (ESD Association Human Body

Model, S5.1)

Operating Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C

TSSOP Package θ

(Thermal Impedance-to-Air)

TSSOP Package θJC

(Thermal Impedance-to-Case)

Peak Reflow Soldering Temperature

Pb Free (20 sec to 40 sec) 260°C

−0.3 V to V

2000 V

128°C/W

14°C/W

+ 0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 6 of 28

AD7747

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCL

RDY

SHLD

TST

REFIN(+)

REFIN(–)

CIN1(–)

CIN1(+)

AD7747

TOP VIEW

(Not to Scale)

NC = NO CONNECT

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 SCL

Serial Interface Clock Input. Connects to the master clock line. Requires pull-up resistor if not already provided in the system.

Logic Output. A falling edge on this output indicates that a conversion on enabled channel(s) has been finished

RDY

and the new data is available. Alternatively, the status register can be read via the 2-wire serial interface and the relevant bit(s) decoded to query the finished conversion. If not used, this pin should be left as an open circuit.

3 SHLD

Capacitive Input Active AC Shielding. To eliminate the CIN parasitic capacitance to ground, the SHLD signal can be used for shielding the connection between the sensor and CIN. If not used, this pin should be left as an

open circuit. 4 TST This pin must be left as an open circuit for proper operation. 5, 6

REFIN(+), REFIN(−)

Differential Voltage Reference Input for the Voltage Channel (ADC). Alternatively, the on-chip internal reference

can be used for the voltage channel. These reference input pins are not used for conversion on capacitive

channel(s) (CDC). If not used, these pins can be left as an open circuit or connected to GND. 7 CIN1(−)

CDC Negative Capacitive Input. The measured capacitance is connected between the CIN1(−) pin and GND. If

not used, this pin should be left as an open circuit. 8 CIN1(+)

CDC Positive Capacitive Input. The measured capacitance is connected between the CIN1(+) pin and GND. If not

used, this pin should be left as an open circuit. 9, 10 NC Not Connected. These pins should be left as an open circuit. 11, 12 VIN(+), VIN(−)

Differential Voltage Input for the Voltage Channel (ADC). These pins are also used to connect an external

temperature sensing diode. If not used, these pins can be left as an open circuit or connected to GND. 13 GND Ground Pin. 14 VDD

Power Supply Voltage. This pin should be decoupled to GND, using a low impedance capacitor, for example in

combination with a 10 μF tantalum and a 0.1 μF multilayer ceramic. 15 NC Not Connected. This pin should be left as an open circuit. 16 SDA

Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if not provided

elsewhere in the system.

SDA

VDD

GND

IN(–)

IN(+)

05469-003

Rev. 0 | Page 7 of 28

AD7747

TYPICAL PERFORMANCE CHARACTERISTICS

INL (ppm)

–20

–40

–60

–80

–8 –7 –6 –5 –4 –3 –1–2 8

INPUT CAPACIT ANCE (pF)

01234567

Figure 4. Capacitance Input Integral Nonlinearity;

= 5 V, CAPDAC = 0x3F

2000

1000

–1000

GAIN ERROR (ppm)

–2000

–3000

–50 150

–25 0 25 50 75 100 125

TEMPERATURE (ºC)

GAIN TC ≈ –28ppm/ºC

Figure 5. Capacitance Input Gain Drift vs. Temperature;

= 5 V, CIN(+) to GND = 8 pF

.20

.15

.10

.050

–0.05

–0.10

–0.15

OFFSET ERROR (fF)

–0.20

–0.25

–0.30

–50 150

–25 0 25 50 75 100 125

TEMPERATURE (ºC)

–10

–20

CAP ERROR (fF)

–30

–40

05469-004

–50

2.7V

3.0V

3.3V

5.0V

0 600500

50 100 150 200 250 300 350 400 450 550

CAPACITANCE SHLD T O GND (pF )

05469-007

Figure 7. Capacitance Input Error vs. Capacitance Between SHLD and GND;

CIN(+) to GND = 8 pF, V

–10

–20

CAP ERROR (fF)

–30

–40

05469-005

–50

2.7V

3.0V

3.3V

5.0V

0 600500

50 100 150 200 250 300 350 400 450 550

CAPACITANCE SHLD T O GND (pF )

= 2.7 V, 3 V, 3.3 V, and 5 V

05469-008

Figure 8. Capacitance Input Error vs. Capacitance Between SHLD and GND;

CIN(+) to GND = 25 pF, V

–10

–20

CAP ERROR (fF)

–30

–40

05469-006

–50

2.7V

3.0V

3.3V

5.0V

0 600500

50 100 150 200 250 300 350 400 450 550

CAPACITANCE CIN TO SHLD (pF )

= 2.7 V, 3 V, 3.3 V, and 5 V

05469-009

Figure 6. Capacitance Input Offset Drift vs. Temperature;

= 5 V, CIN(+) Open

Rev. 0 | Page 8 of 28

Figure 9. Capacitance Input Error vs. Capacitance Between CIN(+) and SHLD;

CIN(+) to GND = 8 pF, V

= 2.7 V, 3 V, 3.3 V, and 5V

AD7747

150

100

CAP ERROR (fF)

–50

–100

–150

01k

10 100

PARALLEL RESISTANCE (MΩ)

05469-010

Figure 10. Capacitance Input Error vs. Parallel Resistance;

CIN(+) to GND = 8 pF, V

–100

–200

–300

–400

–500

–600

CAP ERROR (fF)

–700

–800

–900

–1000

0 200

25 50 75 1 00 125 150 175

CIN TO SHLD RE SISTANCE (kΩ)

= 5 V

05469-058

Figure 11. Capacitance Input Error vs. Resistance Between CIN1(+) and SHLD;

= 5 V

05469-059

100

–100

–200

–300

–400

–500

–600

CAP ERROR (fF)

–700

–800

–900

–1000

CIN(+) to GND = 8 pF, V

0.091

0.27 0. 48 0. 96 5 25 100

CIN TO SHLD RE SISTANCE (MΩ)

Figure 12. Capacitance Input Error vs. Resistance Between CIN(+) and SHLD;

CIN(+) to GND = 25 pF, V

= 5 V

1.0

0.8

0.6

0.4

0.2

–0.2

CAP ERROR (pF)

–0.4

–0.6

–0.8

–1.0

0.01

0.1 1.0 10.0

SHLD TO GND RESI STANCE (MΩ)

100

05469-066

Figure 13. Capacitance Input Error vs. Resistance Between SHLD and GND;

= 5 V

8 pF

25 pF

05469-067

100

CAP ERROR (fF)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CIN(+) to GND = 8 pF; V

SERIAL RESISTANCE (kΩ)

Figure 14. Capacitance Input Error vs. Serial Resistance;

CIN(+) to GND = 8 pF and 25pF, V

0.2

–0.2

CAP ERROR (fF)

–0.4

–0.6

3.0 3.5 4. 0 4.5 5.0

2.5 5.5

VDD (V)

= 5 V

05469-062

Figure 15. Capacitance Input Power Supply Rejection (PSR);

CIN(+) to GND = 8 pF

Rev. 0 | Page 9 of 28

+ 19 hidden pages

ANALOG DEVICES AD7747 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS