ANALOG DEVICES AD7746 Service Manual

24-Bit Capacitance-to-Digital Converter

www.BDTIC.com/ADI

FEATURES

Capacitance-to-digital converter

New standard in single chip solutions
Interfaces to single or differential floating sensors
Resolution down to 4 aF (that is, up to 21 ENOB)
Accuracy: 4 fF
Linearity: 0.01%
Common-mode (not changing) capacitance up to 17 pF
Full-scale (changing) capacitance range: ±4 pF
Tolerant of parasitic capacitance to ground up to 60 pF
Update rate: 10 Hz to 90 Hz
Simultaneous 50 Hz and 60 Hz rejection at 16 Hz

Temperature sensor on-chip

Resolution: 0.1°C, accuracy: ±2°C
Voltage input channel
Internal clock oscillator

2-wire serial interface (I
Power

2.7 V to 5.25 V single-supply operation

0.7 mA current consumption
Operating temperature: –40°C to +125°C
16-lead TSSOP package

APPLICATIONS

Automotive, industrial, and medical systems for

Pressure measurement
Position sensing
Level sensing
Flowmeters
Humidity sensing
Impurity detection

2

C®-compatible)

FUNCTIONAL BLOCK DIAGRAMS

VDD

with Temperature Sensor

AD7745/AD7746

GENERAL DESCRIPTION

The AD7745/AD7746 are a high resolution, Σ-Δ capacitance-to­digital converter (CDC). The capacitance to be measured is
connected directly to the device inputs. The architecture fea­tures inherent high resolution (24-bit no missing codes, up to
21-bit effective resolution), high linearity (±0.01%), and high
accuracy (±4 fF factory calibrated). The AD7745/AD7746
capacitance input range is ±4 pF (changing), while it can accept
up to 17 pF common-mode capacitance (not changing), which
can be balanced by a programmable on-chip, digital-to­capacitance converter (CAPDAC).

The AD7745 has one capacitance input channel, while the
AD7746 has two channels. Each channel can be configured as
single-ended or differential. The AD7745/AD7746 are designed
for floating capacitive sensors. For capacitive sensors with one
plate connected to ground, the AD7747 is recommended.

The parts have an on-chip temperature sensor with a resolution
of 0.1°C and accuracy of ±2°C. The on-chip voltage reference
and the on-chip clock generator eliminate the need for any
external components in capacitive sensor applications. The
parts have a standard voltage input, which together with the
differential reference input allows easy interface to an external
temperature sensor, such as an RTD, thermistor, or diode.

2

The AD7745/AD7746 have a 2-wire, I
interface. Both parts can operate with a single power supply
from 2.7 V to 5.25 V. They are specified over the automotive
temperature range of –40°C to +125°C and are housed in a
16-lead TSSOP package.

C-compatible serial

VDD

TEMP

SENSOR

VIN(+)
VIN(–)

CIN1(+)
CIN1(–)

CAP DAC

CAP DAC

EXCA
EXCB

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

EXCITATION

MUX

CLOCK

GENERATOR

24-BIT Σ-∆

MODULATOR

REFIN(+) REFIN(–) GND

Figure 1.

DIGITAL

FILTER

CONTROL LOGIC

CALIBRATION

VOLTAGE

REFERENCE

AD7745

SERIAL

INTERFACE

I2C

SDA

SCL

RDY

VIN(+)
VIN(–)

CIN1(+)
CIN1(–)

CIN2(+)
CIN2(–)

EXC1
EXC2

05468-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

TEMP

SENSOR

CAP DAC

CAP DAC

EXCITATION

MUX

CLOCK

GENERATOR

24-BIT Σ-∆

MODULATOR

REFIN(+) REFIN(–) GND

Figure 2.

DIGITAL

FILTER

CONTROL LOGIC

CALIBRATION

VOLTAGE

REFERENCE

AD7746

SERIAL

INTERFACE

I2C

SDA

SCL

RDY

05468-002

AD7745/AD7746

www.BDTIC.com/ADI

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics............................................. 8

Output Noise and Resolution Specifications ..............................11

Serial Interface ................................................................................ 12

Read Operation........................................................................... 12

Write Operation.......................................................................... 12

AD7745/AD7746 Reset ............................................................. 13

General Call................................................................................. 13

Register Descriptions ..................................................................... 14

Status Register ............................................................................. 15

Cap Data Register....................................................................... 15

VT Data Register........................................................................ 15

Cap Set-Up Register................................................................... 16

VT Set-Up Register.................................................................... 16

EXC Set-Up Register.................................................................. 17

Configuration Register .............................................................. 18

Cap DAC A Register................................................................... 19

Cap DAC B Register................................................................... 19

Cap Offset Calibration Register................................................19

REVISION HISTORY

4/05—Revision 0: Initial Version

Cap Gain Calibration Register.................................................. 19

Volt Gain Calibration Register ................................................. 19

Circuit Description......................................................................... 20

Overview ..................................................................................... 20

Capacitance-to-Digital Converter ........................................... 20

Excitation Source........................................................................ 20

CAPDAC..................................................................................... 21

Single-Ended Capacitive Input................................................. 21

Differential Capacitive Input .................................................... 21

Parasitic Capacitance to Ground.............................................. 22

Parasitic Resistance to Ground................................................. 22

Parasitic Parallel Resistance ...................................................... 22

Parasitic Serial Resistance ......................................................... 23

Capacitive Gain Calibration ..................................................... 23

Capacitive System Offset Calibration...................................... 23

Internal Temperature Sensor .................................................... 23

External Temperature Sensor ................................................... 24

Volt a ge In p ut ............................................................................... 24

V

Monitor ................................................................................ 24

DD

Typical Application Di agram .................................................... 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

Rev. 0 | Page 2 of 28

AD7745/AD7746

www.BDTIC.com/ADI

SPECIFICATIONS

VDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; GND = 0 V; EXC = 32 kHz; EXC = ±VDD/2; –40°C to +125°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

CAPACITIVE INPUT

Conversion Input Range ±4.096 pF
Integral Nonlinearity (INL)

2

±0.01 % of FSR

No Missing Codes2 24 Bit Conversion time ≥ 62 ms
Resolution, p-p 16.5 Bit Conversion time = 62 ms, see Table 5
Resolution Effective 19 Bit Conversion time = 62 ms, see Table 5
Output Noise, rms 2

Absolute Error
Offset Error

3

2, 4

±4 fF
32 aF1

System Offset Calibration Range2 ±1 pF
Offset Drift vs. Temperature –1 aF/°C
Gain Error

5

0.02 0.08 % of FS 25°C, VDD = 5 V
Gain Drift vs. Temperature2 –28 –26 –24 ppm of FS/°C
Allowed Capacitance to GND2 60 pF See Figure 9 and Figure 10
Power Supply Rejection 0.3 1 fF/V
Normal Mode Rejection 65 dB 50 Hz ± 1%, conversion time = 62 ms
55 dB 60 Hz ± 1%, conversion time = 62 ms
Channel-to-Channel Isolation 70 dB AD7746 only

CAPDAC

Full Range 17 21 pF
Resolution

6

164 fF 7-bit CAPDAC

Drift vs. Temperature2 24 26 28 ppm of FS/°C

EXCITATION

Frequency 32 kHz
Voltage Across Capacitance ±VDD/8 V Configurable via digital interface
±VDD/4 V

±V

DD

× 3/8

V

±VDD/2 V
Average DC Voltage Across

<±40 mV

Capacitance

Allowed Capacitance to GND2 100 pF See Figure 11

TEMPERATURE SENSOR

7

V
Resolution 0.1 °C
Error2 ±0.5 ±2 °C Internal temperature sensor
±2 °C External sensing diode

VOLTAGE INPUT7 V

Differential VIN Voltage Range ±V

REF

V
Absolute VIN Voltage2 GND − 0.03 VDD + 0.03 V
Integral Nonlinearity (INL) ±3 ±15 ppm of FS
No Missing Codes2 24 Bit Conversion time = 122.1 ms
Resolution, p-p 16 Bits

Output Noise 3 µV rms

Offset Error ±3 µV
Offset Drift vs. Temperature 15 nV/°C
Full-Scale Error

2, 9

0.025 0.1 % of FS

1

Factory calibrated

aF/√Hz

1

25°C, VDD = 5 V, after offset calibration

See Table 5

After system offset calibration,
Excluding effect of noise

internal

REF

internal or V

REF

REF

8

= 2.5 V

4

Conversion time = 62 ms
See Table 6 and Table 7

Conversion time = 62 ms
See Table 6 and Table 7

Rev. 0| Page 3 of 28

AD7745/AD7746

www.BDTIC.com/ADI

Parameter Min Typ Max Unit Test Conditions/Comments

Full-Scale Drift vs. Temperature 5 ppm of FS/°C Internal reference

0.5 ppm of FS/°C External reference
Average VIN Input Current 300 nA/V
Analog VIN Input Current Drift ±50 pA/V/°C
Power Supply Rejection 80 dB Internal reference, VIN = V
Power Supply Rejection 90 dB External reference, VIN = V
Normal Mode Rejection 75 dB 50 Hz ± 1%, conversion time = 122.1 ms
50 dB 60 Hz ± 1%, conversion time = 122.1 ms
Common-Mode Rejection 95 dB VIN = 1 V

INTERNAL VOLTAGE REFERENCE

Voltage 1.169 1.17 1.171 V TA = 25°C
Drift vs. Temperature 5 ppm/°C

EXTERNAL VOLTAGE REFERENCE INPUT

Differential REFIN Voltage2 0.1 2.5 V

DD

V
Absolute REFIN Voltage2 GND − 0.03 VDD + 0.03 V
Average REFIN Input Current 400 nA/V
Average REFIN Input Current Drift ±50 pA/V/°C
Common-Mode Rejection 80 dB

SERIAL INTERFACE LOGIC INPUTS
(SCL, SDA)

VIH Input High Voltage 2.1 V
VIL Input Low Voltage 0.8 V
Hysteresis 150 mV
Input Leakage Current (SCL) ±0.1 ±1 µA

OPEN-DRAIN OUTPUT (SDA)

VOL Output Low Voltage 0.4 V

IOH Output High Leakage Current 0.1 1 µA V

LOGIC OUTPUT (

RDY

)
VOL Output Low Voltage 0.4 V I
VOH Output High Voltage 4.0 V I
VOL Output Low Voltage 0.4 V I
VOH Output High Voltage VDD – 0.6 V I

I

= −6.0 mA

SINK

= V

OUT

DD

= 1.6 mA, VDD = 5 V

SINK

= 200 µA, VDD = 5 V

SOURCE

= 100 µA, VDD = 3 V

SINK

= 100 µA, VDD = 3 V

SOURCE

POWER REQUIREMENTS

VDD-to-GND Voltage 4.75 5.25 V VDD = 5 V, nominal

2.7 3.6 V VDD = 3.3 V, nominal
IDD Current 850 µA Digital inputs equal to VDD or GND
750 µA VDD = 5 V
700 µA VDD = 3.3 V
IDD Current Power-Down Mode 0.5 2 µA Digital inputs equal to VDD or GND

1

Capacitance units: 1 pF = 10

2

Specification is not production tested, but is supported by characterization data at initial product release.

3

Factory calibrated. The absolute error includes factory gain calibration error, integral nonlinearity error, and offset error after system offset calibration, all at 25°C. At

different temperatures, compensation for gain drift over temperature is required.

4

The capacitive input offset can be eliminated using a system offset calibration. The accuracy of the system offset calibration is limited by the offset calibration register

LSB size (32 aF) or by converter + system p-p noise during the system capacitive offset calibration, whichever is greater. To minimize the effect of the converter +
system noise, longer conversion times should be used for system capacitive offset calibration. The system capacitance offset calibration range is ±1 pF, the larger
offset can be removed using CAPDACs.

5

The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required.

6

The CAPDAC resolution is seven bits in the actual CAPDAC full range. Using the on-chip offset calibration or adjusting the capacitive offset calibration register can

further reduce the CIN offset or the unchanging CIN component.

7

The VTCHOP bit in the VT SETUP register must be set to 1 for the specified temperature sensor and voltage input performance.

8

Using an external temperature sensing diode 2N3906, with nonideality factor nf = 1.008, connected as in Figure 41, with total serial resistance <100 Ω.

9

Full-scale error applies to both positive and negative full scale.

-12

F; 1 fF = 10

-15

F; 1 aF = 10

-18

F.

REF

REF

/2

/2

Rev. 0 | Page 4 of 28

AD7745/AD7746

A

www.BDTIC.com/ADI

TIMING SPECIFICATIONS

VDD = 2.7 V to 3.6 V, or 4.75 V to 5.25 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; –40°C to +125°C, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

SERIAL INTERFACE

SCL Frequency 0 400 kHz
SCL High Pulse Width, t
SCL Low Pulse Width, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Hold Time (Start Condition), t
Set-Up Time (Start Condition), t
Data Set-Up Time, t
Data Set-Up Time, t
Set-Up Time (Stop Condition), t
Data Hold Time, t
Bus-Free Time (Between Stop and Start Condition, t

1

Sample tested during initial release to ensure compliance.

2

All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.

Output load = 10 pF.

1, 2

HIGH

LOW

R

F

HD;STA

SU;STA

SU;DAT

SU;DAT

SU;STO

(Master) 0 µs

HD;DAT

See Figure 3

0.6 µs

1.3 µs

0.3 µs

0.3 µs

0.6 µs After this period, the first clock is generated

0.6 µs Relevant for repeated start condition

0.25 µs VDD ≥ 3.0 V

0.35 µs VDD < 3.0 V

0.6 µs

) 1.3 µs

BUF

t

LOW

t

R

t

F

t

HD:STA

SCL

SD

t

t

BUF

PS

HD:STA

t

HD:DAT

t

HIGH

t

SU:DAT

Figure 3. Serial Interface Timing Diagram

t

SU:STA

S

t

SU:STO

P

05468-003

Rev. 0| Page 5 of 28

AD7745/AD7746

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

Positive Supply Voltage VDD to GND

Voltage on any Input or Output Pin to
GND

ESD Rating (ESD Association Human Body
Model, S5.1)

Operating Temperature Range –40°C to +125°C
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C

TSSOP Package θJA,
(Thermal Impedance-to-Air)

TSSOP Package θJC,
(Thermal Impedance-to-Case)

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

−0.3 V to +6.5 V

–0.3 V to V

2000 V

128°C/W

14°C/W

+ 0.3 V

DD

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 28

AD7745/AD7746

www.BDTIC.com/ADI

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

SCL

2

RDY

EXCA

3

EXCB
REFIN(+)
REFIN(–)

CIN1(–)
CIN1(+)

AD7745

4

TOP VIEW

5

(Not to Scale)

6
7
8

NC = NO CONNECT

Figure 4. AD7745 Pin Configuration (16-Lead TSSOP)

16

SDA

15

NC

14

VDD

13

GND

12

VIN(–)

11

VIN(+)

10

NC
NC

9

05468-004

Figure 5. AD7746 Pin Configuration (16-Lead TSSOP)

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 SCL

Serial Interface Clock Input. Connects to the master clock line. Requires pull-up resistor if not already
provided in the system.

2

RDY

Logic Output. A falling edge on this output indicates that a conversion on enabled channel(s) has been
finished and the new data is available. Alternatively, the status register can be read via the 2-wire serial
interface and the relevant bit(s) decoded to query the finished conversion. If not used, this pin should be left
as an open circuit.

3, 4 EXCA, EXCB

CDC Excitation Outputs. The measured capacitance is connected between one of the EXC pins and one of the
CIN pins. If not used, these pins should be left as an open circuit.

5, 6

REFIN(+),
REFIN(–)

Differential Voltage Reference Input for the Voltage Channel (ADC). Alternatively, the on-chip internal
reference can be used for the voltage channel. These reference input pins are not used for conversion on
capacitive channel(s) (CDC). If not used, these pins can be left as an open circuit or connected to GND.

7 CIN1(–)

CDC Negative Capacitive Input in Differential Mode. This pin is internally disconnected in single-ended CDC
configuration. If not used, this pin can be left as an open circuit or connected to GND.

8 CIN1(+)

CDC Capacitive Input (in Single-Ended Mode) or Positive Capacitive Input (in Differential Mode). The
measured capacitance is connected between one of the EXC pins and one of the CIN pins. If not used, this pin
can be left as an open circuit or connected to GND.

9, 10

NC Not Connected. This pin should be left as an open circuit.

(AD7745)
9

(AD7746)
10

(AD7746)
11, 12 VIN(+), VIN(–)

CIN2(+)

CIN2(–)

CDC Second Capacitive Input (in Single-Ended Mode) or Positive Capacitive Input (in Differential Mode). If not
used, this pin can be left open circuit or connected to GND.

CDC Negative Capacitive Input in Differential Mode. This pin is internally disconnected in a single-ended CDC
configuration. If not used, this pin can be left as an open circuit or connected to GND.

Differential Voltage Input for the Voltage Channel (ADC). These pins are also used to connect an external

temperature sensing diode. If not used, these pins can be left as an open circuit or connected to GND.
13 GND Ground Pin.
14 VDD

Power Supply Voltage. This pin should be decoupled to GND, using a low impedance capacitor, for example

in combination with a 10 µF tantalum and a 0.1 µF multilayer ceramic.
15 NC Not Connected. This pin should be left as an open circuit.
16 SDA

Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if not provided

elsewhere in the system.

SCL
RDY

EXCA

EXCB
REFIN(+)
REFIN(–)

CIN1(–)
CIN1(+)

1
2
3

AD7746

4

TOP VIEW

5

(Not to Scale)

6
7
8

NC = NO CONNECT

16
15
14
13
12
11
10

9

SDA
NC
VDD
GND
VIN(–)
VIN(+)
CIN2(–)
CIN2(+)

05468-005

Rev. 0| Page 7 of 28

AD7745/AD7746

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

100

80

60

INL (ppm)

40

20

0

–5 5

–4 –3 –2 –1 0 1 2 3 4

INPUT CAPACITANCE (pF)

Figure 6. Capacitance Input Integral Nonlinearity,

V

= 5 V, the Same Configuration as in Figure 31

DD

2000

1000

0

–1000

GAIN ERROR (ppm)

–2000

–3000

–50 150

–25 0 25 50 75 100 125

TEMPERATURE (°C)

GAIN TC ≈ –26ppm/°C

Figure 7. Capacitance Input Offset Drift vs. Temperature,

= 5 V, CIN and EXC Pins Open Circuit

V

DD

100

75

50

25

0

–25

OFFSET ERROR (aF)

–50

–75

–100

–50 150

–25 0 25 50 75 100 125

TEMPERATURE (°C)

Figure 8. Capacitance Input Gain Drift vs. Temperature,

V

= 5 V, CIN(+) to EXC = 4 pF, the Same Configuration as in Figure 30

DD

05468-014

05468-015

05468-016

18

16

14

12

10

8

6

4

CAPACITANCE ERROR (fF)

2

0

–2

0 500

50 100 150 200 250 300 350 400 450

CAPACITANCE CIN PIN TO GND (pF)

2.7V 3V 5V3.3V

05468-017

Figure 9. Capacitance Input Error vs. Capacitance between CIN and GND.

CIN(+) to EXC = 4 pF, CIN(−) to EXC = 0 pF, V

= 2 .7 V, 3 V, 3. 3 V, an d 5 V,

DD

the Same Configuration as in Figure 33

18

16

14

12

10

8

6

4

CAPACITANCE ERROR (fF)

2

0

–2

0 500

50 100 150 200 250 300 350 400 450

2.7V 3V 3.3V

5V

CAPACITANCE CIN PIN TO GND (pF)

05468-018

Figure 10. Capacitance Input Error vs. Capacitance between CIN and GND,

CIN(+) to EXC = 21 pF, CIN(−) to EXC = 23 pF, V

= 2.7 V, 3 V, 3.3 V, and 5 V,

DD

the Same Configuration as in Figure 34

5

4

3

2

1

CAPACITANCE ERROR (fF)

0

–1

0 500

50 100 150 200 250 300 350 400 450

CAPACITANCE EXC PIN TO GND (pF)

2.7V

3V

5V

3.3V

05468-019

Figure 11. Capacitance Input Error vs. Capacitance between EXC and GND,

CIN(+) to EXC = 21 pF, CIN(−) to EXC = 23 pF, V

= 2.7 V, 3 V, 3.3 V, and 5 V,

DD

the Same Configuration as in Figure 34

Rev. 0 | Page 8 of 28

AD7745/AD7746

www.BDTIC.com/ADI

8

6

4

2

0

–2

–4

–6

CAPACITANCE ERROR (fF)

–8

–10

–12

–250

3V

2.7V

–200 –150 –100 –50 0 50 100 150 200

CIN LEAKAGE TO GND (nA)

Figure 12. Capacitance Input Error vs. Leakage Current to GND,

CIN(+) to EXC = 4 pF, CIN(−) to EXC = 0 pF,

= 2.7 V and 3 V

V

DD

8

6

4

2

0

5V
–2

–4

–6

CAPACITANCE ERROR (fF)

–8

–10

–12

–250 250

3.3V

–200 –150 –100 –50 0 50 100 150 200

CIN LEAKAGE TO GND (nA)

Figure 13. Capacitance Input Error vs. Leakage Current to GND,

CIN(+) to EXC =4 pF, CIN(−) to EXC = 0 pF,

VDD=3.3 V and 5 V

10

250

05468-028

05468-030

0

–2

–4

–6

CAPACITANCE ERROR (fF)

–8

–10

123456

07

SERIAL RESISTANCE (kΩ)

05468-031

Figure 15. Capacitance Input Error vs. Serial Resistance,

CIN(+) to EXC = 21 pF, CIN(−) to EXC = 23 pF, V

DD

= 5 V,

the Same Configuration as in Figure 34.

0.2

0

–0.2

–0.4

–0.6

CAPACITANCE ERROR (fF)

–0.8

–1.0

2.5

3.0 3.5 4.0 4.5 5.0
VDD (V)

5.5

05468-032

Figure 16. Capacitance Input Power Supply Rejection (PSR),

CIN(+) to EXC = 4 pF, the Same Configuration as in Figure 30

0.20

1

0.1

0.01

CAPACITANCE ERROR (pF)

0.001

0.0001
1 100000

10 100 1000 10000

PARALLEL RESISTANCE (MΩ)

Figure 14. Capacitance Input Error vs. Resistance in Parallel

05468-029

0.15

0.10

0.05

0

–0.05

CAPDAC CODE DNL (pF)

–0.10

–0.15

–0.20

0 128

16 32 48 64 80 96 112

Figure 17. CAPDAC Differential Nonlinearity (DNL)

with Measured Capacitance

Rev. 0| Page 9 of 28

CAPDAC CODE

05468-033