Analog Devices AD7713 d Datasheet
LC2MOS
Loop-Powered Signal Conditioning ADC
FEATURES
Charge Balancing ADC
24 Bits No Missing Codes
ⴞ0.0015% Nonlinearity
3-Channel Programmable Gain Front End
Gains from 1 to 128
2 Differential Inputs
1 Single-Ended High Voltage Input
Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients
Bidirectional Microcontroller Serial Interface
Single-Supply Operation
Low Power (3.5 mW typ) with Power-Down Mode
(150 W typ)
APPLICATIONS
Loop Powered (Smart) Transmitters
RTD Transducers
Process Control
Portable Industrial Instruments
GENERAL DESCRIPTION
The AD7713 is a complete analog front end for low frequency
measurement applications. The device accepts low level signals
directly from a transducer or high level signals (4 ⫻ V
REF
) and
outputs a serial digital word. It employs ⌺-⌬ conversion
technique to realize up to 24 bits of no missing codes
performance. The input signal is applied to a proprietary programmable gain front end based around an analog modulator.
The modulator output is processed by an on-chip digital filter.
The first notch of this digital filter can be programmed via the
on-chip control register, allowing adjustment of the filter cutoff
and settling time.
The part features two differential analog inputs and one singleended high level analog input as well as a differential reference
input. It can be operated from a single supply (AV
and DV
DD
DD
at 5 V). The part provides two current sources that can be used
to provide excitation in 3-wire and 4-wire RTD configurations.
The AD7713 thus performs all signal conditioning and conversion for a single-, dual- or three-channel system.
The AD7713 is ideal for use in smart, microcontroller-based
systems. Gain settings, signal polarity, and RTD current control
can be configured in software using the bidirectional serial port.
The AD7713 contains self-calibration, system calibration, and
background calibration options and also allows the user to read
and to write the on-chip calibration registers.
*Protected by U.S. Patent No. 5,134,401.
AD7713
*
FUNCTIONAL BLOCK DIAGRAM
REF
DD
1A
200A
200A
REF
IN(–)
PGA
MUX
A = 1 – 128
AV
DD
IN(+)
AD7713
CHARGING BALANCING ADC
AUTO-ZEROED
⌺-⌬
MODULATOR
SERIAL INTERFACE
CONTROL
REGISTER
MODE SDATA A0DRDYTFSRFS SCLK
STANDBY
DIGITAL
FILTER
CLOCK
GENERATION
OUTPUT
REGISTER
SYNC
MCLK
IN
MCLK
OUT
AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)
AIN3
RTD1
RTD2
AV
DDDVDD
AV
INPUT
SCALING
AGND DGND
CMOS construction ensures low power dissipation, and a hardware programmable power-down mode reduces the standby
power consumption to only 150 µW typical. The part is available
in a 24-lead, 0.3 inch wide, PDIP and CERDIP as well as a 24lead SOIC package.
PRODUCT HIGHLIGHTS
1. The AD7713 consumes less than 1 mA in total supply current,
making it ideal for use in loop-powered systems.
2. The two programmable gain channels allow the AD7713 to
accept input signals directly from a transducer removing a
considerable amount of signal conditioning. To maximize
the flexibility of the part, the high level analog input accepts
4 ⫻ V
signals. On-chip current sources provide excitation
REF
for 3-wire and 4-wire RTD configurations.
3. No missing codes ensures true, usable, 24-bit dynamic range
coupled with excellent ±0.0015% accuracy. The effects of
temperature drift are eliminated by on-chip self-calibration,
which removes zero-scale and full-scale errors.
4. The AD7713 is ideal for microcontroller or DSP processor
applications with an on-chip control register, which allows
control over filter cutoff, input gain, signal polarity, and
calibration modes. The AD7713 allows the user to read and
write the on-chip calibration registers.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
AD7713–SPECIFICATIONS
MCLK IN = 2 MHz, unless otherwise noted. All specifications T
Parameter A, S Versions
(AVDD = 5 V ⴞ 5%; DVDD = 5 V ⴞ 5%; REF IN(+) = 2.5 V; REF IN(–) = AGND;
to T
MIN
, unless otherwise noted.)
MAX
1
Unit Conditions/Comments
STATIC PERFORMANCE
No Missing Codes 24 Bits min Guaranteed by Design.
For Filter Notches ≤ 12 Hz.
22 Bits min For Filter Notch = 20 Hz.
18 Bits min For Filter Notch = 50 Hz.
15 Bits min For Filter Notch = 100 Hz.
12 Bits min For Filter Notch = 200 Hz.
Output Noise See Tables I and II Depends on Filter Cutoffs and Selected Gain.
Integral Nonlinearity ±0.0015 % of FSR max Filter Notches ≤ 12 Hz; Typically ±0.0003%.
Positive Full-Scale Error
Full-Scale Drift
5
Unipolar Offset Error
Unipolar Offset Drift
Bipolar Zero Error
Bipolar Zero Drift
5
2, 4
5
2, 4
2, 3, 4
1 µV/°C typ For Gains of 1, 2.
0.3 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128.
0.5 µV/°C typ For Gains of 1, 2.
0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128.
0.5 µV/°C typ For Gains of 1, 2.
0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128.
Gain Drift 2 ppm/°C typ
Bipolar Negative Full-Scale Error
Bipolar Negative Full-Scale Drift
2
5
±0.0004 % of FSR max Typically ±0.0006%.
1 µV/°C typ For Gains of 1, 2.
0.3 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128.
ANALOG INPUTS
Input Sampling Rate, f
Normal-Mode 50 Hz Rejection
Normal-Mode 60 Hz Rejection
AIN1, AIN2
7
Input Voltage Range
S
8
6
6
See Table III
100 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz,
25 Hz, 50 Hz, ±0.02 ⫻ f
NOTCH
.
100 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz,
30 Hz, 60 Hz, ±0.02 ⫻ f
NOTCH
.
For Normal Operation.
Depends on Gain Selected.
0 to +V
REF
9
V max Unipolar Input Range
(B/U Bit of Control Register = 1).
±V
REF
V max Bipolar Input Range
(B/U Bit of Control Register = 0).
Common-Mode Rejection (CMR) 100 dB min At dc and AV
Common-Mode 50 Hz Rejection
Common-Mode 60 Hz Rejection
Common-Mode Voltage Range
6
6
10
90 dB min At dc and AV
150 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz,
25 Hz, 50 Hz, ±0.02 ⫻ f
150 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz,
30 Hz, 60 Hz, ±0.02 ⫻ f
AGND to AV
DD
V min to V max
= 5 V.
DD
= 10 V.
DD
NOTCH.
NOTCH.
DC Input Leakage Current @ 25°C10 pA max
to T
T
MIN
MAX
Sampling Capacitance
6
1nA max
20 pF max
AIN3
Input Voltage Range 0 to + 4 ⫻ V
Gain Error
11
±0.05 % typ Additional Error Contributed by Resistor
REF
V max For Normal Operation. Depends on Gain
Selected.
Attenuator.
Gain Drift 1 ppm/°C typ Additional Drift Contributed by Resistor
Attenuator.
Offset Error
11
4 mV max Additional Error Contributed by Resistor
Attenuator.
Input Impedance 30 kΩ min
REV. D–2–
AD7713
Parameter A, S Versions
1
Unit Conditions/Comments
REFERENCE INPUT
REF IN(+) – REF IN(–) Voltage 2.5 to AVDD/1.8 V min to V max For Specified Performance. Part Is
Functional with Lower V
f
Input Sampling Rate, f
Normal-Mode 50 Hz Rejection
Normal-Mode 60 Hz Rejection
S
6
6
/512
CLK IN
100 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz,
25 Hz, 50 Hz, ±0.02 ⫻ f
100 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz,
30 Hz, 60 Hz, ±0.02 ⫻ f
Common-Mode Rejection (CMR) 100 dB min At DC.
Common-Mode 50 Hz Rejection
Common-Mode 60 Hz Rejection
Common-Mode Voltage Range
6
6
10
150 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz,
25 Hz, 50 Hz, ±0.02 ⫻ f
150 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz,
30 Hz, 60 Hz, ±0.02 ⫻ f
AGND to AV
DD
V min to V max
Voltages.
REF
NOTCH
NOTCH
NOTCH
NOTCH
.
.
.
.
DC Input Leakage Current @ 25°C10 pA max
T
MIN
to T
MAX
1nA max
LOGIC INPUTS
Input Current ±10 µA max
All Inputs Except MCLK IN
, Input Low Voltage 0.8 V max
V
INL
V
, Input High Voltage 2.0 V min
INH
MCLK IN Only
, Input Low Voltage 0.8 V max
V
INL
V
, Input High Voltage 3.5 V min
INH
LOGIC OUTPUTS
VOL, Output Low Voltage 0.4 V max I
, Output High Voltage 4.0 V min I
V
OH
Floating State Leakage Current ±10 µA max
Floating State Output Capacitance
12
9 pF typ
= 1.6 mA.
SINK
SOURCE
= 100 µA.
TRANSDUCER BURN-OUT
Current 1.2 µA nom
Initial Tolerance @ 25°C ±10 % typ
Drift 0.1 %/°C typ
RTD EXCITATION CURRENTS
(RTD1, RTD2)
Output Current 200 µA nom
Initial Tolerance @ 25°C ±20 % max
Drift 20 ppm/°C typ
Initial Matching @ 25°C ±1% max Matching Between RTD1 and RTD2 Currents.
Drift Matching 3 ppm/°C typ Matching Between RTD1 and RTD2 Current
Drift.
Line Regulation (AV
) 200 nA/V max AVDD = 5 V.
DD
Load Regulation 200 nA/V max
SYSTEM CALIBRATION
AIN1, AIN2
Positive Full-Scale Calibration Limit
Negative Full-Scale Calibration Limit
Offset Calibration Limit
Input Span
14
14, 15
13
13
+(1.05 ⫻ V
–(1.05 ⫻ V
–(1.05 ⫻ V
+(0.8 ⫻ V
)/GAIN V max GAIN Is the Selected PGA Gain
REF
(Between 1 and 128).
)/GAIN V max GAIN Is the Selected PGA Gain
REF
(Between 1 and 128).
)/GAIN V max GAIN Is the Selected PGA Gain
REF
(Between 1 and 128).
)/GAIN V min GAIN Is the Selected PGA Gain
REF
(Between 1 and 128).
+(2.1 ⫻ V
)/GAIN V max GAIN Is the Selected PGA Gain
REF
(Between 1 and 128).
REV. D
–3–
AD7713
Parameter A, S Versions
1
Unit Conditions/Comments
AIN3
Positive Full-Scale Calibration Limit13+(4.2 ⫻ V
Offset Calibration Limit
15
0 to V
)/GAIN V max GAIN Is the Selected PGA Gain
REF
(Between 1 and 128).
/GAIN V max GAIN Is the Selected PGA Gain
REF
(Between 1 and 128).
Input Span +(3.2 ⫻ V
)/GAIN V min GAIN Is the Selected PGA Gain
REF
(Between 1 and 128).
+(4.2 ⫻ V
)/GAIN V max GAIN Is the Selected PGA Gain
REF
(Between 1 and 128).
POWER REQUIREMENTS
Power Supply Voltages
AVDD Voltage
Voltage
DV
DD
16
17
5 to 10 V nom ±5% for Specified Performance.
5V nom ± 5% for Specified Performance.
Power Supply Currents
Current 0.6 mA max AVDD = 5 V.
AV
DD
Current 0.5 mA max f
DV
DD
Power Supply Rejection
and DVDD)
(AV
DD
19
0.7 mA max AV
1 mA max f
18
dB typ
= 10 V.
DD
= 1 MHz.
CLK IN
Digital Inputs 0 V to DV
= 2 MHz.
CLK IN
Digital Inputs 0 V to DV
Rejection w.r.t. AGND.
DD
DD
.
.
Power Dissipation
Normal Mode 5.5 mW max AV
= DVDD = 5 V, f
DD
CLK IN
= 1 MHz;
Typically 3.5 mW.
Standby (Power-Down) Mode 300 µW max AVDD = DVDD = 5 V, Typically 150 µW.
NOTES
1
Temperature range is: A Version, –40°C to +85°C; S Version, –55°C to +125°C.
2
Applies after calibration at the temperature of interest.
3
Positive full-scale error applies to both unipolar and bipolar input ranges.
4
These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 µV typical after self-calibration
or background calibration.
5
Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
6
These numbers are guaranteed by design and/or characterization.
7
The AIN1 and AIN2 analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recommended source resistance depends on the selected gain.
8
The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs. The input voltage
range on the AIN3 input is with respect to AGND. The absolute voltage on the AIN1 and AIN2 inputs should not go more positive than AVDD + 30 mV or more
negative than AGND – 30 mV.
9
V
= REF IN(+) – REF IN(–).
REF
10
This common-mode voltage range is allowed, provided that the input voltage on AIN(+) and AIN(–) does not exceed AV
11
This error can be removed using the system calibration capabilities of the AD7713. This error is not removed by the AD7713’s self-calibration feature. The offset
drift on the AIN3 input is four times the value given in the Static Performance section of the specifications.
12
Guaranteed by design, not production tested.
13
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, the device will
output all 0s.
14
These calibration and span limits apply provided the absolute voltage on the AIN1 and AIN2 analog inputs does not exceed AV
AGND – 30 mV.
15
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
16
Operating with AVDD voltages in the range 5.25 V to 10.5 V is guaranteed only over the 0°C to 70°C temperature range.
17
The ± 5% tolerance on the DVDD input is allowed provided that DVDD does not exceed AVDD by more than 0.3 V.
18
Measured at dc and applies in the selected pass band. PSRR at 50 Hz will exceed 120 dB with filter notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, or 50 Hz. PSRR at 60 Hz
will exceed 120 dB with filter notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, or 60 Hz.
19
PSRR depends on gain: gain of 1 = 70 dB typ; gain of 2 = 75 dB typ; gain of 4 = 80 dB typ; gains of 8 to 128 = 85 dB typ.
Specifications subject to change without notice.
+ 30 mV and AGND – 30 mV.
DD
+ 30 mV or go more negative than
DD
REV. D–4–
AD7713
TIMING CHARACTERISTICS
Limit at T
MIN
(DVDD = 5 V ⴞ 5%; AVDD = 5 V or 10 V ⴞ 5%; AGND = DGND = 0 V; f
1, 2
Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted.)
, T
MAX
CLKIN
= 2 MHz;
Parameter (A, S Versions) Unit Conditions/Comments
3, 4
f
CLK IN
400 kHz min Master Clock Frequency: Crystal Oscillator or
2 MHz max Externally Supplied for Specified Performance
t
CLK IN LO
t
CLK IN HI
5
t
r
5
t
f
t
1
0.4 ⫻ t
CLK IN
0.4 ⫻ t
CLK IN
50 ns max Digital Output Rise Time; Typically 20 ns
50 ns max Digital Output Fall Time; Typically 20 ns
1000 ns min SYNC Pulse Width
ns min Master Clock Input Low Time; t
CLK IN
ns min Master Clock Input High Time
= 1/f
CLK IN
Self-Clocking Mode
t
2
t
3
t
4
t
5
t
6
6
t
7
6
t
8
t
9
t
10
t
14
t
15
t
16
t
17
t
18
t
19
0 ns min DRDY to RFS Setup Time
0 ns min DRDY to RFS Hold Time
2 ⫻ t
CLK IN
ns min A0 to RFS Setup Time
0 ns min A0 to RFS Hold Time
4 ⫻ t
4 ⫻ t
t
CLK IN
t
CLK IN
t
CLK IN
3 ⫻ t
+ 20 ns max RFS Low to SCLK Falling Edge
CLK IN
+20 ns max Data Access Time (RFS Low to Data Valid)
CLK IN
/2 ns min SCLK Falling Edge to Data Valid Delay
/2 + 30 ns max
/2 ns nom SCLK High Pulse Width
/2 ns nom SCLK Low Pulse Width
CLK IN
50 ns min A0 to TFS Setup Time
0 ns min A0 to TFS Hold Time
4 ⫻ t
4 ⫻ t
+ 20 ns max TFS to SCLK Falling Edge Delay Time
CLK IN
CLK IN
ns min TFS to SCLK Falling Edge Hold Time
0 ns min Data Valid to SCLK Setup Time
10 ns min Data Valid to SCLK Hold Time
External-Clocking Mode
f
f
SCLK
t
20
t
21
t
22
t
23
6
t
24
6
t
25
t
26
t
27
t
28
7
t
29
t
30
7
t
31
t
32
t
33
t
34
t
35
t
36
NOTES
1
Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 10 to 13.
3
CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7713 is not in standby mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.
4
The AD7713 is production tested with f
5
Specified using 10% and 90% points on waveform of interest.
6
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
7
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
/5 MHz max Serial Clock Input Frequency
CLK IN
0 ns min DRDY to RFS Setup Time
0 ns min DRDY to RFS Hold Time
2 ⫻ t
CLK IN
ns min A0 to RFS Setup Time
0 ns min A0 to RFS Hold Time
4 ⫻ t
CLK IN
ns max Data Access Time (RFS Low to Data Valid)
10 ns min SCLK Falling Edge to Data Valid Delay
2 ⫻ t
2 ⫻ t
2 ⫻ t
t
CLK IN
+ 20 ns max
CLK IN
CLK IN
CLK IN
ns min SCLK High Pulse Width
ns min SCLK Low Pulse Width
+ 10 ns max SCLK Falling Edge to DRDY High
10 ns min SCLK to Data Valid Hold Time
+ 10 ns max
t
CLK IN
10 ns min RFS/TFS to SCLK Falling Edge Hold Time
5 ⫻ t
/2 + 50 ns max RFS to Data Valid Hold Time
CLK IN
0 ns min A0 to TFS Setup Time
0 ns min A0 to TFS Hold Time
4 ⫻ t
2 ⫻ t
CLK IN
– SCLK High ns min Data Valid to SCLK Setup Time
CLK IN
ns min SCLK Falling Edge to TFS Hold Time
30 ns min Data Valid to SCLK Hold Time
at 2 MHz. It is guaranteed by characterization to operate at 400 kHz.
CLK IN
REV. D
–5–
AD7713
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V
AV
DD
AV
to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DV
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DV
DD
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AIN1, AIN2 Input Voltage
to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV
+ 0.3 V
DD
AIN3 Input Voltage to AGND . . . . . . . . . . . . –0.3 V to +22 V
Reference Input Voltage to AGND . . . –0.3 V to AV
Digital Input Voltage to DGND . . . . . –0.3 V to AV
Digital Output Voltage to DGND . . . –0.3 V to DV
+ 0.3 V
DD
+ 0.3 V
DD
+ 0.3 V
DD
Operating Temperature Range
Commercial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
PDIP Package, Power Dissipation . . . . . . . . . . . . . . . . 450 mW
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 105°C/W
JA
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 260°C
CERDIP Package, Power Dissipation . . . . . . . . . . . . . 450 mW
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
Lead Temperature, Soldering . . . . . . . . . . . . . . . . . . 300°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 450 mW
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 75°C/W
JA
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Power Dissipation (Any Package) to 75°C . . . . . . . . . . 450 mW
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature
Model Range Package Option*
AD7713AN –40°C to +85°C N-24
AD7713AR –40°C to +85°C RW-24
AD7713AR-REEL –40°C to +85°C RW-24
AD7713AR-REEL7 –40°C to +85°C RW-24
AD7713AQ –40°C to +85°C Q-24
AD7713SQ –55°C to +125°C Q-24
*N = PDIP; Q = CERDIP; RW = SOIC.
1.6mA
TO OUTPUT PIN
100pF
2.1V
200A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7713 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. D–6–
PIN CONFIGURATION
PDIP, CERDIP, AND SOIC
AD7713
SCLK
MCLK IN
MCLK OUT
A0
SYNC
MODE
AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)
STANDBY
AV
DD
1
2
3
4
5
AD7713
TOP VIEW
6
(Not to Scale)
7
8
9
10
11
12
24
DGND
23
DV
22
SDATA
21
DRDY
20
RFS
19
TFS
18
AGND
17
AIN3
16
RTD2
15
REF IN(+)
14
REF IN(–)
13
RTD1
DD
PIN FUNCTION DESCRIPTION
Pin No. Mnemonic Function
1 SCLK Serial Clock. Logic input/output, depending on the status of the MODE pin. When MODE is high, the
device is in its self-clocking mode, and the SCLK pin provides a serial clock output. This SCLK becomes active when RFS or TFS goes low, and it goes high impedance when either RFS or TFS returns
high or when the device has completed transmission of an output word. When MODE is low, the device
is in its external clocking mode and the SCLK pin acts as an input. This input serial clock can be a continuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a
noncontinuous clock with the information being transmitted to the AD7713 in smaller batches of data.
2 MCLK IN Master Clock Signal for the Device. This can be provided in the form of a crystal or external clock. A
crystal can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be
driven with a CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is
nominally 2 MHz.
3 MCLK OUT When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT.
4A0Address Input. With this input low, reading and writing to the device is to the control register. With
this input high, access is to either the data register or the calibration registers.
5 SYNC Logic Input. Allows for synchronization of the digital filters when using a number of AD7713s. It
resets the nodes of the digital filter.
6 MODE Logic Input. When this pin is high, the device is in its self-clocking mode. With this pin low, the
device is in its external clocking mode.
7 AIN1(+) Analog Input Channel 1. Positive input of the programmable gain differential analog input. The
AIN1(+) input is connected to an output current source that can be used to check that an external
transducer has burnt out or gone open circuit. This output current source can be turned on/off via the
control register.
8 AIN1(–) Analog Input Channel 1. Negative input of the programmable gain differential analog input.
9 AIN2(+) Analog Input Channel 2. Positive input of the programmable gain differential analog input.
10 AIN2(–) Analog Input Channel 2. Negative input of the programmable gain differential analog input.
11 STANDBY Logic Input. Taking this pin low shuts down the internal analog and digital circuitry, reducing power
consumption to less than 100 µW.
12 AV
DD
Analog Positive Supply Voltage, 5 V to 10 V.
13 RTD1 Constant Current Output. A nominal 200 µA constant current is provided at this pin, which can be
used as the excitation current for RTDs. This current can be turned on or off via the control register.
14 REF IN(–) Reference Input. The REF IN(–) can lie anywhere between AV
and AGND, provided REF IN(+) is
DD
greater than REF IN(–).
15 REF IN(+) Reference Input. The reference input is differential providing that REF IN(+) is greater than REF
IN(–). REF IN(+) can lie anywhere between AVDD and AGND.
REV. D
–7–
AD7713
Pin No. Mnemonic Function
16 RTD2 Constant Current Output. A nominal 200 µA constant current is provided at this pin, which can be used as
the excitation current for RTDs. This current can be turned on or off via the control register. This second
current can be used to eliminate lead resistanced errors in 3-wire RTD configurations.
17 AIN3 Analog Input Channel 3. High level analog input that accepts an analog input voltage range of 4 ⫻ V
At the nominal V
of 2.5 V and a gain of 1, the AIN3 input voltage range is 0 V to ±10 V.
REF
REF
/GAIN.
18 AGND Ground Reference Point for Analog Circuitry.
19 TFS Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial data
expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active after TFS
goes low. In the external clocking mode, TFS must go low before the first bit of the data-word is written to the part.
20 RFS Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the self-
clocking mode, both the SCLK and SDATA lines become active after RFS goes low. In the external clocking
mode, the SDATA line becomes active after RFS goes low.
21 DRDY Logic Output. A falling edge indicates that a new output word is available for transmission. The DRDY pin
will return high upon completion of transmission of a full output word. DRDY is also used to indicate when
the AD7713 has completed its on-chip calibration sequence.
22 SDATA Serial Data. Input/output with serial data being written to either the control register or the calibration regis-
ters and serial data being accessed from the control register, calibration registers, or the data register. During
an output data read operation, serial data becomes active after RFS goes low (provided DRDY is low). During a write operation, valid serial data is expected on the rising edges of SCLK when TFS is low. The output
data coding is natural binary for unipolar inputs and offset binary for bipolar inputs.
23 DV
DD
Digital Supply Voltage, 5 V. DVDD should not exceed AVDD by more than 0.3 V in normal operation.
24 DGND Ground Reference Point for Digital Circuitry.
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale (not to be confused with bipolar zero), a point 0.5 LSB below the first code
transition (000...000 to 000...001) and full scale, a point 0.5 LSB
above the last code transition (111...110 to 111...111). The error
is expressed as a percentage of full scale.
Positive Full-Scale Error
Positive full-scale error is the deviation of the last code transition
(111...110 to 111...111) from the ideal input full-scale voltage.
For AIN1(+) and AIN2(+), the ideal full-scale input voltage is
(AIN1(–) + V
/GAIN – 3/2 LSBs), where AIN(–) is either
REF
AIN1(–) or AIN2(–) as appropriate; for AIN3, the ideal full-scale
voltage is 4 ⫻ V
/GAIN – 3/2 LSBs. Positive full-scale error
REF
applies to both unipolar and bipolar analog input ranges.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
from the ideal voltage. For AIN1(+) and AIN2(+), the ideal
input voltage is (AIN1(–) + 0.5 LSB); for AIN3, the ideal input
is 0.5 LSB when operating in the unipolar mode.
Bipolar Zero Error
This is the deviation of the midscale transition (0111 ... 111 to
1000 ... 000) from the ideal input voltage. For AIN1(+) and
AIN2(+), the ideal input voltage is (AIN1(–) – 0.5 LSB); AIN3
can accommodate only unipolar input ranges.
Bipolar Negative Full-Scale Error
Positive Full-Scale Overrange
Positive full-scale overrange is the amount of overhead available
to handle input voltages on AIN1(+) and AIN2(+) inputs
greater than (AIN1(–) + V
than 4 ⫻ V
/GAIN (for example, noise peaks or excess voltages
REF
/GAIN) or on AIN3 of greater
REF
due to system gain errors in system calibration routines) without
introducing errors due to overloading the analog modulator or
to overflowing the digital filter.
Negative Full-Scale Overrange
This is the amount of overhead available to handle voltages on
AIN1(+) and AIN2(+) below (AIN1(–) – V
/GAIN) without
REF
overloading the analog modulator or overflowing the digital filter.
Offset Calibration Range
In the system calibration modes, the AD7713 calibrates its offset
with respect to the analog input. The offset calibration range
specification defines the range of voltages that the AD7713 can
accept and still calibrate offset accurately.
Full-Scale Calibration Range
This is the range of voltages that the AD7713 can accept in the
system calibration mode and still calibrate full scale correctly.
Input Span
In system calibration schemes, two voltages applied in sequence
to the AD7713’s analog input define the analog input range. The
input span specification defines the minimum and maximum
input voltages from zero to full scale that the AD7713 can accept
and still calibrate gain accurately.
This is the deviation of the first code transition from the ideal
input voltage. For AIN1(+) and AIN2(+), the ideal input voltage is (AIN1(–) – V
/GAIN + 0.5 LSB); AIN3 can only
REF
accommodate unipolar input ranges.
REV. D–8–
AD7713
CONTROL REGISTER (24 BITS)
A write to the device with the A0 input low writes data to the
control register. A read to the device with the A0 input low
accesses the contents of the control register. The control register
is 24 bits wide. When writing to the register, 24 bits of data
control register. In other words, it is not possible to write just
the first 12 bits of data into the control register. If more than 24
clock pulses are provided before TFS returns high, then all clock
pulses after the 24th clock pulse are ignored. Similarly, a read
operation from the control register should access 24 bits of data.
must be written; otherwise, the data will not be loaded to the
MSB
MD2 MD1 MD0 G2 G1 G0 CH1 CH0 WL RO BO B/U
FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0
LSB
Operating Mode
MD2 MD1 MD0 Operating Mode
000Normal Mode. This is the normal mode of operation of the device whereby a read to the device with A0 high
accesses data from the data register. This is the default condition of these bits after the internal power-on reset.
001Activate Self-Calibration. This activates self-calibration on the channel selected by CH0 and CH1. This is
a 1-step calibration sequence, and when complete, the part returns to normal mode (with MD2, MD1,
MD0 of the control registers returning to 0, 0, 0). The DRDY output indicates when this self-calibration
is complete. For this calibration type, the zero-scale calibration is done internally on shorted (zeroed)
inputs, and the full-scale calibration is done on V
REF
.
010Activate System Calibration. This activates system calibration on the channel selected by CH0 and CH1.
This is a 2-step calibration sequence, with the zero-scale calibration done first on the selected input
channel and DRDY indicating when this zero-scale calibration is complete. The part returns to normal
mode at the end of this first step in the 2-step sequence.
011Activate System Calibration. This is the second step of the system calibration sequence with full-scale
calibration being performed on the selected input channel. Once again, DRDY indicates when the fullscale calibration is complete. When this calibration is complete, the part returns to normal mode.
100Activate System Offset Calibration. This activates system offset calibration on the channel selected by CH0
and CH1. This is a 1-step calibration sequence and, when complete, the part returns to normal mode with
DRDY indicating when this system offset calibration is complete. For this calibration type, the zero-scale
calibration is done on the selected input channel, and the full-scale calibration is done internally on V
REF
.
101Activate Background Calibration. This activates background calibration on the channel selected by CH0 and
CH1. If the background calibration mode is on, the AD7713 provides continuous self-calibration of the reference and shorted (zeroed) inputs. This calibration takes place as part of the conversion sequence, extending
the conversion time and reducing the word rate by a factor of 6. Its major advantage is that the user does
not have to worry about recalibrating the device when there is a change in the ambient temperature. In
this mode, the shorted (zeroed) inputs and V
, as well as the analog input voltage, are continuously
REF
monitored, and the calibration registers of the device are updated.
110Read/Write Zero-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents of
the zero-scale calibration coefficients of the channel selected by CH0 and CH1. A write to the device with
A0 high writes data to the zero-scale calibration coefficients of the channel selected by CH0 and CH1.
The word length for reading and writing these coefficients is 24 bits, regardless of the status of the WL bit
of the control register. Therefore, when writing to the calibration register, 24 bits of data must be written;
otherwise, the new data will not be transferred to the calibration register.
111Read/Write Full-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents of
the full-scale calibration coefficients of the channel selected by CH0 and CH1. A write to the device with
A0 high writes data to the full-scale calibration coefficients of the channel selected by CH0 and CH1. The
word length for reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of
the control register. Therefore, when writing to the calibration register, 24 bits of data must be written;
otherwise, the new data will not be transferred to the calibration register.
REV. D
–9–
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